Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
8059592: Recent bugfixes in ppc64 port.
Thu, 02 Oct 2014 09:32:53 +0200
- author
- goetz
- date
- Thu, 02 Oct 2014 09:32:53 +0200
- changeset 7222
- f6bde7889409
- parent 7221
- 43ce58b4717b
- child 7225
- ff0986dac06d
8059592: Recent bugfixes in ppc64 port.
Reviewed-by: kvn
1.1 --- a/make/aix/makefiles/fastdebug.make Thu Oct 02 11:31:31 2014 -0700 1.2 +++ b/make/aix/makefiles/fastdebug.make Thu Oct 02 09:32:53 2014 +0200 1.3 @@ -67,7 +67,6 @@ 1.4 # not justified. 1.5 LFLAGS_QIPA= 1.6 1.7 -G_SUFFIX = _g 1.8 VERSION = optimized 1.9 SYSDEFS += -DASSERT -DFASTDEBUG 1.10 PICFLAGS = DEFAULT
2.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Thu Oct 02 11:31:31 2014 -0700 2.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Thu Oct 02 09:32:53 2014 +0200 2.3 @@ -268,8 +268,35 @@ 2.4 2.5 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 2.6 2.7 - MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT), 2.8 - MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT), 2.9 + // Special purpose registers 2.10 + MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 2.11 + MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 2.12 + 2.13 + MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 2.14 + MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 2.15 + 2.16 + MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 2.17 + MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 2.18 + 2.19 + MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 2.20 + MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 2.21 + 2.22 + MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 2.23 + MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 2.24 + 2.25 + MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT), 2.26 + MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT), 2.27 + MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT), 2.28 + MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT), 2.29 + MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT), 2.30 + MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT), 2.31 + MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT), 2.32 + MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT), 2.33 + 2.34 + MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT), 2.35 + MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT), 2.36 + 2.37 + MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT), 2.38 2.39 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 2.40 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 2.41 @@ -291,9 +318,6 @@ 2.42 2.43 // CTR-related opcodes 2.44 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 2.45 - MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT), 2.46 - MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT), 2.47 - 2.48 2.49 LWZ_OPCODE = (32u << OPCODE_SHIFT), 2.50 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 2.51 @@ -585,6 +609,37 @@ 2.52 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 2.53 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 2.54 2.55 + // AES (introduced with Power 8) 2.56 + VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 2.57 + VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 2.58 + VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 2.59 + VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 2.60 + VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 2.61 + 2.62 + // SHA (introduced with Power 8) 2.63 + VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 2.64 + VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 2.65 + 2.66 + // Vector Binary Polynomial Multiplication (introduced with Power 8) 2.67 + VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 2.68 + VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 2.69 + VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 2.70 + VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 2.71 + 2.72 + // Vector Permute and Xor (introduced with Power 8) 2.73 + VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 2.74 + 2.75 + // Transactional Memory instructions (introduced with Power 8) 2.76 + TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 2.77 + TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 2.78 + TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 2.79 + TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 2.80 + TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 2.81 + TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 2.82 + TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 2.83 + TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 2.84 + TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 2.85 + 2.86 // Icache and dcache related instructions 2.87 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 2.88 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 2.89 @@ -1420,6 +1475,25 @@ 2.90 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 2.91 inline void mtcr( Register s); 2.92 2.93 + // Special purpose registers 2.94 + // Exception Register 2.95 + inline void mtxer(Register s1); 2.96 + inline void mfxer(Register d); 2.97 + // Vector Register Save Register 2.98 + inline void mtvrsave(Register s1); 2.99 + inline void mfvrsave(Register d); 2.100 + // Timebase 2.101 + inline void mftb(Register d); 2.102 + // Introduced with Power 8: 2.103 + // Data Stream Control Register 2.104 + inline void mtdscr(Register s1); 2.105 + inline void mfdscr(Register d ); 2.106 + // Transactional Memory Registers 2.107 + inline void mftfhar(Register d); 2.108 + inline void mftfiar(Register d); 2.109 + inline void mftexasr(Register d); 2.110 + inline void mftexasru(Register d); 2.111 + 2.112 // PPC 1, section 2.4.1 Branch Instructions 2.113 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 2.114 inline void b( Label& L); 2.115 @@ -1860,6 +1934,39 @@ 2.116 inline void mtvscr( VectorRegister b); 2.117 inline void mfvscr( VectorRegister d); 2.118 2.119 + // AES (introduced with Power 8) 2.120 + inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2.121 + inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2.122 + inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2.123 + inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2.124 + inline void vsbox( VectorRegister d, VectorRegister a); 2.125 + 2.126 + // SHA (introduced with Power 8) 2.127 + // Not yet implemented. 2.128 + 2.129 + // Vector Binary Polynomial Multiplication (introduced with Power 8) 2.130 + inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2.131 + inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2.132 + inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2.133 + inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2.134 + 2.135 + // Vector Permute and Xor (introduced with Power 8) 2.136 + inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2.137 + 2.138 + // Transactional Memory instructions (introduced with Power 8) 2.139 + inline void tbegin_(); // R=0 2.140 + inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2.141 + inline void tend_(); // A=0 2.142 + inline void tendall_(); // A=1 2.143 + inline void tabort_(Register a); 2.144 + inline void tabortwc_(int t, Register a, Register b); 2.145 + inline void tabortwci_(int t, Register a, int si); 2.146 + inline void tabortdc_(int t, Register a, Register b); 2.147 + inline void tabortdci_(int t, Register a, int si); 2.148 + inline void tsuspend_(); // tsr with L=0 2.149 + inline void tresume_(); // tsr with L=1 2.150 + inline void tcheck(int f); 2.151 + 2.152 // The following encoders use r0 as second operand. These instructions 2.153 // read r0 as '0'. 2.154 inline void lwzx( Register d, Register s2);
3.1 --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp Thu Oct 02 11:31:31 2014 -0700 3.2 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp Thu Oct 02 09:32:53 2014 +0200 3.3 @@ -312,6 +312,25 @@ 3.4 { emit_int32(MCRF_OPCODE | bf(crd) | bfa(cra)); } 3.5 inline void Assembler::mtcr( Register s) { Assembler::mtcrf(0xff, s); } 3.6 3.7 +// Special purpose registers 3.8 +// Exception Register 3.9 +inline void Assembler::mtxer(Register s1) { emit_int32(MTXER_OPCODE | rs(s1)); } 3.10 +inline void Assembler::mfxer(Register d ) { emit_int32(MFXER_OPCODE | rt(d)); } 3.11 +// Vector Register Save Register 3.12 +inline void Assembler::mtvrsave(Register s1) { emit_int32(MTVRSAVE_OPCODE | rs(s1)); } 3.13 +inline void Assembler::mfvrsave(Register d ) { emit_int32(MFVRSAVE_OPCODE | rt(d)); } 3.14 +// Timebase 3.15 +inline void Assembler::mftb(Register d ) { emit_int32(MFTB_OPCODE | rt(d)); } 3.16 +// Introduced with Power 8: 3.17 +// Data Stream Control Register 3.18 +inline void Assembler::mtdscr(Register s1) { emit_int32(MTDSCR_OPCODE | rs(s1)); } 3.19 +inline void Assembler::mfdscr(Register d ) { emit_int32(MFDSCR_OPCODE | rt(d)); } 3.20 +// Transactional Memory Registers 3.21 +inline void Assembler::mftfhar(Register d ) { emit_int32(MFTFHAR_OPCODE | rt(d)); } 3.22 +inline void Assembler::mftfiar(Register d ) { emit_int32(MFTFIAR_OPCODE | rt(d)); } 3.23 +inline void Assembler::mftexasr(Register d ) { emit_int32(MFTEXASR_OPCODE | rt(d)); } 3.24 +inline void Assembler::mftexasru(Register d ) { emit_int32(MFTEXASRU_OPCODE | rt(d)); } 3.25 + 3.26 // SAP JVM 2006-02-13 PPC branch instruction. 3.27 // PPC 1, section 2.4.1 Branch Instructions 3.28 inline void Assembler::b( address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(0), rt); } 3.29 @@ -735,6 +754,39 @@ 3.30 inline void Assembler::mtvscr( VectorRegister b) { emit_int32( MTVSCR_OPCODE | vrb(b)); } 3.31 inline void Assembler::mfvscr( VectorRegister d) { emit_int32( MFVSCR_OPCODE | vrt(d)); } 3.32 3.33 +// AES (introduced with Power 8) 3.34 +inline void Assembler::vcipher( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHER_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.35 +inline void Assembler::vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHERLAST_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.36 +inline void Assembler::vncipher( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHER_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.37 +inline void Assembler::vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHERLAST_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.38 +inline void Assembler::vsbox( VectorRegister d, VectorRegister a) { emit_int32( VSBOX_OPCODE | vrt(d) | vra(a) ); } 3.39 + 3.40 +// SHA (introduced with Power 8) 3.41 +// Not yet implemented. 3.42 + 3.43 +// Vector Binary Polynomial Multiplication (introduced with Power 8) 3.44 +inline void Assembler::vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMB_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.45 +inline void Assembler::vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMD_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.46 +inline void Assembler::vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMH_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.47 +inline void Assembler::vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMW_OPCODE | vrt(d) | vra(a) | vrb(b)); } 3.48 + 3.49 +// Vector Permute and Xor (introduced with Power 8) 3.50 +inline void Assembler::vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VPMSUMW_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); } 3.51 + 3.52 +// Transactional Memory instructions (introduced with Power 8) 3.53 +inline void Assembler::tbegin_() { emit_int32( TBEGIN_OPCODE | rc(1)); } 3.54 +inline void Assembler::tbeginrot_() { emit_int32( TBEGIN_OPCODE | /*R=1*/ 1u << (31-10) | rc(1)); } 3.55 +inline void Assembler::tend_() { emit_int32( TEND_OPCODE | rc(1)); } 3.56 +inline void Assembler::tendall_() { emit_int32( TEND_OPCODE | /*A=1*/ 1u << (31-6) | rc(1)); } 3.57 +inline void Assembler::tabort_(Register a) { emit_int32( TABORT_OPCODE | ra(a) | rc(1)); } 3.58 +inline void Assembler::tabortwc_(int t, Register a, Register b) { emit_int32( TABORTWC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); } 3.59 +inline void Assembler::tabortwci_(int t, Register a, int si) { emit_int32( TABORTWCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); } 3.60 +inline void Assembler::tabortdc_(int t, Register a, Register b) { emit_int32( TABORTDC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); } 3.61 +inline void Assembler::tabortdci_(int t, Register a, int si) { emit_int32( TABORTDCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); } 3.62 +inline void Assembler::tsuspend_() { emit_int32( TSR_OPCODE | rc(1)); } 3.63 +inline void Assembler::tresume_() { emit_int32( TSR_OPCODE | /*L=1*/ 1u << (31-10) | rc(1)); } 3.64 +inline void Assembler::tcheck(int f) { emit_int32( TCHECK_OPCODE | bf(f)); } 3.65 + 3.66 // ra0 version 3.67 inline void Assembler::lwzx( Register d, Register s2) { emit_int32( LWZX_OPCODE | rt(d) | rb(s2));} 3.68 inline void Assembler::lwz( Register d, int si16 ) { emit_int32( LWZ_OPCODE | rt(d) | d1(si16));}
4.1 --- a/src/cpu/ppc/vm/globalDefinitions_ppc.hpp Thu Oct 02 11:31:31 2014 -0700 4.2 +++ b/src/cpu/ppc/vm/globalDefinitions_ppc.hpp Thu Oct 02 09:32:53 2014 +0200 4.3 @@ -37,6 +37,8 @@ 4.4 // signatures accordingly. 4.5 const bool CCallingConventionRequiresIntsAsLongs = true; 4.6 4.7 +#define SUPPORTS_NATIVE_CX8 4.8 + 4.9 // The PPC CPUs are NOT multiple-copy-atomic. 4.10 #define CPU_NOT_MULTIPLE_COPY_ATOMIC 4.11
5.1 --- a/src/cpu/ppc/vm/interp_masm_ppc_64.cpp Thu Oct 02 11:31:31 2014 -0700 5.2 +++ b/src/cpu/ppc/vm/interp_masm_ppc_64.cpp Thu Oct 02 09:32:53 2014 +0200 5.3 @@ -25,7 +25,6 @@ 5.4 5.5 5.6 #include "precompiled.hpp" 5.7 -#include "asm/assembler.hpp" 5.8 #include "asm/macroAssembler.inline.hpp" 5.9 #include "interp_masm_ppc_64.hpp" 5.10 #include "interpreter/interpreterRuntime.hpp"
6.1 --- a/src/cpu/ppc/vm/interpreter_ppc.cpp Thu Oct 02 11:31:31 2014 -0700 6.2 +++ b/src/cpu/ppc/vm/interpreter_ppc.cpp Thu Oct 02 09:32:53 2014 +0200 6.3 @@ -24,7 +24,6 @@ 6.4 */ 6.5 6.6 #include "precompiled.hpp" 6.7 -#include "asm/assembler.hpp" 6.8 #include "asm/macroAssembler.inline.hpp" 6.9 #include "interpreter/bytecodeHistogram.hpp" 6.10 #include "interpreter/interpreter.hpp"
7.1 --- a/src/cpu/ppc/vm/macroAssembler_ppc.cpp Thu Oct 02 11:31:31 2014 -0700 7.2 +++ b/src/cpu/ppc/vm/macroAssembler_ppc.cpp Thu Oct 02 09:32:53 2014 +0200 7.3 @@ -2365,7 +2365,7 @@ 7.4 #endif // INCLUDE_ALL_GCS 7.5 7.6 // Values for last_Java_pc, and last_Java_sp must comply to the rules 7.7 -// in frame_ppc64.hpp. 7.8 +// in frame_ppc.hpp. 7.9 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) { 7.10 // Always set last_Java_pc and flags first because once last_Java_sp 7.11 // is visible has_last_Java_frame is true and users will look at the 7.12 @@ -2492,6 +2492,7 @@ 7.13 } 7.14 7.15 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 7.16 + assert(dst != R0, "Dst reg may not be R0, as R0 is used here."); 7.17 if (src == noreg) src = dst; 7.18 Register shifted_src = src; 7.19 if (Universe::narrow_klass_shift() != 0 || 7.20 @@ -2526,14 +2527,11 @@ 7.21 7.22 void MacroAssembler::reinit_heapbase(Register d, Register tmp) { 7.23 if (Universe::heap() != NULL) { 7.24 - if (Universe::narrow_oop_base() == NULL) { 7.25 - Assembler::xorr(R30, R30, R30); 7.26 - } else { 7.27 - load_const(R30, Universe::narrow_ptrs_base(), tmp); 7.28 - } 7.29 + load_const_optimized(R30, Universe::narrow_ptrs_base(), tmp); 7.30 } else { 7.31 - load_const(R30, Universe::narrow_ptrs_base_addr(), tmp); 7.32 - ld(R30, 0, R30); 7.33 + // Heap not yet allocated. Load indirectly. 7.34 + int simm16_offset = load_const_optimized(R30, Universe::narrow_ptrs_base_addr(), tmp, true); 7.35 + ld(R30, simm16_offset, R30); 7.36 } 7.37 } 7.38
8.1 --- a/src/cpu/ppc/vm/ppc.ad Thu Oct 02 11:31:31 2014 -0700 8.2 +++ b/src/cpu/ppc/vm/ppc.ad Thu Oct 02 09:32:53 2014 +0200 8.3 @@ -1249,6 +1249,7 @@ 8.4 8.5 // Emit the trampoline stub which will be related to the branch-and-link below. 8.6 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 8.7 + if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full. 8.8 __ relocate(rtype); 8.9 } 8.10 8.11 @@ -1412,7 +1413,7 @@ 8.12 while (bang_offset <= bang_end) { 8.13 // Need at least one stack bang at end of shadow zone. 8.14 8.15 - // Again I had to copy code, this time from assembler_ppc64.cpp, 8.16 + // Again I had to copy code, this time from assembler_ppc.cpp, 8.17 // bang_stack_with_offset - see there for comments. 8.18 8.19 // Stack grows down, caller passes positive offset. 8.20 @@ -2002,7 +2003,7 @@ 8.21 8.22 // Inline_cache contains a klass. 8.23 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 8.24 - Register receiver_klass = R0; // tmp 8.25 + Register receiver_klass = R12_scratch2; // tmp 8.26 8.27 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 8.28 assert(R11_scratch1 == R11, "need prologue scratch register"); 8.29 @@ -3486,6 +3487,7 @@ 8.30 8.31 // Emit the trampoline stub which will be related to the branch-and-link below. 8.32 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 8.33 + if (Compile::current()->env()->failing()) { return; } // Code cache may be full. 8.34 __ relocate(_optimized_virtual ? 8.35 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); 8.36 } 8.37 @@ -3529,6 +3531,7 @@ 8.38 8.39 // Emit the trampoline stub which will be related to the branch-and-link below. 8.40 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 8.41 + if (ra_->C->env()->failing()) { return; } // Code cache may be full. 8.42 assert(_optimized_virtual, "methodHandle call should be a virtual call"); 8.43 __ relocate(relocInfo::opt_virtual_call_type); 8.44 } 8.45 @@ -3579,9 +3582,7 @@ 8.46 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 8.47 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 8.48 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 8.49 - 8.50 - if (ra_->C->env()->failing()) 8.51 - return; 8.52 + if (ra_->C->env()->failing()) { return; } // Code cache may be full. 8.53 8.54 // Build relocation at call site with ic position as data. 8.55 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 8.56 @@ -5640,19 +5641,6 @@ 8.57 ins_pipe(pipe_class_memory); 8.58 %} 8.59 8.60 -//// Load compressed klass and decode it if narrow_klass_shift == 0. 8.61 -//// TODO: will narrow_klass_shift ever be 0? 8.62 -//instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{ 8.63 -// match(Set dst (DecodeNKlass (LoadNKlass mem))); 8.64 -// predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*); 8.65 -// ins_cost(MEMORY_REF_COST); 8.66 -// 8.67 -// format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %} 8.68 -// size(4); 8.69 -// ins_encode( enc_lwz(dst, mem) ); 8.70 -// ins_pipe(pipe_class_memory); 8.71 -//%} 8.72 - 8.73 // Load Klass Pointer 8.74 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 8.75 match(Set dst (LoadKlass mem)); 8.76 @@ -6072,11 +6060,15 @@ 8.77 %} 8.78 %} 8.79 8.80 -instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{ 8.81 +// We have seen a safepoint between the hi and lo parts, and this node was handled 8.82 +// as an oop. Therefore this needs a match rule so that build_oop_map knows this is 8.83 +// not a narrow oop. 8.84 +instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 8.85 + match(Set dst src); 8.86 effect(DEF dst, USE src); 8.87 ins_cost(DEFAULT_COST); 8.88 8.89 - format %{ "LIS $dst, $src \t// narrow oop hi" %} 8.90 + format %{ "LIS $dst, $src \t// narrow klass hi" %} 8.91 size(4); 8.92 ins_encode %{ 8.93 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 8.94 @@ -6086,6 +6078,21 @@ 8.95 ins_pipe(pipe_class_default); 8.96 %} 8.97 8.98 +// As loadConNKlass_hi this must be recognized as narrow klass, not oop! 8.99 +instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 8.100 + match(Set dst src1); 8.101 + effect(TEMP src2); 8.102 + ins_cost(DEFAULT_COST); 8.103 + 8.104 + format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 8.105 + size(4); 8.106 + ins_encode %{ 8.107 + // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8.108 + __ clrldi($dst$$Register, $src2$$Register, 0x20); 8.109 + %} 8.110 + ins_pipe(pipe_class_default); 8.111 +%} 8.112 + 8.113 // This needs a match rule so that build_oop_map knows this is 8.114 // not a narrow oop. 8.115 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 8.116 @@ -6093,10 +6100,10 @@ 8.117 effect(TEMP src2); 8.118 ins_cost(DEFAULT_COST); 8.119 8.120 - format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %} 8.121 - size(4); 8.122 - ins_encode %{ 8.123 - // TODO: PPC port $archOpcode(ppc64Opcode_addi); 8.124 + format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 8.125 + size(4); 8.126 + ins_encode %{ 8.127 + // TODO: PPC port $archOpcode(ppc64Opcode_ori); 8.128 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 8.129 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 8.130 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 8.131 @@ -6127,10 +6134,11 @@ 8.132 MachNode *m2 = m1; 8.133 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 8.134 // Value might be 1-extended. Mask out these bits. 8.135 - m2 = new (C) clearMs32bNode(); 8.136 + m2 = new (C) loadConNKlass_maskNode(); 8.137 m2->add_req(NULL, m1); 8.138 m2->_opnds[0] = op_dst; 8.139 - m2->_opnds[1] = op_dst; 8.140 + m2->_opnds[1] = op_src; 8.141 + m2->_opnds[2] = op_dst; 8.142 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 8.143 nodes->push(m2); 8.144 } 8.145 @@ -6975,7 +6983,7 @@ 8.146 size(4); 8.147 ins_encode %{ 8.148 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8.149 - __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 8.150 + __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 8.151 %} 8.152 ins_pipe(pipe_class_default); 8.153 %}
9.1 --- a/src/cpu/ppc/vm/stubGenerator_ppc.cpp Thu Oct 02 11:31:31 2014 -0700 9.2 +++ b/src/cpu/ppc/vm/stubGenerator_ppc.cpp Thu Oct 02 09:32:53 2014 +0200 9.3 @@ -24,7 +24,6 @@ 9.4 */ 9.5 9.6 #include "precompiled.hpp" 9.7 -#include "asm/assembler.hpp" 9.8 #include "asm/macroAssembler.inline.hpp" 9.9 #include "interpreter/interpreter.hpp" 9.10 #include "nativeInst_ppc.hpp" 9.11 @@ -39,9 +38,6 @@ 9.12 #include "runtime/stubCodeGenerator.hpp" 9.13 #include "runtime/stubRoutines.hpp" 9.14 #include "utilities/top.hpp" 9.15 -#ifdef COMPILER2 9.16 -#include "opto/runtime.hpp" 9.17 -#endif 9.18 #include "runtime/thread.inline.hpp" 9.19 9.20 #define __ _masm-> 9.21 @@ -216,7 +212,7 @@ 9.22 { 9.23 BLOCK_COMMENT("Call frame manager or native entry."); 9.24 // Call frame manager or native entry. 9.25 - Register r_new_arg_entry = R14; // PPC_state; 9.26 + Register r_new_arg_entry = R14; 9.27 assert_different_registers(r_new_arg_entry, r_top_of_arguments_addr, 9.28 r_arg_method, r_arg_thread); 9.29
10.1 --- a/src/cpu/ppc/vm/templateTable_ppc_64.cpp Thu Oct 02 11:31:31 2014 -0700 10.2 +++ b/src/cpu/ppc/vm/templateTable_ppc_64.cpp Thu Oct 02 09:32:53 2014 +0200 10.3 @@ -352,7 +352,6 @@ 10.4 __ sldi(Rscratch1, Rscratch1, LogBytesPerWord); 10.5 __ cmpdi(CCR0, Rscratch2, JVM_CONSTANT_Integer); 10.6 __ bne(CCR0, notInt); 10.7 - __ isync(); // Order load of constant wrt. tags. 10.8 __ lwax(R17_tos, Rcpool, Rscratch1); 10.9 __ push(itos); 10.10 __ b(exit); 10.11 @@ -364,7 +363,6 @@ 10.12 __ cmpdi(CCR0, Rscratch2, JVM_CONSTANT_Float); 10.13 __ asm_assert_eq("unexpected type", 0x8765); 10.14 #endif 10.15 - __ isync(); // Order load of constant wrt. tags. 10.16 __ lfsx(F15_ftos, Rcpool, Rscratch1); 10.17 __ push(ftos); 10.18 10.19 @@ -423,13 +421,11 @@ 10.20 // Check out Conversions.java for an example. 10.21 // Also ConstantPool::header_size() is 20, which makes it very difficult 10.22 // to double-align double on the constant pool. SG, 11/7/97 10.23 - __ isync(); // Order load of constant wrt. tags. 10.24 __ lfdx(F15_ftos, Rcpool, Rindex); 10.25 __ push(dtos); 10.26 __ b(Lexit); 10.27 10.28 __ bind(Llong); 10.29 - __ isync(); // Order load of constant wrt. tags. 10.30 __ ldx(R17_tos, Rcpool, Rindex); 10.31 __ push(ltos); 10.32
11.1 --- a/src/os_cpu/linux_ppc/vm/prefetch_linux_ppc.inline.hpp Thu Oct 02 11:31:31 2014 -0700 11.2 +++ b/src/os_cpu/linux_ppc/vm/prefetch_linux_ppc.inline.hpp Thu Oct 02 09:32:53 2014 +0200 11.3 @@ -47,4 +47,4 @@ 11.4 ); 11.5 } 11.6 11.7 -#endif // OS_CPU_LINUX_PPC_VM_PREFETCH_LINUX_OJDKPPC_HPP 11.8 +#endif // OS_CPU_LINUX_PPC_VM_PREFETCH_LINUX_PPC_INLINE_HPP
