1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Thu Oct 02 11:31:31 2014 -0700
1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Thu Oct 02 09:32:53 2014 +0200
1.3 @@ -268,8 +268,35 @@
1.4
1.5 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
1.6
1.7 - MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT),
1.8 - MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT),
1.9 + // Special purpose registers
1.10 + MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
1.11 + MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
1.12 +
1.13 + MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
1.14 + MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
1.15 +
1.16 + MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
1.17 + MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
1.18 +
1.19 + MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
1.20 + MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
1.21 +
1.22 + MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
1.23 + MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
1.24 +
1.25 + MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT),
1.26 + MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT),
1.27 + MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT),
1.28 + MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT),
1.29 + MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT),
1.30 + MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT),
1.31 + MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT),
1.32 + MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT),
1.33 +
1.34 + MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT),
1.35 + MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT),
1.36 +
1.37 + MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT),
1.38
1.39 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
1.40 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
1.41 @@ -291,9 +318,6 @@
1.42
1.43 // CTR-related opcodes
1.44 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
1.45 - MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
1.46 - MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
1.47 -
1.48
1.49 LWZ_OPCODE = (32u << OPCODE_SHIFT),
1.50 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
1.51 @@ -585,6 +609,37 @@
1.52 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
1.53 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
1.54
1.55 + // AES (introduced with Power 8)
1.56 + VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
1.57 + VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
1.58 + VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
1.59 + VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
1.60 + VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
1.61 +
1.62 + // SHA (introduced with Power 8)
1.63 + VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
1.64 + VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
1.65 +
1.66 + // Vector Binary Polynomial Multiplication (introduced with Power 8)
1.67 + VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
1.68 + VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
1.69 + VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
1.70 + VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
1.71 +
1.72 + // Vector Permute and Xor (introduced with Power 8)
1.73 + VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
1.74 +
1.75 + // Transactional Memory instructions (introduced with Power 8)
1.76 + TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
1.77 + TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
1.78 + TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
1.79 + TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
1.80 + TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
1.81 + TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
1.82 + TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
1.83 + TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
1.84 + TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
1.85 +
1.86 // Icache and dcache related instructions
1.87 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
1.88 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
1.89 @@ -1420,6 +1475,25 @@
1.90 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1.91 inline void mtcr( Register s);
1.92
1.93 + // Special purpose registers
1.94 + // Exception Register
1.95 + inline void mtxer(Register s1);
1.96 + inline void mfxer(Register d);
1.97 + // Vector Register Save Register
1.98 + inline void mtvrsave(Register s1);
1.99 + inline void mfvrsave(Register d);
1.100 + // Timebase
1.101 + inline void mftb(Register d);
1.102 + // Introduced with Power 8:
1.103 + // Data Stream Control Register
1.104 + inline void mtdscr(Register s1);
1.105 + inline void mfdscr(Register d );
1.106 + // Transactional Memory Registers
1.107 + inline void mftfhar(Register d);
1.108 + inline void mftfiar(Register d);
1.109 + inline void mftexasr(Register d);
1.110 + inline void mftexasru(Register d);
1.111 +
1.112 // PPC 1, section 2.4.1 Branch Instructions
1.113 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1.114 inline void b( Label& L);
1.115 @@ -1860,6 +1934,39 @@
1.116 inline void mtvscr( VectorRegister b);
1.117 inline void mfvscr( VectorRegister d);
1.118
1.119 + // AES (introduced with Power 8)
1.120 + inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
1.121 + inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1.122 + inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
1.123 + inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1.124 + inline void vsbox( VectorRegister d, VectorRegister a);
1.125 +
1.126 + // SHA (introduced with Power 8)
1.127 + // Not yet implemented.
1.128 +
1.129 + // Vector Binary Polynomial Multiplication (introduced with Power 8)
1.130 + inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
1.131 + inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
1.132 + inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
1.133 + inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
1.134 +
1.135 + // Vector Permute and Xor (introduced with Power 8)
1.136 + inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1.137 +
1.138 + // Transactional Memory instructions (introduced with Power 8)
1.139 + inline void tbegin_(); // R=0
1.140 + inline void tbeginrot_(); // R=1 Rollback-Only Transaction
1.141 + inline void tend_(); // A=0
1.142 + inline void tendall_(); // A=1
1.143 + inline void tabort_(Register a);
1.144 + inline void tabortwc_(int t, Register a, Register b);
1.145 + inline void tabortwci_(int t, Register a, int si);
1.146 + inline void tabortdc_(int t, Register a, Register b);
1.147 + inline void tabortdci_(int t, Register a, int si);
1.148 + inline void tsuspend_(); // tsr with L=0
1.149 + inline void tresume_(); // tsr with L=1
1.150 + inline void tcheck(int f);
1.151 +
1.152 // The following encoders use r0 as second operand. These instructions
1.153 // read r0 as '0'.
1.154 inline void lwzx( Register d, Register s2);
