Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 13:38:41 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 13:51:09 2016 +0800
     1.3 @@ -2804,7 +2804,7 @@
     1.4          } else {
     1.5             __ move(T9, disp);   
     1.6             if( UseLoongsonISA ) {
     1.7 -              gsldxc1(dst_reg, as_Register(base), T9, 0);
     1.8 +              __ gsldxc1(dst_reg, as_Register(base), T9, 0);
     1.9             } else {
    1.10                __ addu(AT, as_Register(base), T9); 
    1.11                __ ldc1(dst_reg, AT, 0);
    1.12 @@ -2824,21 +2824,34 @@
    1.13       guarantee(scale == 0, "scale is not zero !");
    1.14  
    1.15       if( index != 0 ) {
    1.16 -        __ daddu(AT, as_Register(base), as_Register(index));
    1.17          if( Assembler::is_simm16(disp) ) { 
    1.18 -           __ sdc1(src_reg, AT, disp);
    1.19 +           if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
    1.20 +              __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
    1.21 +           } else {
    1.22 +              __ daddu(AT, as_Register(base), as_Register(index));
    1.23 +              __ sdc1(src_reg, AT, disp);
    1.24 +           }
    1.25          } else {
    1.26 +           __ daddu(AT, as_Register(base), as_Register(index));
    1.27             __ move(T9, disp);
    1.28 -           __ addu(AT, AT, T9); 
    1.29 -           __ sdc1(src_reg, AT, 0);
    1.30 +           if( UseLoongsonISA ) {
    1.31 +              __ gssdxc1(src_reg, AT, T9, 0);
    1.32 +           } else {
    1.33 +              __ addu(AT, AT, T9); 
    1.34 +              __ sdc1(src_reg, AT, 0);
    1.35 +           }
    1.36          }    
    1.37       } else {
    1.38          if( Assembler::is_simm16(disp) ) { 
    1.39             __ sdc1(src_reg, as_Register(base), disp);
    1.40          } else {
    1.41             __ move(T9, disp);   
    1.42 -           __ addu(AT, as_Register(base), T9); 
    1.43 -           __ sdc1(src_reg, AT, 0);
    1.44 +           if( UseLoongsonISA ) {
    1.45 +              __ gssdxc1(src_reg, as_Register(base), T9, 0);
    1.46 +           } else {
    1.47 +              __ addu(AT, as_Register(base), T9); 
    1.48 +              __ sdc1(src_reg, AT, 0);
    1.49 +           }
    1.50          }    
    1.51       }
    1.52    %}