# HG changeset patch
# User fujie
# Date 1471499469 -28800
# Node ID d8e0aa0ab46046c82a1a5851234e9533ec956710
# Parent  61c429e80c9603d7a710c0e183dd22b337ae706f
Enable gssdxc1 in store_D_reg_enc for Loongson processors.

diff -r 61c429e80c96 -r d8e0aa0ab460 src/cpu/mips/vm/mips_64.ad
--- a/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 13:38:41 2016 +0800
+++ b/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 13:51:09 2016 +0800
@@ -2804,7 +2804,7 @@
         } else {
            __ move(T9, disp);   
            if( UseLoongsonISA ) {
-              gsldxc1(dst_reg, as_Register(base), T9, 0);
+              __ gsldxc1(dst_reg, as_Register(base), T9, 0);
            } else {
               __ addu(AT, as_Register(base), T9); 
               __ ldc1(dst_reg, AT, 0);
@@ -2824,21 +2824,34 @@
      guarantee(scale == 0, "scale is not zero !");
 
      if( index != 0 ) {
-        __ daddu(AT, as_Register(base), as_Register(index));
         if( Assembler::is_simm16(disp) ) { 
-           __ sdc1(src_reg, AT, disp);
+           if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
+              __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
+           } else {
+              __ daddu(AT, as_Register(base), as_Register(index));
+              __ sdc1(src_reg, AT, disp);
+           }
         } else {
+           __ daddu(AT, as_Register(base), as_Register(index));
            __ move(T9, disp);
-           __ addu(AT, AT, T9); 
-           __ sdc1(src_reg, AT, 0);
+           if( UseLoongsonISA ) {
+              __ gssdxc1(src_reg, AT, T9, 0);
+           } else {
+              __ addu(AT, AT, T9); 
+              __ sdc1(src_reg, AT, 0);
+           }
         }    
      } else {
         if( Assembler::is_simm16(disp) ) { 
            __ sdc1(src_reg, as_Register(base), disp);
         } else {
            __ move(T9, disp);   
-           __ addu(AT, as_Register(base), T9); 
-           __ sdc1(src_reg, AT, 0);
+           if( UseLoongsonISA ) {
+              __ gssdxc1(src_reg, as_Register(base), T9, 0);
+           } else {
+              __ addu(AT, as_Register(base), T9); 
+              __ sdc1(src_reg, AT, 0);
+           }
         }    
      }
   %}