Enable gsldxc1 in load_D_enc for Loongson processors.

Thu, 18 Aug 2016 13:38:41 +0800

author
fujie
date
Thu, 18 Aug 2016 13:38:41 +0800
changeset 80
61c429e80c96
parent 79
3260e336f81c
child 81
d8e0aa0ab460

Enable gsldxc1 in load_D_enc for Loongson processors.

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 11:54:02 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Aug 18 13:38:41 2016 +0800
     1.3 @@ -2781,21 +2781,34 @@
     1.4       guarantee(scale == 0, "scale is not zero !");
     1.5  
     1.6       if( index != 0 ) {
     1.7 -        __ daddu(AT, as_Register(base), as_Register(index));
     1.8          if( Assembler::is_simm16(disp) ) { 
     1.9 -           __ ldc1(dst_reg, AT, disp);
    1.10 +           if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
    1.11 +              __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
    1.12 +           } else {
    1.13 +              __ daddu(AT, as_Register(base), as_Register(index));
    1.14 +              __ ldc1(dst_reg, AT, disp);
    1.15 +           }
    1.16          } else {
    1.17 +           __ daddu(AT, as_Register(base), as_Register(index));
    1.18             __ move(T9, disp);
    1.19 -           __ addu(AT, AT, T9); 
    1.20 -           __ ldc1(dst_reg, AT, 0);
    1.21 +           if( UseLoongsonISA ) {
    1.22 +              __ gsldxc1(dst_reg, AT, T9, 0);
    1.23 +           } else {
    1.24 +              __ addu(AT, AT, T9); 
    1.25 +              __ ldc1(dst_reg, AT, 0);
    1.26 +           }
    1.27          }    
    1.28       } else {
    1.29          if( Assembler::is_simm16(disp) ) { 
    1.30             __ ldc1(dst_reg, as_Register(base), disp);
    1.31          } else {
    1.32             __ move(T9, disp);   
    1.33 -           __ addu(AT, as_Register(base), T9); 
    1.34 -           __ ldc1(dst_reg, AT, 0);
    1.35 +           if( UseLoongsonISA ) {
    1.36 +              gsldxc1(dst_reg, as_Register(base), T9, 0);
    1.37 +           } else {
    1.38 +              __ addu(AT, as_Register(base), T9); 
    1.39 +              __ ldc1(dst_reg, AT, 0);
    1.40 +           }
    1.41          }    
    1.42       }
    1.43    %}

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