Mercurial > jdk8-mips64-public > hotspot / file comparison

comparison: src/share/vm/c1/c1_LIR.cpp

src/share/vm/c1/c1_LIR.cpp

changeset 9138
b56ab8e56604
parent 9126
bc5b8e3dcb6b
child 9142
87ee44a01d68
equal deleted inserted replaced
9137:dc1769738300 9138:b56ab8e56604
59 return FrameMap::nr2xmmreg(xmm_regnrLo()); 59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 } 60 }
61 61
62 #endif // X86 62 #endif // X86
63 63
64 #if defined(SPARC) || defined(PPC) || defined(MIPS64) 64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
65 65
66 FloatRegister LIR_OprDesc::as_float_reg() const { 66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr()); 67 return FrameMap::nr2floatreg(fpu_regnr());
68 } 68 }
69 69
147 } 147 }
148 148
149 149
150 #ifndef PRODUCT 150 #ifndef PRODUCT
151 void LIR_Address::verify0() const { 151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS64) 152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif 155 #endif
156 #ifdef _LP64 156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand"); 157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS64 159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses"); 161 "wrong type for addresses");
162 #endif 162 #endif
163 #else 163 #else
164 assert(base()->is_single_cpu(), "wrong base operand"); 164 assert(base()->is_single_cpu(), "wrong base operand");
304 } 304 }
305 #endif 305 #endif
306 } 306 }
307 307
308 308
309 #ifndef MIPS64 309 #ifndef MIPS
310 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 310 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
311 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 311 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
312 , _cond(cond) 312 , _cond(cond)
313 , _type(type) 313 , _type(type)
314 , _label(block->label()) 314 , _label(block->label())
615 case lir_cond_float_branch: // may have info, input and result register always invalid 615 case lir_cond_float_branch: // may have info, input and result register always invalid
616 { 616 {
617 assert(op->as_OpBranch() != NULL, "must be"); 617 assert(op->as_OpBranch() != NULL, "must be");
618 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 618 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
619 619
620 #ifdef MIPS64 620 #ifdef MIPS
621 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1); 621 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
622 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2); 622 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
623 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1); 623 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
624 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2); 624 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
625 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3); 625 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
646 } 646 }
647 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 647 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
648 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 648 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
649 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 649 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
650 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 650 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
651 #ifdef MIPS64 651 #ifdef MIPS
652 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5); 652 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
653 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6); 653 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
654 #endif 654 #endif
655 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 655 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
656 do_stub(opAllocObj->_stub); 656 do_stub(opAllocObj->_stub);
671 break; 671 break;
672 } 672 }
673 673
674 674
675 // LIR_Op2 675 // LIR_Op2
676 #ifdef MIPS64 676 #ifdef MIPS
677 case lir_null_check_for_branch: 677 case lir_null_check_for_branch:
678 #else 678 #else
679 case lir_cmp: 679 case lir_cmp:
680 #endif 680 #endif
681 case lir_cmp_l2i: 681 case lir_cmp_l2i:
843 843
844 break; 844 break;
845 } 845 }
846 846
847 // LIR_Op3 847 // LIR_Op3
848 #ifdef MIPS64 848 #ifdef MIPS
849 case lir_frem: 849 case lir_frem:
850 #endif 850 #endif
851 case lir_idiv: 851 case lir_idiv:
852 case lir_irem: { 852 case lir_irem: {
853 assert(op->as_Op3() != NULL, "must be"); 853 assert(op->as_Op3() != NULL, "must be");
930 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 930 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
931 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 931 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
932 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 932 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
933 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 933 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
934 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 934 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
935 #ifndef MIPS64 935 #ifndef MIPS
936 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 936 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
937 #endif 937 #endif
938 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 938 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
939 939
940 // the implementation of arraycopy always has a call into the runtime 940 // the implementation of arraycopy always has a call into the runtime
1047 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 1047 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1048 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 1048 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1049 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 1049 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1050 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 1050 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1051 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 1051 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1052 #ifdef MIPS64 1052 #ifdef MIPS
1053 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5); 1053 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1054 #endif 1054 #endif
1055 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 1055 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1056 do_stub(opAllocArray->_stub); 1056 do_stub(opAllocArray->_stub);
1057 break; 1057 break;
1320 patch_code, 1320 patch_code,
1321 info, lir_move_volatile)); 1321 info, lir_move_volatile));
1322 } 1322 }
1323 1323
1324 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1324 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1325 #ifdef MIPS64 1325 #ifdef MIPS
1326 add(base, offset, base); 1326 add(base, offset, base);
1327 offset = 0; 1327 offset = 0;
1328 #endif 1328 #endif
1329 append(new LIR_Op1( 1329 append(new LIR_Op1(
1330 lir_move, 1330 lir_move,
1386 info, 1386 info,
1387 lir_move_volatile)); 1387 lir_move_volatile));
1388 } 1388 }
1389 1389
1390 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1390 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1391 #ifdef MIPS64 1391 #ifdef MIPS
1392 add(base, offset, base); 1392 add(base, offset, base);
1393 offset = 0; 1393 offset = 0;
1394 #endif 1394 #endif
1395 append(new LIR_Op1( 1395 append(new LIR_Op1(
1396 lir_move, 1396 lir_move,
1399 type, 1399 type,
1400 patch_code, 1400 patch_code,
1401 info, lir_move_volatile)); 1401 info, lir_move_volatile));
1402 } 1402 }
1403 1403
1404 #ifdef MIPS64 1404 #ifdef MIPS
1405 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1405 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1406 append(new LIR_Op3( 1406 append(new LIR_Op3(
1407 lir_frem, 1407 lir_frem,
1408 left, 1408 left,
1409 right, 1409 right,
1455 res, 1455 res,
1456 info)); 1456 info));
1457 } 1457 }
1458 1458
1459 1459
1460 #ifndef MIPS64 1460 #ifndef MIPS
1461 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1461 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1462 append(new LIR_Op2( 1462 append(new LIR_Op2(
1463 lir_cmp, 1463 lir_cmp,
1464 condition, 1464 condition,
1465 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1465 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1479 1479
1480 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) { 1480 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1481 if (deoptimize_on_null) { 1481 if (deoptimize_on_null) {
1482 // Emit an explicit null check and deoptimize if opr is null 1482 // Emit an explicit null check and deoptimize if opr is null
1483 CodeStub* deopt = new DeoptimizeStub(info); 1483 CodeStub* deopt = new DeoptimizeStub(info);
1484 #ifndef MIPS64 1484 #ifndef MIPS
1485 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL)); 1485 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1486 branch(lir_cond_equal, T_OBJECT, deopt); 1486 branch(lir_cond_equal, T_OBJECT, deopt);
1487 #else 1487 #else
1488 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL)); 1488 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1489 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt); 1489 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1492 // Emit an implicit null check 1492 // Emit an implicit null check
1493 append(new LIR_Op1(lir_null_check, opr, info)); 1493 append(new LIR_Op1(lir_null_check, opr, info));
1494 } 1494 }
1495 } 1495 }
1496 1496
1497 #ifndef MIPS64 1497 #ifndef MIPS
1498 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1498 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1499 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1499 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1500 append(new LIR_OpAllocObj( 1500 append(new LIR_OpAllocObj(
1501 klass, 1501 klass,
1502 dst, 1502 dst,
1656 } 1656 }
1657 append(c); 1657 append(c);
1658 } 1658 }
1659 1659
1660 1660
1661 #ifndef MIPS64 1661 #ifndef MIPS
1662 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1662 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1663 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1663 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1664 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1664 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1665 } 1665 }
1666 1666
1793 } 1793 }
1794 1794
1795 // LIR_Address 1795 // LIR_Address
1796 void LIR_Address::print_value_on(outputStream* out) const { 1796 void LIR_Address::print_value_on(outputStream* out) const {
1797 out->print("Base:"); _base->print(out); 1797 out->print("Base:"); _base->print(out);
1798 #ifndef MIPS64 1798 #ifndef MIPS
1799 if (!_index->is_illegal()) { 1799 if (!_index->is_illegal()) {
1800 out->print(" Index:"); _index->print(out); 1800 out->print(" Index:"); _index->print(out);
1801 switch (scale()) { 1801 switch (scale()) {
1802 case times_1: break; 1802 case times_1: break;
1803 case times_2: out->print(" * 2"); break; 1803 case times_2: out->print(" * 2"); break;
1935 case lir_alloc_object: s = "alloc_obj"; break; 1935 case lir_alloc_object: s = "alloc_obj"; break;
1936 case lir_monaddr: s = "mon_addr"; break; 1936 case lir_monaddr: s = "mon_addr"; break;
1937 case lir_pack64: s = "pack64"; break; 1937 case lir_pack64: s = "pack64"; break;
1938 case lir_unpack64: s = "unpack64"; break; 1938 case lir_unpack64: s = "unpack64"; break;
1939 // LIR_Op2 1939 // LIR_Op2
1940 #ifdef MIPS64 1940 #ifdef MIPS
1941 case lir_null_check_for_branch: s = "null_check_for_branch"; break; 1941 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1942 #else 1942 #else
1943 case lir_cmp: s = "cmp"; break; 1943 case lir_cmp: s = "cmp"; break;
1944 #endif 1944 #endif
1945 case lir_cmp_l2i: s = "cmp_l2i"; break; 1945 case lir_cmp_l2i: s = "cmp_l2i"; break;
1970 case lir_ushr: s = "ushift_right"; break; 1970 case lir_ushr: s = "ushift_right"; break;
1971 case lir_alloc_array: s = "alloc_array"; break; 1971 case lir_alloc_array: s = "alloc_array"; break;
1972 case lir_xadd: s = "xadd"; break; 1972 case lir_xadd: s = "xadd"; break;
1973 case lir_xchg: s = "xchg"; break; 1973 case lir_xchg: s = "xchg"; break;
1974 // LIR_Op3 1974 // LIR_Op3
1975 #ifdef MIPS64 1975 #ifdef MIPS
1976 case lir_frem: s = "frem"; break; 1976 case lir_frem: s = "frem"; break;
1977 #endif 1977 #endif
1978 case lir_idiv: s = "idiv"; break; 1978 case lir_idiv: s = "idiv"; break;
1979 case lir_irem: s = "irem"; break; 1979 case lir_irem: s = "irem"; break;
1980 // LIR_OpJavaCall 1980 // LIR_OpJavaCall
2111 } 2111 }
2112 2112
2113 // LIR_OpBranch 2113 // LIR_OpBranch
2114 void LIR_OpBranch::print_instr(outputStream* out) const { 2114 void LIR_OpBranch::print_instr(outputStream* out) const {
2115 print_condition(out, cond()); out->print(" "); 2115 print_condition(out, cond()); out->print(" ");
2116 #ifdef MIPS64 2116 #ifdef MIPS
2117 in_opr1()->print(out); out->print(" "); 2117 in_opr1()->print(out); out->print(" ");
2118 in_opr2()->print(out); out->print(" "); 2118 in_opr2()->print(out); out->print(" ");
2119 #endif 2119 #endif
2120 if (block() != NULL) { 2120 if (block() != NULL) {
2121 out->print("[B%d] ", block()->block_id()); 2121 out->print("[B%d] ", block()->block_id());
2188 obj()->print(out); out->print(" "); 2188 obj()->print(out); out->print(" ");
2189 tmp1()->print(out); out->print(" "); 2189 tmp1()->print(out); out->print(" ");
2190 tmp2()->print(out); out->print(" "); 2190 tmp2()->print(out); out->print(" ");
2191 tmp3()->print(out); out->print(" "); 2191 tmp3()->print(out); out->print(" ");
2192 tmp4()->print(out); out->print(" "); 2192 tmp4()->print(out); out->print(" ");
2193 #ifdef MIPS64 2193 #ifdef MIPS
2194 tmp5()->print(out); out->print(" "); 2194 tmp5()->print(out); out->print(" ");
2195 tmp6()->print(out); out->print(" "); 2195 tmp6()->print(out); out->print(" ");
2196 #endif 2196 #endif
2197 out->print("[hdr:%d]", header_size()); out->print(" "); 2197 out->print("[hdr:%d]", header_size()); out->print(" ");
2198 out->print("[obj:%d]", object_size()); out->print(" "); 2198 out->print("[obj:%d]", object_size()); out->print(" ");
2205 result_opr()->print(out); out->print(" "); 2205 result_opr()->print(out); out->print(" ");
2206 } 2206 }
2207 2207
2208 // LIR_Op2 2208 // LIR_Op2
2209 void LIR_Op2::print_instr(outputStream* out) const { 2209 void LIR_Op2::print_instr(outputStream* out) const {
2210 #ifndef MIPS64 2210 #ifndef MIPS
2211 if (code() == lir_cmove) { 2211 if (code() == lir_cmove) {
2212 print_condition(out, condition()); out->print(" "); 2212 print_condition(out, condition()); out->print(" ");
2213 } 2213 }
2214 #endif 2214 #endif
2215 in_opr1()->print(out); out->print(" "); 2215 in_opr1()->print(out); out->print(" ");
2228 obj()->print(out); out->print(" "); 2228 obj()->print(out); out->print(" ");
2229 tmp1()->print(out); out->print(" "); 2229 tmp1()->print(out); out->print(" ");
2230 tmp2()->print(out); out->print(" "); 2230 tmp2()->print(out); out->print(" ");
2231 tmp3()->print(out); out->print(" "); 2231 tmp3()->print(out); out->print(" ");
2232 tmp4()->print(out); out->print(" "); 2232 tmp4()->print(out); out->print(" ");
2233 #ifdef MIPS64 2233 #ifdef MIPS
2234 tmp5()->print(out); out->print(" "); 2234 tmp5()->print(out); out->print(" ");
2235 #endif 2235 #endif
2236 out->print("[type:0x%x]", type()); out->print(" "); 2236 out->print("[type:0x%x]", type()); out->print(" ");
2237 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2237 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2238 } 2238 }

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