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src/share/vm/c1/c1_LIR.cpp@b56ab8e56604
src/share/vm/c1/c1_LIR.cpp
Tue, 24 Jul 2018 14:29:09 +0800
- author
- fujie
- date
- Tue, 24 Jul 2018 14:29:09 +0800
- changeset 9138
- b56ab8e56604
- parent 9126
- bc5b8e3dcb6b
- child 9142
- 87ee44a01d68
- permissions
- -rw-r--r--
#7173 #ifdefine MIPS64 --> #ifdefine MIPS
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
76 #ifdef ARM
78 FloatRegister LIR_OprDesc::as_float_reg() const {
79 return as_FloatRegister(fpu_regnr());
80 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
86 #endif
89 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
91 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
92 ValueTag tag = type->tag();
93 switch (tag) {
94 case metaDataTag : {
95 ClassConstant* c = type->as_ClassConstant();
96 if (c != NULL && !c->value()->is_loaded()) {
97 return LIR_OprFact::metadataConst(NULL);
98 } else if (c != NULL) {
99 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
100 } else {
101 MethodConstant* m = type->as_MethodConstant();
102 assert (m != NULL, "not a class or a method?");
103 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
104 }
105 }
106 case objectTag : {
107 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
108 }
109 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
110 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
111 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
112 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
113 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 }
119 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
120 switch (type->tag()) {
121 case objectTag: return LIR_OprFact::oopConst(NULL);
122 case addressTag:return LIR_OprFact::addressConst(0);
123 case intTag: return LIR_OprFact::intConst(0);
124 case floatTag: return LIR_OprFact::floatConst(0.0);
125 case longTag: return LIR_OprFact::longConst(0);
126 case doubleTag: return LIR_OprFact::doubleConst(0.0);
127 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
128 }
129 return illegalOpr;
130 }
134 //---------------------------------------------------
137 LIR_Address::Scale LIR_Address::scale(BasicType type) {
138 int elem_size = type2aelembytes(type);
139 switch (elem_size) {
140 case 1: return LIR_Address::times_1;
141 case 2: return LIR_Address::times_2;
142 case 4: return LIR_Address::times_4;
143 case 8: return LIR_Address::times_8;
144 }
145 ShouldNotReachHere();
146 return LIR_Address::times_1;
147 }
150 #ifndef PRODUCT
151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif
156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses");
162 #endif
163 #else
164 assert(base()->is_single_cpu(), "wrong base operand");
165 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
166 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
167 "wrong type for addresses");
168 #endif
169 }
170 #endif
173 //---------------------------------------------------
175 char LIR_OprDesc::type_char(BasicType t) {
176 switch (t) {
177 case T_ARRAY:
178 t = T_OBJECT;
179 case T_BOOLEAN:
180 case T_CHAR:
181 case T_FLOAT:
182 case T_DOUBLE:
183 case T_BYTE:
184 case T_SHORT:
185 case T_INT:
186 case T_LONG:
187 case T_OBJECT:
188 case T_ADDRESS:
189 case T_VOID:
190 return ::type2char(t);
191 case T_METADATA:
192 return 'M';
193 case T_ILLEGAL:
194 return '?';
196 default:
197 ShouldNotReachHere();
198 return '?';
199 }
200 }
202 #ifndef PRODUCT
203 void LIR_OprDesc::validate_type() const {
205 #ifdef ASSERT
206 if (!is_pointer() && !is_illegal()) {
207 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
208 switch (as_BasicType(type_field())) {
209 case T_LONG:
210 assert((kindfield == cpu_register || kindfield == stack_value) &&
211 size_field() == double_size, "must match");
212 break;
213 case T_FLOAT:
214 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
215 assert((kindfield == fpu_register || kindfield == stack_value
216 ARM_ONLY(|| kindfield == cpu_register)
217 PPC_ONLY(|| kindfield == cpu_register) ) &&
218 size_field() == single_size, "must match");
219 break;
220 case T_DOUBLE:
221 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
222 assert((kindfield == fpu_register || kindfield == stack_value
223 ARM_ONLY(|| kindfield == cpu_register)
224 PPC_ONLY(|| kindfield == cpu_register) ) &&
225 size_field() == double_size, "must match");
226 break;
227 case T_BOOLEAN:
228 case T_CHAR:
229 case T_BYTE:
230 case T_SHORT:
231 case T_INT:
232 case T_ADDRESS:
233 case T_OBJECT:
234 case T_METADATA:
235 case T_ARRAY:
236 assert((kindfield == cpu_register || kindfield == stack_value) &&
237 size_field() == single_size, "must match");
238 break;
240 case T_ILLEGAL:
241 // XXX TKR also means unknown right now
242 // assert(is_illegal(), "must match");
243 break;
245 default:
246 ShouldNotReachHere();
247 }
248 }
249 #endif
251 }
252 #endif // PRODUCT
255 bool LIR_OprDesc::is_oop() const {
256 if (is_pointer()) {
257 return pointer()->is_oop_pointer();
258 } else {
259 OprType t= type_field();
260 assert(t != unknown_type, "not set");
261 return t == object_type;
262 }
263 }
267 void LIR_Op2::verify() const {
268 #ifdef ASSERT
269 switch (code()) {
270 case lir_cmove:
271 case lir_xchg:
272 break;
274 default:
275 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
276 "can't produce oops from arith");
277 }
279 if (TwoOperandLIRForm) {
280 switch (code()) {
281 case lir_add:
282 case lir_sub:
283 case lir_mul:
284 case lir_mul_strictfp:
285 case lir_div:
286 case lir_div_strictfp:
287 case lir_rem:
288 case lir_logic_and:
289 case lir_logic_or:
290 case lir_logic_xor:
291 case lir_shl:
292 case lir_shr:
293 assert(in_opr1() == result_opr(), "opr1 and result must match");
294 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
295 break;
297 // special handling for lir_ushr because of write barriers
298 case lir_ushr:
299 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
300 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
301 break;
303 }
304 }
305 #endif
306 }
309 #ifndef MIPS
310 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
311 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
312 , _cond(cond)
313 , _type(type)
314 , _label(block->label())
315 , _block(block)
316 , _ublock(NULL)
317 , _stub(NULL) {
318 }
320 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
321 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
322 , _cond(cond)
323 , _type(type)
324 , _label(stub->entry())
325 , _block(NULL)
326 , _ublock(NULL)
327 , _stub(stub) {
328 }
330 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
331 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
332 , _cond(cond)
333 , _type(type)
334 , _label(block->label())
335 , _block(block)
336 , _ublock(ublock)
337 , _stub(NULL)
338 {
339 }
341 #else
342 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
343 BlockBegin* block):
344 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
345 _cond(cond),
346 _type(type),
347 _label(block->label()),
348 _block(block),
349 _ublock(NULL),
350 _stub(NULL) {
351 }
353 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
354 CodeStub* stub):
355 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
356 _cond(cond),
357 _type(type),
358 _label(stub->entry()),
359 _block(NULL),
360 _ublock(NULL),
361 _stub(stub) {
362 }
365 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
366 BlockBegin *block, BlockBegin *ublock):
367 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
368 _cond(cond),
369 _type(type),
370 _label(block->label()),
371 _block(block),
372 _ublock(ublock),
373 _stub(NULL) {
374 }
376 #endif
377 void LIR_OpBranch::change_block(BlockBegin* b) {
378 assert(_block != NULL, "must have old block");
379 assert(_block->label() == label(), "must be equal");
381 _block = b;
382 _label = b->label();
383 }
385 void LIR_OpBranch::change_ublock(BlockBegin* b) {
386 assert(_ublock != NULL, "must have old block");
387 _ublock = b;
388 }
390 void LIR_OpBranch::negate_cond() {
391 switch (_cond) {
392 case lir_cond_equal: _cond = lir_cond_notEqual; break;
393 case lir_cond_notEqual: _cond = lir_cond_equal; break;
394 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
395 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
396 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
397 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
398 default: ShouldNotReachHere();
399 }
400 }
403 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
404 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
405 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
406 CodeStub* stub)
408 : LIR_Op(code, result, NULL)
409 , _object(object)
410 , _array(LIR_OprFact::illegalOpr)
411 , _klass(klass)
412 , _tmp1(tmp1)
413 , _tmp2(tmp2)
414 , _tmp3(tmp3)
415 , _fast_check(fast_check)
416 , _stub(stub)
417 , _info_for_patch(info_for_patch)
418 , _info_for_exception(info_for_exception)
419 , _profiled_method(NULL)
420 , _profiled_bci(-1)
421 , _should_profile(false)
422 {
423 if (code == lir_checkcast) {
424 assert(info_for_exception != NULL, "checkcast throws exceptions");
425 } else if (code == lir_instanceof) {
426 assert(info_for_exception == NULL, "instanceof throws no exceptions");
427 } else {
428 ShouldNotReachHere();
429 }
430 }
434 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
435 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
436 , _object(object)
437 , _array(array)
438 , _klass(NULL)
439 , _tmp1(tmp1)
440 , _tmp2(tmp2)
441 , _tmp3(tmp3)
442 , _fast_check(false)
443 , _stub(NULL)
444 , _info_for_patch(NULL)
445 , _info_for_exception(info_for_exception)
446 , _profiled_method(NULL)
447 , _profiled_bci(-1)
448 , _should_profile(false)
449 {
450 if (code == lir_store_check) {
451 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
452 assert(info_for_exception != NULL, "store_check throws exceptions");
453 } else {
454 ShouldNotReachHere();
455 }
456 }
459 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
460 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
461 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
462 , _tmp(tmp)
463 , _src(src)
464 , _src_pos(src_pos)
465 , _dst(dst)
466 , _dst_pos(dst_pos)
467 , _flags(flags)
468 , _expected_type(expected_type)
469 , _length(length) {
470 _stub = new ArrayCopyStub(this);
471 }
473 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
474 : LIR_Op(lir_updatecrc32, res, NULL)
475 , _crc(crc)
476 , _val(val) {
477 }
479 //-------------------verify--------------------------
481 void LIR_Op1::verify() const {
482 switch(code()) {
483 case lir_move:
484 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
485 break;
486 case lir_null_check:
487 assert(in_opr()->is_register(), "must be");
488 break;
489 case lir_return:
490 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
491 break;
492 }
493 }
495 void LIR_OpRTCall::verify() const {
496 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
497 }
499 //-------------------visits--------------------------
501 // complete rework of LIR instruction visitor.
502 // The virtual call for each instruction type is replaced by a big
503 // switch that adds the operands for each instruction
505 void LIR_OpVisitState::visit(LIR_Op* op) {
506 // copy information from the LIR_Op
507 reset();
508 set_op(op);
510 switch (op->code()) {
512 // LIR_Op0
513 case lir_word_align: // result and info always invalid
514 case lir_backwardbranch_target: // result and info always invalid
515 case lir_build_frame: // result and info always invalid
516 case lir_fpop_raw: // result and info always invalid
517 case lir_24bit_FPU: // result and info always invalid
518 case lir_reset_FPU: // result and info always invalid
519 case lir_breakpoint: // result and info always invalid
520 case lir_membar: // result and info always invalid
521 case lir_membar_acquire: // result and info always invalid
522 case lir_membar_release: // result and info always invalid
523 case lir_membar_loadload: // result and info always invalid
524 case lir_membar_storestore: // result and info always invalid
525 case lir_membar_loadstore: // result and info always invalid
526 case lir_membar_storeload: // result and info always invalid
527 {
528 assert(op->as_Op0() != NULL, "must be");
529 assert(op->_info == NULL, "info not used by this instruction");
530 assert(op->_result->is_illegal(), "not used");
531 break;
532 }
534 case lir_nop: // may have info, result always invalid
535 case lir_std_entry: // may have result, info always invalid
536 case lir_osr_entry: // may have result, info always invalid
537 case lir_get_thread: // may have result, info always invalid
538 {
539 assert(op->as_Op0() != NULL, "must be");
540 if (op->_info != NULL) do_info(op->_info);
541 if (op->_result->is_valid()) do_output(op->_result);
542 break;
543 }
546 // LIR_OpLabel
547 case lir_label: // result and info always invalid
548 {
549 assert(op->as_OpLabel() != NULL, "must be");
550 assert(op->_info == NULL, "info not used by this instruction");
551 assert(op->_result->is_illegal(), "not used");
552 break;
553 }
556 // LIR_Op1
557 case lir_fxch: // input always valid, result and info always invalid
558 case lir_fld: // input always valid, result and info always invalid
559 case lir_ffree: // input always valid, result and info always invalid
560 case lir_push: // input always valid, result and info always invalid
561 case lir_pop: // input always valid, result and info always invalid
562 case lir_return: // input always valid, result and info always invalid
563 case lir_leal: // input and result always valid, info always invalid
564 case lir_neg: // input and result always valid, info always invalid
565 case lir_monaddr: // input and result always valid, info always invalid
566 case lir_null_check: // input and info always valid, result always invalid
567 case lir_move: // input and result always valid, may have info
568 case lir_pack64: // input and result always valid
569 case lir_unpack64: // input and result always valid
570 case lir_prefetchr: // input always valid, result and info always invalid
571 case lir_prefetchw: // input always valid, result and info always invalid
572 {
573 assert(op->as_Op1() != NULL, "must be");
574 LIR_Op1* op1 = (LIR_Op1*)op;
576 if (op1->_info) do_info(op1->_info);
577 if (op1->_opr->is_valid()) do_input(op1->_opr);
578 if (op1->_result->is_valid()) do_output(op1->_result);
580 break;
581 }
583 case lir_safepoint:
584 {
585 assert(op->as_Op1() != NULL, "must be");
586 LIR_Op1* op1 = (LIR_Op1*)op;
588 assert(op1->_info != NULL, ""); do_info(op1->_info);
589 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
590 assert(op1->_result->is_illegal(), "safepoint does not produce value");
592 break;
593 }
595 // LIR_OpConvert;
596 case lir_convert: // input and result always valid, info always invalid
597 {
598 assert(op->as_OpConvert() != NULL, "must be");
599 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
601 assert(opConvert->_info == NULL, "must be");
602 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
603 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
604 #ifdef PPC
605 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
606 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
607 #endif
608 do_stub(opConvert->_stub);
610 break;
611 }
613 // LIR_OpBranch;
614 case lir_branch: // may have info, input and result register always invalid
615 case lir_cond_float_branch: // may have info, input and result register always invalid
616 {
617 assert(op->as_OpBranch() != NULL, "must be");
618 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
620 #ifdef MIPS
621 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
622 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
623 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
624 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
625 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
626 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
627 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
628 #endif
629 if (opBranch->_info != NULL) do_info(opBranch->_info);
630 assert(opBranch->_result->is_illegal(), "not used");
631 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
633 break;
634 }
637 // LIR_OpAllocObj
638 case lir_alloc_object:
639 {
640 assert(op->as_OpAllocObj() != NULL, "must be");
641 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
643 if (opAllocObj->_info) do_info(opAllocObj->_info);
644 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
645 do_temp(opAllocObj->_opr);
646 }
647 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
648 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
649 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
650 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
651 #ifdef MIPS
652 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
653 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
654 #endif
655 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
656 do_stub(opAllocObj->_stub);
657 break;
658 }
661 // LIR_OpRoundFP;
662 case lir_roundfp: {
663 assert(op->as_OpRoundFP() != NULL, "must be");
664 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
666 assert(op->_info == NULL, "info not used by this instruction");
667 assert(opRoundFP->_tmp->is_illegal(), "not used");
668 do_input(opRoundFP->_opr);
669 do_output(opRoundFP->_result);
671 break;
672 }
675 // LIR_Op2
676 #ifdef MIPS
677 case lir_null_check_for_branch:
678 #else
679 case lir_cmp:
680 #endif
681 case lir_cmp_l2i:
682 case lir_ucmp_fd2i:
683 case lir_cmp_fd2i:
684 case lir_add:
685 case lir_sub:
686 case lir_mul:
687 case lir_div:
688 case lir_rem:
689 case lir_sqrt:
690 case lir_abs:
691 case lir_logic_and:
692 case lir_logic_or:
693 case lir_logic_xor:
694 case lir_shl:
695 case lir_shr:
696 case lir_ushr:
697 case lir_xadd:
698 case lir_xchg:
699 case lir_assert:
700 {
701 assert(op->as_Op2() != NULL, "must be");
702 LIR_Op2* op2 = (LIR_Op2*)op;
703 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
704 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
706 if (op2->_info) do_info(op2->_info);
707 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
708 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
709 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
710 if (op2->_result->is_valid()) do_output(op2->_result);
711 if (op->code() == lir_xchg || op->code() == lir_xadd) {
712 // on ARM and PPC, return value is loaded first so could
713 // destroy inputs. On other platforms that implement those
714 // (x86, sparc), the extra constrainsts are harmless.
715 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
716 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
717 }
719 break;
720 }
722 // special handling for cmove: right input operand must not be equal
723 // to the result operand, otherwise the backend fails
724 case lir_cmove:
725 {
726 assert(op->as_Op2() != NULL, "must be");
727 LIR_Op2* op2 = (LIR_Op2*)op;
729 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
730 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
731 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
733 do_input(op2->_opr1);
734 do_input(op2->_opr2);
735 do_temp(op2->_opr2);
736 do_output(op2->_result);
738 break;
739 }
741 // vspecial handling for strict operations: register input operands
742 // as temp to guarantee that they do not overlap with other
743 // registers
744 case lir_mul_strictfp:
745 case lir_div_strictfp:
746 {
747 assert(op->as_Op2() != NULL, "must be");
748 LIR_Op2* op2 = (LIR_Op2*)op;
750 assert(op2->_info == NULL, "not used");
751 assert(op2->_opr1->is_valid(), "used");
752 assert(op2->_opr2->is_valid(), "used");
753 assert(op2->_result->is_valid(), "used");
754 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
755 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
757 do_input(op2->_opr1); do_temp(op2->_opr1);
758 do_input(op2->_opr2); do_temp(op2->_opr2);
759 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
760 do_output(op2->_result);
762 break;
763 }
765 case lir_throw: {
766 assert(op->as_Op2() != NULL, "must be");
767 LIR_Op2* op2 = (LIR_Op2*)op;
769 if (op2->_info) do_info(op2->_info);
770 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
771 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
772 assert(op2->_result->is_illegal(), "no result");
773 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
774 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
776 break;
777 }
779 case lir_unwind: {
780 assert(op->as_Op1() != NULL, "must be");
781 LIR_Op1* op1 = (LIR_Op1*)op;
783 assert(op1->_info == NULL, "no info");
784 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
785 assert(op1->_result->is_illegal(), "no result");
787 break;
788 }
791 case lir_tan:
792 case lir_sin:
793 case lir_cos:
794 case lir_log:
795 case lir_log10:
796 case lir_exp: {
797 assert(op->as_Op2() != NULL, "must be");
798 LIR_Op2* op2 = (LIR_Op2*)op;
800 // On x86 tan/sin/cos need two temporary fpu stack slots and
801 // log/log10 need one so handle opr2 and tmp as temp inputs.
802 // Register input operand as temp to guarantee that it doesn't
803 // overlap with the input.
804 assert(op2->_info == NULL, "not used");
805 assert(op2->_tmp5->is_illegal(), "not used");
806 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
807 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
808 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
809 assert(op2->_opr1->is_valid(), "used");
810 do_input(op2->_opr1); do_temp(op2->_opr1);
812 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
813 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
814 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
815 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
816 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
817 if (op2->_result->is_valid()) do_output(op2->_result);
819 break;
820 }
822 case lir_pow: {
823 assert(op->as_Op2() != NULL, "must be");
824 LIR_Op2* op2 = (LIR_Op2*)op;
826 // On x86 pow needs two temporary fpu stack slots: tmp1 and
827 // tmp2. Register input operands as temps to guarantee that it
828 // doesn't overlap with the temporary slots.
829 assert(op2->_info == NULL, "not used");
830 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
831 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
832 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
833 assert(op2->_result->is_valid(), "used");
835 do_input(op2->_opr1); do_temp(op2->_opr1);
836 do_input(op2->_opr2); do_temp(op2->_opr2);
837 do_temp(op2->_tmp1);
838 do_temp(op2->_tmp2);
839 do_temp(op2->_tmp3);
840 do_temp(op2->_tmp4);
841 do_temp(op2->_tmp5);
842 do_output(op2->_result);
844 break;
845 }
847 // LIR_Op3
848 #ifdef MIPS
849 case lir_frem:
850 #endif
851 case lir_idiv:
852 case lir_irem: {
853 assert(op->as_Op3() != NULL, "must be");
854 LIR_Op3* op3= (LIR_Op3*)op;
856 if (op3->_info) do_info(op3->_info);
857 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
859 // second operand is input and temp, so ensure that second operand
860 // and third operand get not the same register
861 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
862 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
863 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
865 if (op3->_result->is_valid()) do_output(op3->_result);
867 break;
868 }
871 // LIR_OpJavaCall
872 case lir_static_call:
873 case lir_optvirtual_call:
874 case lir_icvirtual_call:
875 case lir_virtual_call:
876 case lir_dynamic_call: {
877 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
878 assert(opJavaCall != NULL, "must be");
880 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
882 // only visit register parameters
883 int n = opJavaCall->_arguments->length();
884 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
885 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
886 do_input(*opJavaCall->_arguments->adr_at(i));
887 }
888 }
890 if (opJavaCall->_info) do_info(opJavaCall->_info);
891 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
892 opJavaCall->is_method_handle_invoke()) {
893 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
894 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
895 }
896 do_call();
897 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
899 break;
900 }
903 // LIR_OpRTCall
904 case lir_rtcall: {
905 assert(op->as_OpRTCall() != NULL, "must be");
906 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
908 // only visit register parameters
909 int n = opRTCall->_arguments->length();
910 for (int i = 0; i < n; i++) {
911 if (!opRTCall->_arguments->at(i)->is_pointer()) {
912 do_input(*opRTCall->_arguments->adr_at(i));
913 }
914 }
915 if (opRTCall->_info) do_info(opRTCall->_info);
916 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
917 do_call();
918 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
920 break;
921 }
924 // LIR_OpArrayCopy
925 case lir_arraycopy: {
926 assert(op->as_OpArrayCopy() != NULL, "must be");
927 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
929 assert(opArrayCopy->_result->is_illegal(), "unused");
930 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
931 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
932 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
933 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
934 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
935 #ifndef MIPS
936 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
937 #endif
938 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
940 // the implementation of arraycopy always has a call into the runtime
941 do_call();
943 break;
944 }
947 // LIR_OpUpdateCRC32
948 case lir_updatecrc32: {
949 assert(op->as_OpUpdateCRC32() != NULL, "must be");
950 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
952 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
953 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
954 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
955 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
957 break;
958 }
961 // LIR_OpLock
962 case lir_lock:
963 case lir_unlock: {
964 assert(op->as_OpLock() != NULL, "must be");
965 LIR_OpLock* opLock = (LIR_OpLock*)op;
967 if (opLock->_info) do_info(opLock->_info);
969 // TODO: check if these operands really have to be temp
970 // (or if input is sufficient). This may have influence on the oop map!
971 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
972 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
973 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
975 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
976 assert(opLock->_result->is_illegal(), "unused");
978 do_stub(opLock->_stub);
980 break;
981 }
984 // LIR_OpDelay
985 case lir_delay_slot: {
986 assert(op->as_OpDelay() != NULL, "must be");
987 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
989 visit(opDelay->delay_op());
990 break;
991 }
993 // LIR_OpTypeCheck
994 case lir_instanceof:
995 case lir_checkcast:
996 case lir_store_check: {
997 assert(op->as_OpTypeCheck() != NULL, "must be");
998 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1000 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1001 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1002 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1003 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1004 do_temp(opTypeCheck->_object);
1005 }
1006 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1007 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1008 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1009 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1010 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1011 do_stub(opTypeCheck->_stub);
1012 break;
1013 }
1015 // LIR_OpCompareAndSwap
1016 case lir_cas_long:
1017 case lir_cas_obj:
1018 case lir_cas_int: {
1019 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1020 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1022 assert(opCompareAndSwap->_addr->is_valid(), "used");
1023 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1024 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1025 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1026 do_input(opCompareAndSwap->_addr);
1027 do_temp(opCompareAndSwap->_addr);
1028 do_input(opCompareAndSwap->_cmp_value);
1029 do_temp(opCompareAndSwap->_cmp_value);
1030 do_input(opCompareAndSwap->_new_value);
1031 do_temp(opCompareAndSwap->_new_value);
1032 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1033 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1034 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1036 break;
1037 }
1040 // LIR_OpAllocArray;
1041 case lir_alloc_array: {
1042 assert(op->as_OpAllocArray() != NULL, "must be");
1043 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1045 if (opAllocArray->_info) do_info(opAllocArray->_info);
1046 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1047 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1048 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1049 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1050 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1051 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1052 #ifdef MIPS
1053 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1054 #endif
1055 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1056 do_stub(opAllocArray->_stub);
1057 break;
1058 }
1060 // LIR_OpProfileCall:
1061 case lir_profile_call: {
1062 assert(op->as_OpProfileCall() != NULL, "must be");
1063 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1065 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1066 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1067 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1068 break;
1069 }
1071 // LIR_OpProfileType:
1072 case lir_profile_type: {
1073 assert(op->as_OpProfileType() != NULL, "must be");
1074 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1076 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1077 do_input(opProfileType->_obj);
1078 do_temp(opProfileType->_tmp);
1079 break;
1080 }
1081 default:
1082 ShouldNotReachHere();
1083 }
1084 }
1087 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1088 if (stub != NULL) {
1089 stub->visit(this);
1090 }
1091 }
1093 XHandlers* LIR_OpVisitState::all_xhandler() {
1094 XHandlers* result = NULL;
1096 int i;
1097 for (i = 0; i < info_count(); i++) {
1098 if (info_at(i)->exception_handlers() != NULL) {
1099 result = info_at(i)->exception_handlers();
1100 break;
1101 }
1102 }
1104 #ifdef ASSERT
1105 for (i = 0; i < info_count(); i++) {
1106 assert(info_at(i)->exception_handlers() == NULL ||
1107 info_at(i)->exception_handlers() == result,
1108 "only one xhandler list allowed per LIR-operation");
1109 }
1110 #endif
1112 if (result != NULL) {
1113 return result;
1114 } else {
1115 return new XHandlers();
1116 }
1118 return result;
1119 }
1122 #ifdef ASSERT
1123 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1124 visit(op);
1126 return opr_count(inputMode) == 0 &&
1127 opr_count(outputMode) == 0 &&
1128 opr_count(tempMode) == 0 &&
1129 info_count() == 0 &&
1130 !has_call() &&
1131 !has_slow_case();
1132 }
1133 #endif
1135 //---------------------------------------------------
1138 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1139 masm->emit_call(this);
1140 }
1142 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1143 masm->emit_rtcall(this);
1144 }
1146 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1147 masm->emit_opLabel(this);
1148 }
1150 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1151 masm->emit_arraycopy(this);
1152 masm->append_code_stub(stub());
1153 }
1155 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1156 masm->emit_updatecrc32(this);
1157 }
1159 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1160 masm->emit_op0(this);
1161 }
1163 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1164 masm->emit_op1(this);
1165 }
1167 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1168 masm->emit_alloc_obj(this);
1169 masm->append_code_stub(stub());
1170 }
1172 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1173 masm->emit_opBranch(this);
1174 if (stub()) {
1175 masm->append_code_stub(stub());
1176 }
1177 }
1179 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1180 masm->emit_opConvert(this);
1181 if (stub() != NULL) {
1182 masm->append_code_stub(stub());
1183 }
1184 }
1186 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1187 masm->emit_op2(this);
1188 }
1190 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1191 masm->emit_alloc_array(this);
1192 masm->append_code_stub(stub());
1193 }
1195 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1196 masm->emit_opTypeCheck(this);
1197 if (stub()) {
1198 masm->append_code_stub(stub());
1199 }
1200 }
1202 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1203 masm->emit_compare_and_swap(this);
1204 }
1206 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1207 masm->emit_op3(this);
1208 }
1210 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1211 masm->emit_lock(this);
1212 if (stub()) {
1213 masm->append_code_stub(stub());
1214 }
1215 }
1217 #ifdef ASSERT
1218 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1219 masm->emit_assert(this);
1220 }
1221 #endif
1223 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1224 masm->emit_delay(this);
1225 }
1227 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1228 masm->emit_profile_call(this);
1229 }
1231 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1232 masm->emit_profile_type(this);
1233 }
1235 // LIR_List
1236 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1237 : _operations(8)
1238 , _compilation(compilation)
1239 #ifndef PRODUCT
1240 , _block(block)
1241 #endif
1242 #ifdef ASSERT
1243 , _file(NULL)
1244 , _line(0)
1245 #endif
1246 { }
1249 #ifdef ASSERT
1250 void LIR_List::set_file_and_line(const char * file, int line) {
1251 const char * f = strrchr(file, '/');
1252 if (f == NULL) f = strrchr(file, '\\');
1253 if (f == NULL) {
1254 f = file;
1255 } else {
1256 f++;
1257 }
1258 _file = f;
1259 _line = line;
1260 }
1261 #endif
1264 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1265 assert(this == buffer->lir_list(), "wrong lir list");
1266 const int n = _operations.length();
1268 if (buffer->number_of_ops() > 0) {
1269 // increase size of instructions list
1270 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1271 // insert ops from buffer into instructions list
1272 int op_index = buffer->number_of_ops() - 1;
1273 int ip_index = buffer->number_of_insertion_points() - 1;
1274 int from_index = n - 1;
1275 int to_index = _operations.length() - 1;
1276 for (; ip_index >= 0; ip_index --) {
1277 int index = buffer->index_at(ip_index);
1278 // make room after insertion point
1279 while (index < from_index) {
1280 _operations.at_put(to_index --, _operations.at(from_index --));
1281 }
1282 // insert ops from buffer
1283 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1284 _operations.at_put(to_index --, buffer->op_at(op_index --));
1285 }
1286 }
1287 }
1289 buffer->finish();
1290 }
1293 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1294 assert(reg->type() == T_OBJECT, "bad reg");
1295 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1296 }
1298 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1299 assert(reg->type() == T_METADATA, "bad reg");
1300 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1301 }
1303 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1304 append(new LIR_Op1(
1305 lir_move,
1306 LIR_OprFact::address(addr),
1307 src,
1308 addr->type(),
1309 patch_code,
1310 info));
1311 }
1314 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1315 append(new LIR_Op1(
1316 lir_move,
1317 LIR_OprFact::address(address),
1318 dst,
1319 address->type(),
1320 patch_code,
1321 info, lir_move_volatile));
1322 }
1324 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1325 #ifdef MIPS
1326 add(base, offset, base);
1327 offset = 0;
1328 #endif
1329 append(new LIR_Op1(
1330 lir_move,
1331 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1332 dst,
1333 type,
1334 patch_code,
1335 info, lir_move_volatile));
1336 }
1339 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1340 append(new LIR_Op1(
1341 is_store ? lir_prefetchw : lir_prefetchr,
1342 LIR_OprFact::address(addr)));
1343 }
1346 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1347 append(new LIR_Op1(
1348 lir_move,
1349 LIR_OprFact::intConst(v),
1350 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1351 type,
1352 patch_code,
1353 info));
1354 }
1357 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1358 append(new LIR_Op1(
1359 lir_move,
1360 LIR_OprFact::oopConst(o),
1361 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1362 type,
1363 patch_code,
1364 info));
1365 }
1368 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1369 append(new LIR_Op1(
1370 lir_move,
1371 src,
1372 LIR_OprFact::address(addr),
1373 addr->type(),
1374 patch_code,
1375 info));
1376 }
1379 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1380 append(new LIR_Op1(
1381 lir_move,
1382 src,
1383 LIR_OprFact::address(addr),
1384 addr->type(),
1385 patch_code,
1386 info,
1387 lir_move_volatile));
1388 }
1390 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1391 #ifdef MIPS
1392 add(base, offset, base);
1393 offset = 0;
1394 #endif
1395 append(new LIR_Op1(
1396 lir_move,
1397 src,
1398 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1399 type,
1400 patch_code,
1401 info, lir_move_volatile));
1402 }
1404 #ifdef MIPS
1405 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1406 append(new LIR_Op3(
1407 lir_frem,
1408 left,
1409 right,
1410 tmp,
1411 res,
1412 info));
1413 }
1414 #endif
1416 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1417 append(new LIR_Op3(
1418 lir_idiv,
1419 left,
1420 right,
1421 tmp,
1422 res,
1423 info));
1424 }
1427 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1428 append(new LIR_Op3(
1429 lir_idiv,
1430 left,
1431 LIR_OprFact::intConst(right),
1432 tmp,
1433 res,
1434 info));
1435 }
1438 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1439 append(new LIR_Op3(
1440 lir_irem,
1441 left,
1442 right,
1443 tmp,
1444 res,
1445 info));
1446 }
1449 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1450 append(new LIR_Op3(
1451 lir_irem,
1452 left,
1453 LIR_OprFact::intConst(right),
1454 tmp,
1455 res,
1456 info));
1457 }
1460 #ifndef MIPS
1461 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1462 append(new LIR_Op2(
1463 lir_cmp,
1464 condition,
1465 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1466 LIR_OprFact::intConst(c),
1467 info));
1468 }
1470 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1471 append(new LIR_Op2(
1472 lir_cmp,
1473 condition,
1474 reg,
1475 LIR_OprFact::address(addr),
1476 info));
1477 }
1478 #endif
1480 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1481 if (deoptimize_on_null) {
1482 // Emit an explicit null check and deoptimize if opr is null
1483 CodeStub* deopt = new DeoptimizeStub(info);
1484 #ifndef MIPS
1485 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1486 branch(lir_cond_equal, T_OBJECT, deopt);
1487 #else
1488 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1489 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1490 #endif
1491 } else {
1492 // Emit an implicit null check
1493 append(new LIR_Op1(lir_null_check, opr, info));
1494 }
1495 }
1497 #ifndef MIPS
1498 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1499 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1500 append(new LIR_OpAllocObj(
1501 klass,
1502 dst,
1503 t1,
1504 t2,
1505 t3,
1506 t4,
1507 header_size,
1508 object_size,
1509 init_check,
1510 stub));
1511 }
1513 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1514 append(new LIR_OpAllocArray(
1515 klass,
1516 len,
1517 dst,
1518 t1,
1519 t2,
1520 t3,
1521 t4,
1522 type,
1523 stub));
1524 }
1525 #else
1526 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1527 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1528 append(new LIR_OpAllocObj(
1529 klass,
1530 dst,
1531 t1,
1532 t2,
1533 t3,
1534 t4,
1535 t5,
1536 t6,
1537 header_size,
1538 object_size,
1539 init_check,
1540 stub));
1541 }
1542 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1543 BasicType type, LIR_Opr klass, CodeStub* stub) {
1544 append(new LIR_OpAllocArray(
1545 klass,
1546 len,
1547 dst,
1548 t1,
1549 t2,
1550 t3,
1551 t4,
1552 t5,
1553 type,
1554 stub));
1555 }
1557 #endif
1559 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1560 append(new LIR_Op2(
1561 lir_shl,
1562 value,
1563 count,
1564 dst,
1565 tmp));
1566 }
1568 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1569 append(new LIR_Op2(
1570 lir_shr,
1571 value,
1572 count,
1573 dst,
1574 tmp));
1575 }
1578 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1579 append(new LIR_Op2(
1580 lir_ushr,
1581 value,
1582 count,
1583 dst,
1584 tmp));
1585 }
1587 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1588 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1589 left,
1590 right,
1591 dst));
1592 }
1594 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1595 append(new LIR_OpLock(
1596 lir_lock,
1597 hdr,
1598 obj,
1599 lock,
1600 scratch,
1601 stub,
1602 info));
1603 }
1605 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1606 append(new LIR_OpLock(
1607 lir_unlock,
1608 hdr,
1609 obj,
1610 lock,
1611 scratch,
1612 stub,
1613 NULL));
1614 }
1617 void check_LIR() {
1618 // cannot do the proper checking as PRODUCT and other modes return different results
1619 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1620 }
1624 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1625 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1626 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1627 ciMethod* profiled_method, int profiled_bci) {
1628 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1629 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1630 if (profiled_method != NULL) {
1631 c->set_profiled_method(profiled_method);
1632 c->set_profiled_bci(profiled_bci);
1633 c->set_should_profile(true);
1634 }
1635 append(c);
1636 }
1638 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1639 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1640 if (profiled_method != NULL) {
1641 c->set_profiled_method(profiled_method);
1642 c->set_profiled_bci(profiled_bci);
1643 c->set_should_profile(true);
1644 }
1645 append(c);
1646 }
1649 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1650 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1651 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1652 if (profiled_method != NULL) {
1653 c->set_profiled_method(profiled_method);
1654 c->set_profiled_bci(profiled_bci);
1655 c->set_should_profile(true);
1656 }
1657 append(c);
1658 }
1661 #ifndef MIPS
1662 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1663 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1664 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1665 }
1667 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1668 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1669 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1670 }
1672 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1673 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1674 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1675 }
1676 #else
1677 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1678 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1679 // // implying successful swap of new_value into addr
1680 append(new LIR_OpCompareAndSwap(lir_cas_long,
1681 addr,
1682 cmp_value,
1683 new_value,
1684 t1,
1685 t2,
1686 result));
1687 }
1689 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1690 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1691 // // implying successful swap of new_value into addr
1692 append(new LIR_OpCompareAndSwap(lir_cas_obj,
1693 addr,
1694 cmp_value,
1695 new_value,
1696 t1,
1697 t2,
1698 result));
1699 }
1701 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1702 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1703 // // implying successful swap of new_value into addr
1704 append(new LIR_OpCompareAndSwap(lir_cas_int,
1705 addr,
1706 cmp_value,
1707 new_value,
1708 t1,
1709 t2,
1710 result));
1711 }
1712 #endif
1715 #ifdef PRODUCT
1717 void print_LIR(BlockList* blocks) {
1718 }
1720 #else
1721 // LIR_OprDesc
1722 void LIR_OprDesc::print() const {
1723 print(tty);
1724 }
1726 void LIR_OprDesc::print(outputStream* out) const {
1727 if (is_illegal()) {
1728 return;
1729 }
1731 out->print("[");
1732 if (is_pointer()) {
1733 pointer()->print_value_on(out);
1734 } else if (is_single_stack()) {
1735 out->print("stack:%d", single_stack_ix());
1736 } else if (is_double_stack()) {
1737 out->print("dbl_stack:%d",double_stack_ix());
1738 } else if (is_virtual()) {
1739 out->print("R%d", vreg_number());
1740 } else if (is_single_cpu()) {
1741 out->print("%s", as_register()->name());
1742 } else if (is_double_cpu()) {
1743 out->print("%s", as_register_hi()->name());
1744 out->print("%s", as_register_lo()->name());
1745 #if defined(X86)
1746 } else if (is_single_xmm()) {
1747 out->print("%s", as_xmm_float_reg()->name());
1748 } else if (is_double_xmm()) {
1749 out->print("%s", as_xmm_double_reg()->name());
1750 } else if (is_single_fpu()) {
1751 out->print("fpu%d", fpu_regnr());
1752 } else if (is_double_fpu()) {
1753 out->print("fpu%d", fpu_regnrLo());
1754 #elif defined(ARM)
1755 } else if (is_single_fpu()) {
1756 out->print("s%d", fpu_regnr());
1757 } else if (is_double_fpu()) {
1758 out->print("d%d", fpu_regnrLo() >> 1);
1759 #else
1760 } else if (is_single_fpu()) {
1761 out->print("%s", as_float_reg()->name());
1762 } else if (is_double_fpu()) {
1763 out->print("%s", as_double_reg()->name());
1764 #endif
1766 } else if (is_illegal()) {
1767 out->print("-");
1768 } else {
1769 out->print("Unknown Operand");
1770 }
1771 if (!is_illegal()) {
1772 out->print("|%c", type_char());
1773 }
1774 if (is_register() && is_last_use()) {
1775 out->print("(last_use)");
1776 }
1777 out->print("]");
1778 }
1781 // LIR_Address
1782 void LIR_Const::print_value_on(outputStream* out) const {
1783 switch (type()) {
1784 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1785 case T_INT: out->print("int:%d", as_jint()); break;
1786 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1787 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1788 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1789 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1790 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1791 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1792 }
1793 }
1795 // LIR_Address
1796 void LIR_Address::print_value_on(outputStream* out) const {
1797 out->print("Base:"); _base->print(out);
1798 #ifndef MIPS
1799 if (!_index->is_illegal()) {
1800 out->print(" Index:"); _index->print(out);
1801 switch (scale()) {
1802 case times_1: break;
1803 case times_2: out->print(" * 2"); break;
1804 case times_4: out->print(" * 4"); break;
1805 case times_8: out->print(" * 8"); break;
1806 }
1807 }
1808 #endif
1809 out->print(" Disp: " INTX_FORMAT, _disp);
1810 }
1812 // debug output of block header without InstructionPrinter
1813 // (because phi functions are not necessary for LIR)
1814 static void print_block(BlockBegin* x) {
1815 // print block id
1816 BlockEnd* end = x->end();
1817 tty->print("B%d ", x->block_id());
1819 // print flags
1820 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1821 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1822 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1823 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1824 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1825 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1826 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1828 // print block bci range
1829 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1831 // print predecessors and successors
1832 if (x->number_of_preds() > 0) {
1833 tty->print("preds: ");
1834 for (int i = 0; i < x->number_of_preds(); i ++) {
1835 tty->print("B%d ", x->pred_at(i)->block_id());
1836 }
1837 }
1839 if (x->number_of_sux() > 0) {
1840 tty->print("sux: ");
1841 for (int i = 0; i < x->number_of_sux(); i ++) {
1842 tty->print("B%d ", x->sux_at(i)->block_id());
1843 }
1844 }
1846 // print exception handlers
1847 if (x->number_of_exception_handlers() > 0) {
1848 tty->print("xhandler: ");
1849 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1850 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1851 }
1852 }
1854 tty->cr();
1855 }
1857 void print_LIR(BlockList* blocks) {
1858 tty->print_cr("LIR:");
1859 int i;
1860 for (i = 0; i < blocks->length(); i++) {
1861 BlockBegin* bb = blocks->at(i);
1862 print_block(bb);
1863 tty->print("__id_Instruction___________________________________________"); tty->cr();
1864 bb->lir()->print_instructions();
1865 }
1866 }
1868 void LIR_List::print_instructions() {
1869 for (int i = 0; i < _operations.length(); i++) {
1870 _operations.at(i)->print(); tty->cr();
1871 }
1872 tty->cr();
1873 }
1875 // LIR_Ops printing routines
1876 // LIR_Op
1877 void LIR_Op::print_on(outputStream* out) const {
1878 if (id() != -1 || PrintCFGToFile) {
1879 out->print("%4d ", id());
1880 } else {
1881 out->print(" ");
1882 }
1883 out->print("%s ", name());
1884 print_instr(out);
1885 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1886 #ifdef ASSERT
1887 if (Verbose && _file != NULL) {
1888 out->print(" (%s:%d)", _file, _line);
1889 }
1890 #endif
1891 }
1893 const char * LIR_Op::name() const {
1894 const char* s = NULL;
1895 switch(code()) {
1896 // LIR_Op0
1897 case lir_membar: s = "membar"; break;
1898 case lir_membar_acquire: s = "membar_acquire"; break;
1899 case lir_membar_release: s = "membar_release"; break;
1900 case lir_membar_loadload: s = "membar_loadload"; break;
1901 case lir_membar_storestore: s = "membar_storestore"; break;
1902 case lir_membar_loadstore: s = "membar_loadstore"; break;
1903 case lir_membar_storeload: s = "membar_storeload"; break;
1904 case lir_word_align: s = "word_align"; break;
1905 case lir_label: s = "label"; break;
1906 case lir_nop: s = "nop"; break;
1907 case lir_backwardbranch_target: s = "backbranch"; break;
1908 case lir_std_entry: s = "std_entry"; break;
1909 case lir_osr_entry: s = "osr_entry"; break;
1910 case lir_build_frame: s = "build_frm"; break;
1911 case lir_fpop_raw: s = "fpop_raw"; break;
1912 case lir_24bit_FPU: s = "24bit_FPU"; break;
1913 case lir_reset_FPU: s = "reset_FPU"; break;
1914 case lir_breakpoint: s = "breakpoint"; break;
1915 case lir_get_thread: s = "get_thread"; break;
1916 // LIR_Op1
1917 case lir_fxch: s = "fxch"; break;
1918 case lir_fld: s = "fld"; break;
1919 case lir_ffree: s = "ffree"; break;
1920 case lir_push: s = "push"; break;
1921 case lir_pop: s = "pop"; break;
1922 case lir_null_check: s = "null_check"; break;
1923 case lir_return: s = "return"; break;
1924 case lir_safepoint: s = "safepoint"; break;
1925 case lir_neg: s = "neg"; break;
1926 case lir_leal: s = "leal"; break;
1927 case lir_branch: s = "branch"; break;
1928 case lir_cond_float_branch: s = "flt_cond_br"; break;
1929 case lir_move: s = "move"; break;
1930 case lir_roundfp: s = "roundfp"; break;
1931 case lir_rtcall: s = "rtcall"; break;
1932 case lir_throw: s = "throw"; break;
1933 case lir_unwind: s = "unwind"; break;
1934 case lir_convert: s = "convert"; break;
1935 case lir_alloc_object: s = "alloc_obj"; break;
1936 case lir_monaddr: s = "mon_addr"; break;
1937 case lir_pack64: s = "pack64"; break;
1938 case lir_unpack64: s = "unpack64"; break;
1939 // LIR_Op2
1940 #ifdef MIPS
1941 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1942 #else
1943 case lir_cmp: s = "cmp"; break;
1944 #endif
1945 case lir_cmp_l2i: s = "cmp_l2i"; break;
1946 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1947 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1948 case lir_cmove: s = "cmove"; break;
1949 case lir_add: s = "add"; break;
1950 case lir_sub: s = "sub"; break;
1951 case lir_mul: s = "mul"; break;
1952 case lir_mul_strictfp: s = "mul_strictfp"; break;
1953 case lir_div: s = "div"; break;
1954 case lir_div_strictfp: s = "div_strictfp"; break;
1955 case lir_rem: s = "rem"; break;
1956 case lir_abs: s = "abs"; break;
1957 case lir_sqrt: s = "sqrt"; break;
1958 case lir_sin: s = "sin"; break;
1959 case lir_cos: s = "cos"; break;
1960 case lir_tan: s = "tan"; break;
1961 case lir_log: s = "log"; break;
1962 case lir_log10: s = "log10"; break;
1963 case lir_exp: s = "exp"; break;
1964 case lir_pow: s = "pow"; break;
1965 case lir_logic_and: s = "logic_and"; break;
1966 case lir_logic_or: s = "logic_or"; break;
1967 case lir_logic_xor: s = "logic_xor"; break;
1968 case lir_shl: s = "shift_left"; break;
1969 case lir_shr: s = "shift_right"; break;
1970 case lir_ushr: s = "ushift_right"; break;
1971 case lir_alloc_array: s = "alloc_array"; break;
1972 case lir_xadd: s = "xadd"; break;
1973 case lir_xchg: s = "xchg"; break;
1974 // LIR_Op3
1975 #ifdef MIPS
1976 case lir_frem: s = "frem"; break;
1977 #endif
1978 case lir_idiv: s = "idiv"; break;
1979 case lir_irem: s = "irem"; break;
1980 // LIR_OpJavaCall
1981 case lir_static_call: s = "static"; break;
1982 case lir_optvirtual_call: s = "optvirtual"; break;
1983 case lir_icvirtual_call: s = "icvirtual"; break;
1984 case lir_virtual_call: s = "virtual"; break;
1985 case lir_dynamic_call: s = "dynamic"; break;
1986 // LIR_OpArrayCopy
1987 case lir_arraycopy: s = "arraycopy"; break;
1988 // LIR_OpUpdateCRC32
1989 case lir_updatecrc32: s = "updatecrc32"; break;
1990 // LIR_OpLock
1991 case lir_lock: s = "lock"; break;
1992 case lir_unlock: s = "unlock"; break;
1993 // LIR_OpDelay
1994 case lir_delay_slot: s = "delay"; break;
1995 // LIR_OpTypeCheck
1996 case lir_instanceof: s = "instanceof"; break;
1997 case lir_checkcast: s = "checkcast"; break;
1998 case lir_store_check: s = "store_check"; break;
1999 // LIR_OpCompareAndSwap
2000 case lir_cas_long: s = "cas_long"; break;
2001 case lir_cas_obj: s = "cas_obj"; break;
2002 case lir_cas_int: s = "cas_int"; break;
2003 // LIR_OpProfileCall
2004 case lir_profile_call: s = "profile_call"; break;
2005 // LIR_OpProfileType
2006 case lir_profile_type: s = "profile_type"; break;
2007 // LIR_OpAssert
2008 #ifdef ASSERT
2009 case lir_assert: s = "assert"; break;
2010 #endif
2011 case lir_none: ShouldNotReachHere();break;
2012 default: s = "illegal_op"; break;
2013 }
2014 return s;
2015 }
2017 // LIR_OpJavaCall
2018 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2019 out->print("call: ");
2020 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2021 if (receiver()->is_valid()) {
2022 out->print(" [recv: "); receiver()->print(out); out->print("]");
2023 }
2024 if (result_opr()->is_valid()) {
2025 out->print(" [result: "); result_opr()->print(out); out->print("]");
2026 }
2027 }
2029 // LIR_OpLabel
2030 void LIR_OpLabel::print_instr(outputStream* out) const {
2031 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2032 }
2034 // LIR_OpArrayCopy
2035 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2036 src()->print(out); out->print(" ");
2037 src_pos()->print(out); out->print(" ");
2038 dst()->print(out); out->print(" ");
2039 dst_pos()->print(out); out->print(" ");
2040 length()->print(out); out->print(" ");
2041 tmp()->print(out); out->print(" ");
2042 }
2044 // LIR_OpUpdateCRC32
2045 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2046 crc()->print(out); out->print(" ");
2047 val()->print(out); out->print(" ");
2048 result_opr()->print(out); out->print(" ");
2049 }
2051 // LIR_OpCompareAndSwap
2052 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2053 addr()->print(out); out->print(" ");
2054 cmp_value()->print(out); out->print(" ");
2055 new_value()->print(out); out->print(" ");
2056 tmp1()->print(out); out->print(" ");
2057 tmp2()->print(out); out->print(" ");
2059 }
2061 // LIR_Op0
2062 void LIR_Op0::print_instr(outputStream* out) const {
2063 result_opr()->print(out);
2064 }
2066 // LIR_Op1
2067 const char * LIR_Op1::name() const {
2068 if (code() == lir_move) {
2069 switch (move_kind()) {
2070 case lir_move_normal:
2071 return "move";
2072 case lir_move_unaligned:
2073 return "unaligned move";
2074 case lir_move_volatile:
2075 return "volatile_move";
2076 case lir_move_wide:
2077 return "wide_move";
2078 default:
2079 ShouldNotReachHere();
2080 return "illegal_op";
2081 }
2082 } else {
2083 return LIR_Op::name();
2084 }
2085 }
2088 void LIR_Op1::print_instr(outputStream* out) const {
2089 _opr->print(out); out->print(" ");
2090 result_opr()->print(out); out->print(" ");
2091 print_patch_code(out, patch_code());
2092 }
2095 // LIR_Op1
2096 void LIR_OpRTCall::print_instr(outputStream* out) const {
2097 intx a = (intx)addr();
2098 out->print("%s", Runtime1::name_for_address(addr()));
2099 out->print(" ");
2100 tmp()->print(out);
2101 }
2103 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2104 switch(code) {
2105 case lir_patch_none: break;
2106 case lir_patch_low: out->print("[patch_low]"); break;
2107 case lir_patch_high: out->print("[patch_high]"); break;
2108 case lir_patch_normal: out->print("[patch_normal]"); break;
2109 default: ShouldNotReachHere();
2110 }
2111 }
2113 // LIR_OpBranch
2114 void LIR_OpBranch::print_instr(outputStream* out) const {
2115 print_condition(out, cond()); out->print(" ");
2116 #ifdef MIPS
2117 in_opr1()->print(out); out->print(" ");
2118 in_opr2()->print(out); out->print(" ");
2119 #endif
2120 if (block() != NULL) {
2121 out->print("[B%d] ", block()->block_id());
2122 } else if (stub() != NULL) {
2123 out->print("[");
2124 stub()->print_name(out);
2125 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2126 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2127 } else {
2128 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2129 }
2130 if (ublock() != NULL) {
2131 out->print("unordered: [B%d] ", ublock()->block_id());
2132 }
2133 }
2135 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2136 switch(cond) {
2137 case lir_cond_equal: out->print("[EQ]"); break;
2138 case lir_cond_notEqual: out->print("[NE]"); break;
2139 case lir_cond_less: out->print("[LT]"); break;
2140 case lir_cond_lessEqual: out->print("[LE]"); break;
2141 case lir_cond_greaterEqual: out->print("[GE]"); break;
2142 case lir_cond_greater: out->print("[GT]"); break;
2143 case lir_cond_belowEqual: out->print("[BE]"); break;
2144 case lir_cond_aboveEqual: out->print("[AE]"); break;
2145 case lir_cond_always: out->print("[AL]"); break;
2146 default: out->print("[%d]",cond); break;
2147 }
2148 }
2150 // LIR_OpConvert
2151 void LIR_OpConvert::print_instr(outputStream* out) const {
2152 print_bytecode(out, bytecode());
2153 in_opr()->print(out); out->print(" ");
2154 result_opr()->print(out); out->print(" ");
2155 #ifdef PPC
2156 if(tmp1()->is_valid()) {
2157 tmp1()->print(out); out->print(" ");
2158 tmp2()->print(out); out->print(" ");
2159 }
2160 #endif
2161 }
2163 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2164 switch(code) {
2165 case Bytecodes::_d2f: out->print("[d2f] "); break;
2166 case Bytecodes::_d2i: out->print("[d2i] "); break;
2167 case Bytecodes::_d2l: out->print("[d2l] "); break;
2168 case Bytecodes::_f2d: out->print("[f2d] "); break;
2169 case Bytecodes::_f2i: out->print("[f2i] "); break;
2170 case Bytecodes::_f2l: out->print("[f2l] "); break;
2171 case Bytecodes::_i2b: out->print("[i2b] "); break;
2172 case Bytecodes::_i2c: out->print("[i2c] "); break;
2173 case Bytecodes::_i2d: out->print("[i2d] "); break;
2174 case Bytecodes::_i2f: out->print("[i2f] "); break;
2175 case Bytecodes::_i2l: out->print("[i2l] "); break;
2176 case Bytecodes::_i2s: out->print("[i2s] "); break;
2177 case Bytecodes::_l2i: out->print("[l2i] "); break;
2178 case Bytecodes::_l2f: out->print("[l2f] "); break;
2179 case Bytecodes::_l2d: out->print("[l2d] "); break;
2180 default:
2181 out->print("[?%d]",code);
2182 break;
2183 }
2184 }
2186 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2187 klass()->print(out); out->print(" ");
2188 obj()->print(out); out->print(" ");
2189 tmp1()->print(out); out->print(" ");
2190 tmp2()->print(out); out->print(" ");
2191 tmp3()->print(out); out->print(" ");
2192 tmp4()->print(out); out->print(" ");
2193 #ifdef MIPS
2194 tmp5()->print(out); out->print(" ");
2195 tmp6()->print(out); out->print(" ");
2196 #endif
2197 out->print("[hdr:%d]", header_size()); out->print(" ");
2198 out->print("[obj:%d]", object_size()); out->print(" ");
2199 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2200 }
2202 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2203 _opr->print(out); out->print(" ");
2204 tmp()->print(out); out->print(" ");
2205 result_opr()->print(out); out->print(" ");
2206 }
2208 // LIR_Op2
2209 void LIR_Op2::print_instr(outputStream* out) const {
2210 #ifndef MIPS
2211 if (code() == lir_cmove) {
2212 print_condition(out, condition()); out->print(" ");
2213 }
2214 #endif
2215 in_opr1()->print(out); out->print(" ");
2216 in_opr2()->print(out); out->print(" ");
2217 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2218 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2219 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2220 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2221 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2222 result_opr()->print(out);
2223 }
2225 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2226 klass()->print(out); out->print(" ");
2227 len()->print(out); out->print(" ");
2228 obj()->print(out); out->print(" ");
2229 tmp1()->print(out); out->print(" ");
2230 tmp2()->print(out); out->print(" ");
2231 tmp3()->print(out); out->print(" ");
2232 tmp4()->print(out); out->print(" ");
2233 #ifdef MIPS
2234 tmp5()->print(out); out->print(" ");
2235 #endif
2236 out->print("[type:0x%x]", type()); out->print(" ");
2237 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2238 }
2241 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2242 object()->print(out); out->print(" ");
2243 if (code() == lir_store_check) {
2244 array()->print(out); out->print(" ");
2245 }
2246 if (code() != lir_store_check) {
2247 klass()->print_name_on(out); out->print(" ");
2248 if (fast_check()) out->print("fast_check ");
2249 }
2250 tmp1()->print(out); out->print(" ");
2251 tmp2()->print(out); out->print(" ");
2252 tmp3()->print(out); out->print(" ");
2253 result_opr()->print(out); out->print(" ");
2254 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2255 }
2258 // LIR_Op3
2259 void LIR_Op3::print_instr(outputStream* out) const {
2260 in_opr1()->print(out); out->print(" ");
2261 in_opr2()->print(out); out->print(" ");
2262 in_opr3()->print(out); out->print(" ");
2263 result_opr()->print(out);
2264 }
2267 void LIR_OpLock::print_instr(outputStream* out) const {
2268 hdr_opr()->print(out); out->print(" ");
2269 obj_opr()->print(out); out->print(" ");
2270 lock_opr()->print(out); out->print(" ");
2271 if (_scratch->is_valid()) {
2272 _scratch->print(out); out->print(" ");
2273 }
2274 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2275 }
2277 #ifdef ASSERT
2278 void LIR_OpAssert::print_instr(outputStream* out) const {
2279 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2280 Unimplemented();
2281 /*
2282 print_condition(out, condition()); out->print(" ");
2283 in_opr1()->print(out); out->print(" ");
2284 in_opr2()->print(out); out->print(", \"");
2285 out->print("%s", msg()); out->print("\"");
2286 */
2287 }
2288 #endif
2291 void LIR_OpDelay::print_instr(outputStream* out) const {
2292 _op->print_on(out);
2293 }
2296 // LIR_OpProfileCall
2297 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2298 profiled_method()->name()->print_symbol_on(out);
2299 out->print(".");
2300 profiled_method()->holder()->name()->print_symbol_on(out);
2301 out->print(" @ %d ", profiled_bci());
2302 mdo()->print(out); out->print(" ");
2303 recv()->print(out); out->print(" ");
2304 tmp1()->print(out); out->print(" ");
2305 }
2307 // LIR_OpProfileType
2308 void LIR_OpProfileType::print_instr(outputStream* out) const {
2309 out->print("exact = "); exact_klass()->print_name_on(out);
2310 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2311 mdp()->print(out); out->print(" ");
2312 obj()->print(out); out->print(" ");
2313 tmp()->print(out); out->print(" ");
2314 }
2316 #endif // PRODUCT
2318 // Implementation of LIR_InsertionBuffer
2320 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2321 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2323 int i = number_of_insertion_points() - 1;
2324 if (i < 0 || index_at(i) < index) {
2325 append_new(index, 1);
2326 } else {
2327 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2328 assert(count_at(i) > 0, "check");
2329 set_count_at(i, count_at(i) + 1);
2330 }
2331 _ops.push(op);
2333 DEBUG_ONLY(verify());
2334 }
2336 #ifdef ASSERT
2337 void LIR_InsertionBuffer::verify() {
2338 int sum = 0;
2339 int prev_idx = -1;
2341 for (int i = 0; i < number_of_insertion_points(); i++) {
2342 assert(prev_idx < index_at(i), "index must be ordered ascending");
2343 sum += count_at(i);
2344 }
2345 assert(sum == number_of_ops(), "wrong total sum");
2346 }
2347 #endif
