diff -r dc1769738300 -r b56ab8e56604 src/share/vm/c1/c1_LIR.cpp
--- a/src/share/vm/c1/c1_LIR.cpp	Tue Jul 24 13:22:11 2018 +0800
+++ b/src/share/vm/c1/c1_LIR.cpp	Tue Jul 24 14:29:09 2018 +0800
@@ -61,7 +61,7 @@
 
 #endif // X86
 
-#if defined(SPARC) || defined(PPC) || defined(MIPS64)
+#if defined(SPARC) || defined(PPC) || defined(MIPS)
 
 FloatRegister LIR_OprDesc::as_float_reg() const {
   return FrameMap::nr2floatreg(fpu_regnr());
@@ -149,14 +149,14 @@
 
 #ifndef PRODUCT
 void LIR_Address::verify0() const {
-#if defined(SPARC) || defined(PPC) || defined(MIPS64)
+#if defined(SPARC) || defined(PPC) || defined(MIPS)
   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
   assert(disp() == 0 || index()->is_illegal(), "can't have both");
 #endif
 #ifdef _LP64
   assert(base()->is_cpu_register(), "wrong base operand");
   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
-#ifndef MIPS64
+#ifndef MIPS
   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
          "wrong type for addresses");
 #endif
@@ -306,7 +306,7 @@
 }
 
 
-#ifndef MIPS64
+#ifndef MIPS
 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
   , _cond(cond)
@@ -617,7 +617,7 @@
       assert(op->as_OpBranch() != NULL, "must be");
       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 
-#ifdef MIPS64
+#ifdef MIPS
       if (opBranch->_opr1->is_valid())         do_input(opBranch->_opr1);
       if (opBranch->_opr2->is_valid())         do_input(opBranch->_opr2);
       if (opBranch->_tmp1->is_valid())          do_temp(opBranch->_tmp1);
@@ -648,7 +648,7 @@
       if (opAllocObj->_tmp2->is_valid())         do_temp(opAllocObj->_tmp2);
       if (opAllocObj->_tmp3->is_valid())         do_temp(opAllocObj->_tmp3);
       if (opAllocObj->_tmp4->is_valid())         do_temp(opAllocObj->_tmp4);
-#ifdef MIPS64
+#ifdef MIPS
       if (opAllocObj->_tmp5->is_valid())         do_temp(opAllocObj->_tmp5);
       if (opAllocObj->_tmp6->is_valid())         do_temp(opAllocObj->_tmp6);
 #endif
@@ -673,7 +673,7 @@
 
 
 // LIR_Op2
-#ifdef MIPS64
+#ifdef MIPS
     case lir_null_check_for_branch:
 #else
     case lir_cmp:
@@ -845,7 +845,7 @@
     }
 
 // LIR_Op3
-#ifdef MIPS64
+#ifdef MIPS
     case lir_frem:
 #endif
     case lir_idiv:
@@ -932,7 +932,7 @@
       assert(opArrayCopy->_dst->is_valid(), "used");          do_input(opArrayCopy->_dst);     do_temp(opArrayCopy->_dst);
       assert(opArrayCopy->_dst_pos->is_valid(), "used");      do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
       assert(opArrayCopy->_length->is_valid(), "used");       do_input(opArrayCopy->_length);  do_temp(opArrayCopy->_length);
-#ifndef MIPS64
+#ifndef MIPS
       assert(opArrayCopy->_tmp->is_valid(), "used");          do_temp(opArrayCopy->_tmp);
 #endif
       if (opArrayCopy->_info)                     do_info(opArrayCopy->_info);
@@ -1049,7 +1049,7 @@
       if (opAllocArray->_tmp2->is_valid())            do_temp(opAllocArray->_tmp2);
       if (opAllocArray->_tmp3->is_valid())            do_temp(opAllocArray->_tmp3);
       if (opAllocArray->_tmp4->is_valid())            do_temp(opAllocArray->_tmp4);
-#ifdef MIPS64
+#ifdef MIPS
       if (opAllocArray->_tmp5->is_valid())            do_temp(opAllocArray->_tmp5);
 #endif
       if (opAllocArray->_result->is_valid())          do_output(opAllocArray->_result);
@@ -1322,7 +1322,7 @@
 }
 
 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
-#ifdef MIPS64
+#ifdef MIPS
   add(base, offset, base);
   offset = 0;
 #endif
@@ -1388,7 +1388,7 @@
 }
 
 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
-#ifdef MIPS64
+#ifdef MIPS
   add(base, offset, base);
   offset = 0;
 #endif
@@ -1401,7 +1401,7 @@
             info, lir_move_volatile));
 }
 
-#ifdef MIPS64
+#ifdef MIPS
 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
   append(new LIR_Op3(
                     lir_frem,
@@ -1457,7 +1457,7 @@
 }
 
 
-#ifndef MIPS64
+#ifndef MIPS
 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
   append(new LIR_Op2(
                     lir_cmp,
@@ -1481,7 +1481,7 @@
   if (deoptimize_on_null) {
     // Emit an explicit null check and deoptimize if opr is null
     CodeStub* deopt = new DeoptimizeStub(info);
-#ifndef MIPS64
+#ifndef MIPS
     cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
     branch(lir_cond_equal, T_OBJECT, deopt);
 #else
@@ -1494,7 +1494,7 @@
   }
 }
 
-#ifndef MIPS64
+#ifndef MIPS
 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
                                int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
   append(new LIR_OpAllocObj(
@@ -1658,7 +1658,7 @@
 }
 
 
-#ifndef MIPS64
+#ifndef MIPS
 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
                         LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
   append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
@@ -1795,7 +1795,7 @@
 // LIR_Address
 void LIR_Address::print_value_on(outputStream* out) const {
   out->print("Base:"); _base->print(out);
-#ifndef MIPS64
+#ifndef MIPS
   if (!_index->is_illegal()) {
     out->print(" Index:"); _index->print(out);
     switch (scale()) {
@@ -1937,7 +1937,7 @@
      case lir_pack64:                s = "pack64";        break;
      case lir_unpack64:              s = "unpack64";      break;
      // LIR_Op2
-#ifdef MIPS64
+#ifdef MIPS
      case lir_null_check_for_branch: s = "null_check_for_branch"; break;
 #else
      case lir_cmp:                   s = "cmp";           break;
@@ -1972,7 +1972,7 @@
      case lir_xadd:                  s = "xadd";          break;
      case lir_xchg:                  s = "xchg";          break;
      // LIR_Op3
-#ifdef MIPS64
+#ifdef MIPS
      case lir_frem:                  s = "frem";          break;
 #endif
      case lir_idiv:                  s = "idiv";          break;
@@ -2113,7 +2113,7 @@
 // LIR_OpBranch
 void LIR_OpBranch::print_instr(outputStream* out) const {
   print_condition(out, cond());             out->print(" ");
-#ifdef MIPS64
+#ifdef MIPS
   in_opr1()->print(out); out->print(" ");
   in_opr2()->print(out); out->print(" ");
 #endif
@@ -2190,7 +2190,7 @@
   tmp2()->print(out);                       out->print(" ");
   tmp3()->print(out);                       out->print(" ");
   tmp4()->print(out);                       out->print(" ");
-#ifdef MIPS64
+#ifdef MIPS
   tmp5()->print(out);                       out->print(" ");
   tmp6()->print(out);                       out->print(" ");
 #endif
@@ -2207,7 +2207,7 @@
 
 // LIR_Op2
 void LIR_Op2::print_instr(outputStream* out) const {
-#ifndef MIPS64
+#ifndef MIPS
   if (code() == lir_cmove) {
     print_condition(out, condition());         out->print(" ");
   }
@@ -2230,7 +2230,7 @@
   tmp2()->print(out);                    out->print(" ");
   tmp3()->print(out);                    out->print(" ");
   tmp4()->print(out);                    out->print(" ");
-#ifdef MIPS64
+#ifdef MIPS
   tmp5()->print(out);                    out->print(" ");
 #endif
   out->print("[type:0x%x]", type());     out->print(" ");