1.1 --- a/src/share/vm/c1/c1_LIR.cpp Tue Jul 24 13:22:11 2018 +0800
1.2 +++ b/src/share/vm/c1/c1_LIR.cpp Tue Jul 24 14:29:09 2018 +0800
1.3 @@ -61,7 +61,7 @@
1.4
1.5 #endif // X86
1.6
1.7 -#if defined(SPARC) || defined(PPC) || defined(MIPS64)
1.8 +#if defined(SPARC) || defined(PPC) || defined(MIPS)
1.9
1.10 FloatRegister LIR_OprDesc::as_float_reg() const {
1.11 return FrameMap::nr2floatreg(fpu_regnr());
1.12 @@ -149,14 +149,14 @@
1.13
1.14 #ifndef PRODUCT
1.15 void LIR_Address::verify0() const {
1.16 -#if defined(SPARC) || defined(PPC) || defined(MIPS64)
1.17 +#if defined(SPARC) || defined(PPC) || defined(MIPS)
1.18 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
1.19 assert(disp() == 0 || index()->is_illegal(), "can't have both");
1.20 #endif
1.21 #ifdef _LP64
1.22 assert(base()->is_cpu_register(), "wrong base operand");
1.23 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
1.24 -#ifndef MIPS64
1.25 +#ifndef MIPS
1.26 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
1.27 "wrong type for addresses");
1.28 #endif
1.29 @@ -306,7 +306,7 @@
1.30 }
1.31
1.32
1.33 -#ifndef MIPS64
1.34 +#ifndef MIPS
1.35 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
1.36 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
1.37 , _cond(cond)
1.38 @@ -617,7 +617,7 @@
1.39 assert(op->as_OpBranch() != NULL, "must be");
1.40 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
1.41
1.42 -#ifdef MIPS64
1.43 +#ifdef MIPS
1.44 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
1.45 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
1.46 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
1.47 @@ -648,7 +648,7 @@
1.48 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
1.49 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
1.50 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
1.51 -#ifdef MIPS64
1.52 +#ifdef MIPS
1.53 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
1.54 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
1.55 #endif
1.56 @@ -673,7 +673,7 @@
1.57
1.58
1.59 // LIR_Op2
1.60 -#ifdef MIPS64
1.61 +#ifdef MIPS
1.62 case lir_null_check_for_branch:
1.63 #else
1.64 case lir_cmp:
1.65 @@ -845,7 +845,7 @@
1.66 }
1.67
1.68 // LIR_Op3
1.69 -#ifdef MIPS64
1.70 +#ifdef MIPS
1.71 case lir_frem:
1.72 #endif
1.73 case lir_idiv:
1.74 @@ -932,7 +932,7 @@
1.75 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
1.76 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
1.77 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
1.78 -#ifndef MIPS64
1.79 +#ifndef MIPS
1.80 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
1.81 #endif
1.82 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1.83 @@ -1049,7 +1049,7 @@
1.84 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1.85 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1.86 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1.87 -#ifdef MIPS64
1.88 +#ifdef MIPS
1.89 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1.90 #endif
1.91 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1.92 @@ -1322,7 +1322,7 @@
1.93 }
1.94
1.95 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.96 -#ifdef MIPS64
1.97 +#ifdef MIPS
1.98 add(base, offset, base);
1.99 offset = 0;
1.100 #endif
1.101 @@ -1388,7 +1388,7 @@
1.102 }
1.103
1.104 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.105 -#ifdef MIPS64
1.106 +#ifdef MIPS
1.107 add(base, offset, base);
1.108 offset = 0;
1.109 #endif
1.110 @@ -1401,7 +1401,7 @@
1.111 info, lir_move_volatile));
1.112 }
1.113
1.114 -#ifdef MIPS64
1.115 +#ifdef MIPS
1.116 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1.117 append(new LIR_Op3(
1.118 lir_frem,
1.119 @@ -1457,7 +1457,7 @@
1.120 }
1.121
1.122
1.123 -#ifndef MIPS64
1.124 +#ifndef MIPS
1.125 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1.126 append(new LIR_Op2(
1.127 lir_cmp,
1.128 @@ -1481,7 +1481,7 @@
1.129 if (deoptimize_on_null) {
1.130 // Emit an explicit null check and deoptimize if opr is null
1.131 CodeStub* deopt = new DeoptimizeStub(info);
1.132 -#ifndef MIPS64
1.133 +#ifndef MIPS
1.134 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1.135 branch(lir_cond_equal, T_OBJECT, deopt);
1.136 #else
1.137 @@ -1494,7 +1494,7 @@
1.138 }
1.139 }
1.140
1.141 -#ifndef MIPS64
1.142 +#ifndef MIPS
1.143 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1.144 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1.145 append(new LIR_OpAllocObj(
1.146 @@ -1658,7 +1658,7 @@
1.147 }
1.148
1.149
1.150 -#ifndef MIPS64
1.151 +#ifndef MIPS
1.152 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.153 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.154 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1.155 @@ -1795,7 +1795,7 @@
1.156 // LIR_Address
1.157 void LIR_Address::print_value_on(outputStream* out) const {
1.158 out->print("Base:"); _base->print(out);
1.159 -#ifndef MIPS64
1.160 +#ifndef MIPS
1.161 if (!_index->is_illegal()) {
1.162 out->print(" Index:"); _index->print(out);
1.163 switch (scale()) {
1.164 @@ -1937,7 +1937,7 @@
1.165 case lir_pack64: s = "pack64"; break;
1.166 case lir_unpack64: s = "unpack64"; break;
1.167 // LIR_Op2
1.168 -#ifdef MIPS64
1.169 +#ifdef MIPS
1.170 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1.171 #else
1.172 case lir_cmp: s = "cmp"; break;
1.173 @@ -1972,7 +1972,7 @@
1.174 case lir_xadd: s = "xadd"; break;
1.175 case lir_xchg: s = "xchg"; break;
1.176 // LIR_Op3
1.177 -#ifdef MIPS64
1.178 +#ifdef MIPS
1.179 case lir_frem: s = "frem"; break;
1.180 #endif
1.181 case lir_idiv: s = "idiv"; break;
1.182 @@ -2113,7 +2113,7 @@
1.183 // LIR_OpBranch
1.184 void LIR_OpBranch::print_instr(outputStream* out) const {
1.185 print_condition(out, cond()); out->print(" ");
1.186 -#ifdef MIPS64
1.187 +#ifdef MIPS
1.188 in_opr1()->print(out); out->print(" ");
1.189 in_opr2()->print(out); out->print(" ");
1.190 #endif
1.191 @@ -2190,7 +2190,7 @@
1.192 tmp2()->print(out); out->print(" ");
1.193 tmp3()->print(out); out->print(" ");
1.194 tmp4()->print(out); out->print(" ");
1.195 -#ifdef MIPS64
1.196 +#ifdef MIPS
1.197 tmp5()->print(out); out->print(" ");
1.198 tmp6()->print(out); out->print(" ");
1.199 #endif
1.200 @@ -2207,7 +2207,7 @@
1.201
1.202 // LIR_Op2
1.203 void LIR_Op2::print_instr(outputStream* out) const {
1.204 -#ifndef MIPS64
1.205 +#ifndef MIPS
1.206 if (code() == lir_cmove) {
1.207 print_condition(out, condition()); out->print(" ");
1.208 }
1.209 @@ -2230,7 +2230,7 @@
1.210 tmp2()->print(out); out->print(" ");
1.211 tmp3()->print(out); out->print(" ");
1.212 tmp4()->print(out); out->print(" ");
1.213 -#ifdef MIPS64
1.214 +#ifdef MIPS
1.215 tmp5()->print(out); out->print(" ");
1.216 #endif
1.217 out->print("[type:0x%x]", type()); out->print(" ");
