Wed, 18 Sep 2013 14:34:56 -0700
8024342: PPC64 (part 111): Support for C calling conventions that require 64-bit ints.
Summary: Some platforms, as ppc and s390x/zArch require that 32-bit ints are passed as 64-bit values to C functions. This change adds support to adapt the signature and to issue proper casts to c2-compiled stubs. The functions are used in generate_native_wrapper(). Adapt signature used by the compiler as in PhaseIdealLoop::intrinsify_fill().
Reviewed-by: kvn
duke@435 | 1 | /* |
drchase@5285 | 2 | * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "compiler/compileLog.hpp" |
stefank@2314 | 27 | #include "compiler/oopMap.hpp" |
stefank@2314 | 28 | #include "memory/allocation.inline.hpp" |
stefank@2314 | 29 | #include "opto/addnode.hpp" |
stefank@2314 | 30 | #include "opto/block.hpp" |
stefank@2314 | 31 | #include "opto/callnode.hpp" |
stefank@2314 | 32 | #include "opto/cfgnode.hpp" |
stefank@2314 | 33 | #include "opto/chaitin.hpp" |
stefank@2314 | 34 | #include "opto/coalesce.hpp" |
stefank@2314 | 35 | #include "opto/connode.hpp" |
stefank@2314 | 36 | #include "opto/idealGraphPrinter.hpp" |
stefank@2314 | 37 | #include "opto/indexSet.hpp" |
stefank@2314 | 38 | #include "opto/machnode.hpp" |
stefank@2314 | 39 | #include "opto/memnode.hpp" |
stefank@2314 | 40 | #include "opto/opcodes.hpp" |
stefank@2314 | 41 | #include "opto/rootnode.hpp" |
duke@435 | 42 | |
duke@435 | 43 | #ifndef PRODUCT |
adlertz@5539 | 44 | void LRG::dump() const { |
duke@435 | 45 | ttyLocker ttyl; |
duke@435 | 46 | tty->print("%d ",num_regs()); |
duke@435 | 47 | _mask.dump(); |
duke@435 | 48 | if( _msize_valid ) { |
duke@435 | 49 | if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); |
duke@435 | 50 | else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); |
duke@435 | 51 | } else { |
duke@435 | 52 | tty->print(", #?(%d) ",_mask.Size()); |
duke@435 | 53 | } |
duke@435 | 54 | |
duke@435 | 55 | tty->print("EffDeg: "); |
duke@435 | 56 | if( _degree_valid ) tty->print( "%d ", _eff_degree ); |
duke@435 | 57 | else tty->print("? "); |
duke@435 | 58 | |
never@730 | 59 | if( is_multidef() ) { |
duke@435 | 60 | tty->print("MultiDef "); |
duke@435 | 61 | if (_defs != NULL) { |
duke@435 | 62 | tty->print("("); |
duke@435 | 63 | for (int i = 0; i < _defs->length(); i++) { |
duke@435 | 64 | tty->print("N%d ", _defs->at(i)->_idx); |
duke@435 | 65 | } |
duke@435 | 66 | tty->print(") "); |
duke@435 | 67 | } |
duke@435 | 68 | } |
duke@435 | 69 | else if( _def == 0 ) tty->print("Dead "); |
duke@435 | 70 | else tty->print("Def: N%d ",_def->_idx); |
duke@435 | 71 | |
duke@435 | 72 | tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); |
duke@435 | 73 | // Flags |
duke@435 | 74 | if( _is_oop ) tty->print("Oop "); |
duke@435 | 75 | if( _is_float ) tty->print("Float "); |
kvn@3882 | 76 | if( _is_vector ) tty->print("Vector "); |
duke@435 | 77 | if( _was_spilled1 ) tty->print("Spilled "); |
duke@435 | 78 | if( _was_spilled2 ) tty->print("Spilled2 "); |
duke@435 | 79 | if( _direct_conflict ) tty->print("Direct_conflict "); |
duke@435 | 80 | if( _fat_proj ) tty->print("Fat "); |
duke@435 | 81 | if( _was_lo ) tty->print("Lo "); |
duke@435 | 82 | if( _has_copy ) tty->print("Copy "); |
duke@435 | 83 | if( _at_risk ) tty->print("Risk "); |
duke@435 | 84 | |
duke@435 | 85 | if( _must_spill ) tty->print("Must_spill "); |
duke@435 | 86 | if( _is_bound ) tty->print("Bound "); |
duke@435 | 87 | if( _msize_valid ) { |
duke@435 | 88 | if( _degree_valid && lo_degree() ) tty->print("Trivial "); |
duke@435 | 89 | } |
duke@435 | 90 | |
duke@435 | 91 | tty->cr(); |
duke@435 | 92 | } |
duke@435 | 93 | #endif |
duke@435 | 94 | |
duke@435 | 95 | // Compute score from cost and area. Low score is best to spill. |
duke@435 | 96 | static double raw_score( double cost, double area ) { |
duke@435 | 97 | return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; |
duke@435 | 98 | } |
duke@435 | 99 | |
duke@435 | 100 | double LRG::score() const { |
duke@435 | 101 | // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. |
duke@435 | 102 | // Bigger area lowers score, encourages spilling this live range. |
duke@435 | 103 | // Bigger cost raise score, prevents spilling this live range. |
duke@435 | 104 | // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer |
duke@435 | 105 | // to turn a divide by a constant into a multiply by the reciprical). |
duke@435 | 106 | double score = raw_score( _cost, _area); |
duke@435 | 107 | |
duke@435 | 108 | // Account for area. Basically, LRGs covering large areas are better |
duke@435 | 109 | // to spill because more other LRGs get freed up. |
duke@435 | 110 | if( _area == 0.0 ) // No area? Then no progress to spill |
duke@435 | 111 | return 1e35; |
duke@435 | 112 | |
duke@435 | 113 | if( _was_spilled2 ) // If spilled once before, we are unlikely |
duke@435 | 114 | return score + 1e30; // to make progress again. |
duke@435 | 115 | |
duke@435 | 116 | if( _cost >= _area*3.0 ) // Tiny area relative to cost |
duke@435 | 117 | return score + 1e17; // Probably no progress to spill |
duke@435 | 118 | |
duke@435 | 119 | if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost |
duke@435 | 120 | return score + 1e10; // Likely no progress to spill |
duke@435 | 121 | |
duke@435 | 122 | return score; |
duke@435 | 123 | } |
duke@435 | 124 | |
duke@435 | 125 | LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { |
duke@435 | 126 | memset( _lidxs, 0, sizeof(uint)*max ); |
duke@435 | 127 | } |
duke@435 | 128 | |
duke@435 | 129 | void LRG_List::extend( uint nidx, uint lidx ) { |
duke@435 | 130 | _nesting.check(); |
duke@435 | 131 | if( nidx >= _max ) { |
duke@435 | 132 | uint size = 16; |
duke@435 | 133 | while( size <= nidx ) size <<=1; |
duke@435 | 134 | _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size ); |
duke@435 | 135 | _max = size; |
duke@435 | 136 | } |
duke@435 | 137 | while( _cnt <= nidx ) |
duke@435 | 138 | _lidxs[_cnt++] = 0; |
duke@435 | 139 | _lidxs[nidx] = lidx; |
duke@435 | 140 | } |
duke@435 | 141 | |
duke@435 | 142 | #define NUMBUCKS 3 |
duke@435 | 143 | |
neliasso@4949 | 144 | // Straight out of Tarjan's union-find algorithm |
neliasso@4949 | 145 | uint LiveRangeMap::find_compress(uint lrg) { |
neliasso@4949 | 146 | uint cur = lrg; |
neliasso@4949 | 147 | uint next = _uf_map[cur]; |
neliasso@4949 | 148 | while (next != cur) { // Scan chain of equivalences |
neliasso@4949 | 149 | assert( next < cur, "always union smaller"); |
neliasso@4949 | 150 | cur = next; // until find a fixed-point |
neliasso@4949 | 151 | next = _uf_map[cur]; |
neliasso@4949 | 152 | } |
neliasso@4949 | 153 | |
neliasso@4949 | 154 | // Core of union-find algorithm: update chain of |
neliasso@4949 | 155 | // equivalences to be equal to the root. |
neliasso@4949 | 156 | while (lrg != next) { |
neliasso@4949 | 157 | uint tmp = _uf_map[lrg]; |
neliasso@4949 | 158 | _uf_map.map(lrg, next); |
neliasso@4949 | 159 | lrg = tmp; |
neliasso@4949 | 160 | } |
neliasso@4949 | 161 | return lrg; |
neliasso@4949 | 162 | } |
neliasso@4949 | 163 | |
neliasso@4949 | 164 | // Reset the Union-Find map to identity |
neliasso@4949 | 165 | void LiveRangeMap::reset_uf_map(uint max_lrg_id) { |
neliasso@4949 | 166 | _max_lrg_id= max_lrg_id; |
neliasso@4949 | 167 | // Force the Union-Find mapping to be at least this large |
neliasso@4949 | 168 | _uf_map.extend(_max_lrg_id, 0); |
neliasso@4949 | 169 | // Initialize it to be the ID mapping. |
neliasso@4949 | 170 | for (uint i = 0; i < _max_lrg_id; ++i) { |
neliasso@4949 | 171 | _uf_map.map(i, i); |
neliasso@4949 | 172 | } |
neliasso@4949 | 173 | } |
neliasso@4949 | 174 | |
neliasso@4949 | 175 | // Make all Nodes map directly to their final live range; no need for |
neliasso@4949 | 176 | // the Union-Find mapping after this call. |
neliasso@4949 | 177 | void LiveRangeMap::compress_uf_map_for_nodes() { |
neliasso@4949 | 178 | // For all Nodes, compress mapping |
neliasso@4949 | 179 | uint unique = _names.Size(); |
neliasso@4949 | 180 | for (uint i = 0; i < unique; ++i) { |
neliasso@4949 | 181 | uint lrg = _names[i]; |
neliasso@4949 | 182 | uint compressed_lrg = find(lrg); |
neliasso@4949 | 183 | if (lrg != compressed_lrg) { |
neliasso@4949 | 184 | _names.map(i, compressed_lrg); |
neliasso@4949 | 185 | } |
neliasso@4949 | 186 | } |
neliasso@4949 | 187 | } |
neliasso@4949 | 188 | |
neliasso@4949 | 189 | // Like Find above, but no path compress, so bad asymptotic behavior |
neliasso@4949 | 190 | uint LiveRangeMap::find_const(uint lrg) const { |
neliasso@4949 | 191 | if (!lrg) { |
neliasso@4949 | 192 | return lrg; // Ignore the zero LRG |
neliasso@4949 | 193 | } |
neliasso@4949 | 194 | |
neliasso@4949 | 195 | // Off the end? This happens during debugging dumps when you got |
neliasso@4949 | 196 | // brand new live ranges but have not told the allocator yet. |
neliasso@4949 | 197 | if (lrg >= _max_lrg_id) { |
neliasso@4949 | 198 | return lrg; |
neliasso@4949 | 199 | } |
neliasso@4949 | 200 | |
neliasso@4949 | 201 | uint next = _uf_map[lrg]; |
neliasso@4949 | 202 | while (next != lrg) { // Scan chain of equivalences |
neliasso@4949 | 203 | assert(next < lrg, "always union smaller"); |
neliasso@4949 | 204 | lrg = next; // until find a fixed-point |
neliasso@4949 | 205 | next = _uf_map[lrg]; |
neliasso@4949 | 206 | } |
neliasso@4949 | 207 | return next; |
neliasso@4949 | 208 | } |
neliasso@4949 | 209 | |
duke@435 | 210 | PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) |
duke@435 | 211 | : PhaseRegAlloc(unique, cfg, matcher, |
duke@435 | 212 | #ifndef PRODUCT |
duke@435 | 213 | print_chaitin_statistics |
duke@435 | 214 | #else |
duke@435 | 215 | NULL |
duke@435 | 216 | #endif |
neliasso@4949 | 217 | ) |
neliasso@4949 | 218 | , _lrg_map(unique) |
neliasso@4949 | 219 | , _live(0) |
neliasso@4949 | 220 | , _spilled_once(Thread::current()->resource_area()) |
neliasso@4949 | 221 | , _spilled_twice(Thread::current()->resource_area()) |
neliasso@4949 | 222 | , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0) |
neliasso@4949 | 223 | , _oldphi(unique) |
duke@435 | 224 | #ifndef PRODUCT |
duke@435 | 225 | , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) |
duke@435 | 226 | #endif |
duke@435 | 227 | { |
duke@435 | 228 | NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) |
kvn@1108 | 229 | |
adlertz@5539 | 230 | _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); |
kvn@1108 | 231 | |
duke@435 | 232 | // Build a list of basic blocks, sorted by frequency |
adlertz@5539 | 233 | _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
duke@435 | 234 | // Experiment with sorting strategies to speed compilation |
duke@435 | 235 | double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket |
duke@435 | 236 | Block **buckets[NUMBUCKS]; // Array of buckets |
duke@435 | 237 | uint buckcnt[NUMBUCKS]; // Array of bucket counters |
duke@435 | 238 | double buckval[NUMBUCKS]; // Array of bucket value cutoffs |
neliasso@4949 | 239 | for (uint i = 0; i < NUMBUCKS; i++) { |
adlertz@5539 | 240 | buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
duke@435 | 241 | buckcnt[i] = 0; |
duke@435 | 242 | // Bump by three orders of magnitude each time |
duke@435 | 243 | cutoff *= 0.001; |
duke@435 | 244 | buckval[i] = cutoff; |
adlertz@5539 | 245 | for (uint j = 0; j < _cfg.number_of_blocks(); j++) { |
duke@435 | 246 | buckets[i][j] = NULL; |
duke@435 | 247 | } |
duke@435 | 248 | } |
duke@435 | 249 | // Sort blocks into buckets |
adlertz@5539 | 250 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
neliasso@4949 | 251 | for (uint j = 0; j < NUMBUCKS; j++) { |
adlertz@5539 | 252 | if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { |
duke@435 | 253 | // Assign block to end of list for appropriate bucket |
adlertz@5539 | 254 | buckets[j][buckcnt[j]++] = _cfg.get_block(i); |
neliasso@4949 | 255 | break; // kick out of inner loop |
duke@435 | 256 | } |
duke@435 | 257 | } |
duke@435 | 258 | } |
duke@435 | 259 | // Dump buckets into final block array |
duke@435 | 260 | uint blkcnt = 0; |
neliasso@4949 | 261 | for (uint i = 0; i < NUMBUCKS; i++) { |
neliasso@4949 | 262 | for (uint j = 0; j < buckcnt[i]; j++) { |
duke@435 | 263 | _blks[blkcnt++] = buckets[i][j]; |
duke@435 | 264 | } |
duke@435 | 265 | } |
duke@435 | 266 | |
adlertz@5539 | 267 | assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); |
duke@435 | 268 | } |
duke@435 | 269 | |
neliasso@4949 | 270 | // union 2 sets together. |
neliasso@4949 | 271 | void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { |
neliasso@4949 | 272 | uint src = _lrg_map.find(src_n); |
neliasso@4949 | 273 | uint dst = _lrg_map.find(dst_n); |
neliasso@4949 | 274 | assert(src, ""); |
neliasso@4949 | 275 | assert(dst, ""); |
neliasso@4949 | 276 | assert(src < _lrg_map.max_lrg_id(), "oob"); |
neliasso@4949 | 277 | assert(dst < _lrg_map.max_lrg_id(), "oob"); |
neliasso@4949 | 278 | assert(src < dst, "always union smaller"); |
neliasso@4949 | 279 | _lrg_map.uf_map(dst, src); |
neliasso@4949 | 280 | } |
neliasso@4949 | 281 | |
neliasso@4949 | 282 | void PhaseChaitin::new_lrg(const Node *x, uint lrg) { |
neliasso@4949 | 283 | // Make the Node->LRG mapping |
neliasso@4949 | 284 | _lrg_map.extend(x->_idx,lrg); |
neliasso@4949 | 285 | // Make the Union-Find mapping an identity function |
neliasso@4949 | 286 | _lrg_map.uf_extend(lrg, lrg); |
neliasso@4949 | 287 | } |
neliasso@4949 | 288 | |
neliasso@4949 | 289 | |
kvn@5543 | 290 | int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) { |
kvn@5543 | 291 | assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections"); |
kvn@5543 | 292 | DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); ) |
kvn@5543 | 293 | int found_projs = 0; |
kvn@5543 | 294 | uint cnt = orig->outcnt(); |
kvn@5543 | 295 | for (uint i = 0; i < cnt; i++) { |
kvn@5543 | 296 | Node* proj = orig->raw_out(i); |
kvn@5543 | 297 | if (proj->is_MachProj()) { |
kvn@5543 | 298 | assert(proj->outcnt() == 0, "only kill projections are expected here"); |
kvn@5543 | 299 | assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections"); |
kvn@5543 | 300 | found_projs++; |
kvn@5543 | 301 | // Copy kill projections after the cloned node |
kvn@5543 | 302 | Node* kills = proj->clone(); |
kvn@5543 | 303 | kills->set_req(0, copy); |
kvn@5543 | 304 | b->_nodes.insert(idx++, kills); |
kvn@5543 | 305 | _cfg.map_node_to_block(kills, b); |
kvn@5543 | 306 | new_lrg(kills, max_lrg_id++); |
kvn@5543 | 307 | } |
neliasso@4949 | 308 | } |
kvn@5543 | 309 | return found_projs; |
neliasso@4949 | 310 | } |
neliasso@4949 | 311 | |
neliasso@4949 | 312 | // Renumber the live ranges to compact them. Makes the IFG smaller. |
neliasso@4949 | 313 | void PhaseChaitin::compact() { |
neliasso@4949 | 314 | // Current the _uf_map contains a series of short chains which are headed |
neliasso@4949 | 315 | // by a self-cycle. All the chains run from big numbers to little numbers. |
neliasso@4949 | 316 | // The Find() call chases the chains & shortens them for the next Find call. |
neliasso@4949 | 317 | // We are going to change this structure slightly. Numbers above a moving |
neliasso@4949 | 318 | // wave 'i' are unchanged. Numbers below 'j' point directly to their |
neliasso@4949 | 319 | // compacted live range with no further chaining. There are no chains or |
neliasso@4949 | 320 | // cycles below 'i', so the Find call no longer works. |
neliasso@4949 | 321 | uint j=1; |
neliasso@4949 | 322 | uint i; |
neliasso@4949 | 323 | for (i = 1; i < _lrg_map.max_lrg_id(); i++) { |
neliasso@4949 | 324 | uint lr = _lrg_map.uf_live_range_id(i); |
neliasso@4949 | 325 | // Ignore unallocated live ranges |
neliasso@4949 | 326 | if (!lr) { |
neliasso@4949 | 327 | continue; |
neliasso@4949 | 328 | } |
neliasso@4949 | 329 | assert(lr <= i, ""); |
neliasso@4949 | 330 | _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr)); |
neliasso@4949 | 331 | } |
neliasso@4949 | 332 | // Now change the Node->LR mapping to reflect the compacted names |
neliasso@4949 | 333 | uint unique = _lrg_map.size(); |
neliasso@4949 | 334 | for (i = 0; i < unique; i++) { |
neliasso@4949 | 335 | uint lrg_id = _lrg_map.live_range_id(i); |
neliasso@4949 | 336 | _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id)); |
neliasso@4949 | 337 | } |
neliasso@4949 | 338 | |
neliasso@4949 | 339 | // Reset the Union-Find mapping |
neliasso@4949 | 340 | _lrg_map.reset_uf_map(j); |
neliasso@4949 | 341 | } |
neliasso@4949 | 342 | |
duke@435 | 343 | void PhaseChaitin::Register_Allocate() { |
duke@435 | 344 | |
duke@435 | 345 | // Above the OLD FP (and in registers) are the incoming arguments. Stack |
duke@435 | 346 | // slots in this area are called "arg_slots". Above the NEW FP (and in |
duke@435 | 347 | // registers) is the outgoing argument area; above that is the spill/temp |
duke@435 | 348 | // area. These are all "frame_slots". Arg_slots start at the zero |
duke@435 | 349 | // stack_slots and count up to the known arg_size. Frame_slots start at |
duke@435 | 350 | // the stack_slot #arg_size and go up. After allocation I map stack |
duke@435 | 351 | // slots to actual offsets. Stack-slots in the arg_slot area are biased |
duke@435 | 352 | // by the frame_size; stack-slots in the frame_slot area are biased by 0. |
duke@435 | 353 | |
duke@435 | 354 | _trip_cnt = 0; |
duke@435 | 355 | _alternate = 0; |
duke@435 | 356 | _matcher._allocation_started = true; |
duke@435 | 357 | |
kvn@4019 | 358 | ResourceArea split_arena; // Arena for Split local resources |
duke@435 | 359 | ResourceArea live_arena; // Arena for liveness & IFG info |
duke@435 | 360 | ResourceMark rm(&live_arena); |
duke@435 | 361 | |
duke@435 | 362 | // Need live-ness for the IFG; need the IFG for coalescing. If the |
duke@435 | 363 | // liveness is JUST for coalescing, then I can get some mileage by renaming |
duke@435 | 364 | // all copy-related live ranges low and then using the max copy-related |
duke@435 | 365 | // live range as a cut-off for LIVE and the IFG. In other words, I can |
duke@435 | 366 | // build a subset of LIVE and IFG just for copies. |
neliasso@4949 | 367 | PhaseLive live(_cfg, _lrg_map.names(), &live_arena); |
duke@435 | 368 | |
duke@435 | 369 | // Need IFG for coalescing and coloring |
neliasso@4949 | 370 | PhaseIFG ifg(&live_arena); |
duke@435 | 371 | _ifg = &ifg; |
duke@435 | 372 | |
duke@435 | 373 | // Come out of SSA world to the Named world. Assign (virtual) registers to |
duke@435 | 374 | // Nodes. Use the same register for all inputs and the output of PhiNodes |
duke@435 | 375 | // - effectively ending SSA form. This requires either coalescing live |
duke@435 | 376 | // ranges or inserting copies. For the moment, we insert "virtual copies" |
duke@435 | 377 | // - we pretend there is a copy prior to each Phi in predecessor blocks. |
duke@435 | 378 | // We will attempt to coalesce such "virtual copies" before we manifest |
duke@435 | 379 | // them for real. |
duke@435 | 380 | de_ssa(); |
duke@435 | 381 | |
kvn@1001 | 382 | #ifdef ASSERT |
kvn@1001 | 383 | // Veify the graph before RA. |
kvn@1001 | 384 | verify(&live_arena); |
kvn@1001 | 385 | #endif |
kvn@1001 | 386 | |
duke@435 | 387 | { |
duke@435 | 388 | NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) |
duke@435 | 389 | _live = NULL; // Mark live as being not available |
duke@435 | 390 | rm.reset_to_mark(); // Reclaim working storage |
duke@435 | 391 | IndexSet::reset_memory(C, &live_arena); |
neliasso@4949 | 392 | ifg.init(_lrg_map.max_lrg_id()); // Empty IFG |
duke@435 | 393 | gather_lrg_masks( false ); // Collect LRG masks |
neliasso@4949 | 394 | live.compute(_lrg_map.max_lrg_id()); // Compute liveness |
duke@435 | 395 | _live = &live; // Mark LIVE as being available |
duke@435 | 396 | } |
duke@435 | 397 | |
duke@435 | 398 | // Base pointers are currently "used" by instructions which define new |
duke@435 | 399 | // derived pointers. This makes base pointers live up to the where the |
duke@435 | 400 | // derived pointer is made, but not beyond. Really, they need to be live |
duke@435 | 401 | // across any GC point where the derived value is live. So this code looks |
duke@435 | 402 | // at all the GC points, and "stretches" the live range of any base pointer |
duke@435 | 403 | // to the GC point. |
neliasso@4949 | 404 | if (stretch_base_pointer_live_ranges(&live_arena)) { |
neliasso@4949 | 405 | NOT_PRODUCT(Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler);) |
duke@435 | 406 | // Since some live range stretched, I need to recompute live |
duke@435 | 407 | _live = NULL; |
duke@435 | 408 | rm.reset_to_mark(); // Reclaim working storage |
duke@435 | 409 | IndexSet::reset_memory(C, &live_arena); |
neliasso@4949 | 410 | ifg.init(_lrg_map.max_lrg_id()); |
neliasso@4949 | 411 | gather_lrg_masks(false); |
neliasso@4949 | 412 | live.compute(_lrg_map.max_lrg_id()); |
duke@435 | 413 | _live = &live; |
duke@435 | 414 | } |
duke@435 | 415 | // Create the interference graph using virtual copies |
neliasso@4949 | 416 | build_ifg_virtual(); // Include stack slots this time |
duke@435 | 417 | |
duke@435 | 418 | // Aggressive (but pessimistic) copy coalescing. |
duke@435 | 419 | // This pass works on virtual copies. Any virtual copies which are not |
duke@435 | 420 | // coalesced get manifested as actual copies |
duke@435 | 421 | { |
duke@435 | 422 | // The IFG is/was triangular. I am 'squaring it up' so Union can run |
duke@435 | 423 | // faster. Union requires a 'for all' operation which is slow on the |
duke@435 | 424 | // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - |
duke@435 | 425 | // meaning I can visit all the Nodes neighbors less than a Node in time |
duke@435 | 426 | // O(# of neighbors), but I have to visit all the Nodes greater than a |
duke@435 | 427 | // given Node and search them for an instance, i.e., time O(#MaxLRG)). |
duke@435 | 428 | _ifg->SquareUp(); |
duke@435 | 429 | |
neliasso@4949 | 430 | PhaseAggressiveCoalesce coalesce(*this); |
neliasso@4949 | 431 | coalesce.coalesce_driver(); |
duke@435 | 432 | // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do |
duke@435 | 433 | // not match the Phi itself, insert a copy. |
duke@435 | 434 | coalesce.insert_copies(_matcher); |
drchase@5285 | 435 | if (C->failing()) { |
drchase@5285 | 436 | return; |
drchase@5285 | 437 | } |
duke@435 | 438 | } |
duke@435 | 439 | |
duke@435 | 440 | // After aggressive coalesce, attempt a first cut at coloring. |
duke@435 | 441 | // To color, we need the IFG and for that we need LIVE. |
duke@435 | 442 | { |
duke@435 | 443 | NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) |
duke@435 | 444 | _live = NULL; |
duke@435 | 445 | rm.reset_to_mark(); // Reclaim working storage |
duke@435 | 446 | IndexSet::reset_memory(C, &live_arena); |
neliasso@4949 | 447 | ifg.init(_lrg_map.max_lrg_id()); |
duke@435 | 448 | gather_lrg_masks( true ); |
neliasso@4949 | 449 | live.compute(_lrg_map.max_lrg_id()); |
duke@435 | 450 | _live = &live; |
duke@435 | 451 | } |
duke@435 | 452 | |
duke@435 | 453 | // Build physical interference graph |
duke@435 | 454 | uint must_spill = 0; |
neliasso@4949 | 455 | must_spill = build_ifg_physical(&live_arena); |
duke@435 | 456 | // If we have a guaranteed spill, might as well spill now |
neliasso@4949 | 457 | if (must_spill) { |
neliasso@4949 | 458 | if(!_lrg_map.max_lrg_id()) { |
neliasso@4949 | 459 | return; |
neliasso@4949 | 460 | } |
duke@435 | 461 | // Bail out if unique gets too large (ie - unique > MaxNodeLimit) |
duke@435 | 462 | C->check_node_count(10*must_spill, "out of nodes before split"); |
neliasso@4949 | 463 | if (C->failing()) { |
neliasso@4949 | 464 | return; |
neliasso@4949 | 465 | } |
neliasso@4949 | 466 | |
neliasso@4949 | 467 | uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere |
neliasso@4949 | 468 | _lrg_map.set_max_lrg_id(new_max_lrg_id); |
duke@435 | 469 | // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
duke@435 | 470 | // or we failed to split |
duke@435 | 471 | C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); |
neliasso@4949 | 472 | if (C->failing()) { |
neliasso@4949 | 473 | return; |
neliasso@4949 | 474 | } |
duke@435 | 475 | |
neliasso@4949 | 476 | NOT_PRODUCT(C->verify_graph_edges();) |
duke@435 | 477 | |
duke@435 | 478 | compact(); // Compact LRGs; return new lower max lrg |
duke@435 | 479 | |
duke@435 | 480 | { |
duke@435 | 481 | NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) |
duke@435 | 482 | _live = NULL; |
duke@435 | 483 | rm.reset_to_mark(); // Reclaim working storage |
duke@435 | 484 | IndexSet::reset_memory(C, &live_arena); |
neliasso@4949 | 485 | ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph |
duke@435 | 486 | gather_lrg_masks( true ); // Collect intersect mask |
neliasso@4949 | 487 | live.compute(_lrg_map.max_lrg_id()); // Compute LIVE |
duke@435 | 488 | _live = &live; |
duke@435 | 489 | } |
neliasso@4949 | 490 | build_ifg_physical(&live_arena); |
duke@435 | 491 | _ifg->SquareUp(); |
duke@435 | 492 | _ifg->Compute_Effective_Degree(); |
duke@435 | 493 | // Only do conservative coalescing if requested |
neliasso@4949 | 494 | if (OptoCoalesce) { |
duke@435 | 495 | // Conservative (and pessimistic) copy coalescing of those spills |
neliasso@4949 | 496 | PhaseConservativeCoalesce coalesce(*this); |
duke@435 | 497 | // If max live ranges greater than cutoff, don't color the stack. |
duke@435 | 498 | // This cutoff can be larger than below since it is only done once. |
neliasso@4949 | 499 | coalesce.coalesce_driver(); |
duke@435 | 500 | } |
neliasso@4949 | 501 | _lrg_map.compress_uf_map_for_nodes(); |
duke@435 | 502 | |
duke@435 | 503 | #ifdef ASSERT |
kvn@1001 | 504 | verify(&live_arena, true); |
duke@435 | 505 | #endif |
duke@435 | 506 | } else { |
duke@435 | 507 | ifg.SquareUp(); |
duke@435 | 508 | ifg.Compute_Effective_Degree(); |
duke@435 | 509 | #ifdef ASSERT |
duke@435 | 510 | set_was_low(); |
duke@435 | 511 | #endif |
duke@435 | 512 | } |
duke@435 | 513 | |
duke@435 | 514 | // Prepare for Simplify & Select |
duke@435 | 515 | cache_lrg_info(); // Count degree of LRGs |
duke@435 | 516 | |
duke@435 | 517 | // Simplify the InterFerence Graph by removing LRGs of low degree. |
duke@435 | 518 | // LRGs of low degree are trivially colorable. |
duke@435 | 519 | Simplify(); |
duke@435 | 520 | |
duke@435 | 521 | // Select colors by re-inserting LRGs back into the IFG in reverse order. |
duke@435 | 522 | // Return whether or not something spills. |
duke@435 | 523 | uint spills = Select( ); |
duke@435 | 524 | |
duke@435 | 525 | // If we spill, split and recycle the entire thing |
duke@435 | 526 | while( spills ) { |
duke@435 | 527 | if( _trip_cnt++ > 24 ) { |
duke@435 | 528 | DEBUG_ONLY( dump_for_spill_split_recycle(); ) |
duke@435 | 529 | if( _trip_cnt > 27 ) { |
duke@435 | 530 | C->record_method_not_compilable("failed spill-split-recycle sanity check"); |
duke@435 | 531 | return; |
duke@435 | 532 | } |
duke@435 | 533 | } |
duke@435 | 534 | |
neliasso@4949 | 535 | if (!_lrg_map.max_lrg_id()) { |
neliasso@4949 | 536 | return; |
neliasso@4949 | 537 | } |
neliasso@4949 | 538 | uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere |
neliasso@4949 | 539 | _lrg_map.set_max_lrg_id(new_max_lrg_id); |
duke@435 | 540 | // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
neliasso@4949 | 541 | C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split"); |
neliasso@4949 | 542 | if (C->failing()) { |
neliasso@4949 | 543 | return; |
neliasso@4949 | 544 | } |
duke@435 | 545 | |
neliasso@4949 | 546 | compact(); // Compact LRGs; return new lower max lrg |
duke@435 | 547 | |
duke@435 | 548 | // Nuke the live-ness and interference graph and LiveRanGe info |
duke@435 | 549 | { |
duke@435 | 550 | NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) |
duke@435 | 551 | _live = NULL; |
duke@435 | 552 | rm.reset_to_mark(); // Reclaim working storage |
duke@435 | 553 | IndexSet::reset_memory(C, &live_arena); |
neliasso@4949 | 554 | ifg.init(_lrg_map.max_lrg_id()); |
duke@435 | 555 | |
duke@435 | 556 | // Create LiveRanGe array. |
duke@435 | 557 | // Intersect register masks for all USEs and DEFs |
neliasso@4949 | 558 | gather_lrg_masks(true); |
neliasso@4949 | 559 | live.compute(_lrg_map.max_lrg_id()); |
duke@435 | 560 | _live = &live; |
duke@435 | 561 | } |
neliasso@4949 | 562 | must_spill = build_ifg_physical(&live_arena); |
duke@435 | 563 | _ifg->SquareUp(); |
duke@435 | 564 | _ifg->Compute_Effective_Degree(); |
duke@435 | 565 | |
duke@435 | 566 | // Only do conservative coalescing if requested |
neliasso@4949 | 567 | if (OptoCoalesce) { |
duke@435 | 568 | // Conservative (and pessimistic) copy coalescing |
neliasso@4949 | 569 | PhaseConservativeCoalesce coalesce(*this); |
duke@435 | 570 | // Check for few live ranges determines how aggressive coalesce is. |
neliasso@4949 | 571 | coalesce.coalesce_driver(); |
duke@435 | 572 | } |
neliasso@4949 | 573 | _lrg_map.compress_uf_map_for_nodes(); |
duke@435 | 574 | #ifdef ASSERT |
kvn@1001 | 575 | verify(&live_arena, true); |
duke@435 | 576 | #endif |
duke@435 | 577 | cache_lrg_info(); // Count degree of LRGs |
duke@435 | 578 | |
duke@435 | 579 | // Simplify the InterFerence Graph by removing LRGs of low degree. |
duke@435 | 580 | // LRGs of low degree are trivially colorable. |
duke@435 | 581 | Simplify(); |
duke@435 | 582 | |
duke@435 | 583 | // Select colors by re-inserting LRGs back into the IFG in reverse order. |
duke@435 | 584 | // Return whether or not something spills. |
neliasso@4949 | 585 | spills = Select(); |
duke@435 | 586 | } |
duke@435 | 587 | |
duke@435 | 588 | // Count number of Simplify-Select trips per coloring success. |
duke@435 | 589 | _allocator_attempts += _trip_cnt + 1; |
duke@435 | 590 | _allocator_successes += 1; |
duke@435 | 591 | |
duke@435 | 592 | // Peephole remove copies |
duke@435 | 593 | post_allocate_copy_removal(); |
duke@435 | 594 | |
kvn@1001 | 595 | #ifdef ASSERT |
kvn@1001 | 596 | // Veify the graph after RA. |
kvn@1001 | 597 | verify(&live_arena); |
kvn@1001 | 598 | #endif |
kvn@1001 | 599 | |
duke@435 | 600 | // max_reg is past the largest *register* used. |
duke@435 | 601 | // Convert that to a frame_slot number. |
neliasso@4949 | 602 | if (_max_reg <= _matcher._new_SP) { |
duke@435 | 603 | _framesize = C->out_preserve_stack_slots(); |
neliasso@4949 | 604 | } |
neliasso@4949 | 605 | else { |
neliasso@4949 | 606 | _framesize = _max_reg -_matcher._new_SP; |
neliasso@4949 | 607 | } |
duke@435 | 608 | assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); |
duke@435 | 609 | |
duke@435 | 610 | // This frame must preserve the required fp alignment |
never@854 | 611 | _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); |
duke@435 | 612 | assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" ); |
duke@435 | 613 | #ifndef PRODUCT |
duke@435 | 614 | _total_framesize += _framesize; |
neliasso@4949 | 615 | if ((int)_framesize > _max_framesize) { |
duke@435 | 616 | _max_framesize = _framesize; |
neliasso@4949 | 617 | } |
duke@435 | 618 | #endif |
duke@435 | 619 | |
duke@435 | 620 | // Convert CISC spills |
duke@435 | 621 | fixup_spills(); |
duke@435 | 622 | |
duke@435 | 623 | // Log regalloc results |
duke@435 | 624 | CompileLog* log = Compile::current()->log(); |
duke@435 | 625 | if (log != NULL) { |
duke@435 | 626 | log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); |
duke@435 | 627 | } |
duke@435 | 628 | |
neliasso@4949 | 629 | if (C->failing()) { |
neliasso@4949 | 630 | return; |
neliasso@4949 | 631 | } |
duke@435 | 632 | |
neliasso@4949 | 633 | NOT_PRODUCT(C->verify_graph_edges();) |
duke@435 | 634 | |
duke@435 | 635 | // Move important info out of the live_arena to longer lasting storage. |
neliasso@4949 | 636 | alloc_node_regs(_lrg_map.size()); |
neliasso@4949 | 637 | for (uint i=0; i < _lrg_map.size(); i++) { |
neliasso@4949 | 638 | if (_lrg_map.live_range_id(i)) { // Live range associated with Node? |
neliasso@4949 | 639 | LRG &lrg = lrgs(_lrg_map.live_range_id(i)); |
kvn@3882 | 640 | if (!lrg.alive()) { |
kvn@4007 | 641 | set_bad(i); |
kvn@3882 | 642 | } else if (lrg.num_regs() == 1) { |
kvn@4007 | 643 | set1(i, lrg.reg()); |
kvn@4007 | 644 | } else { // Must be a register-set |
kvn@4007 | 645 | if (!lrg._fat_proj) { // Must be aligned adjacent register set |
duke@435 | 646 | // Live ranges record the highest register in their mask. |
duke@435 | 647 | // We want the low register for the AD file writer's convenience. |
kvn@4007 | 648 | OptoReg::Name hi = lrg.reg(); // Get hi register |
kvn@4007 | 649 | OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo |
kvn@4007 | 650 | // We have to use pair [lo,lo+1] even for wide vectors because |
kvn@4007 | 651 | // the rest of code generation works only with pairs. It is safe |
kvn@4007 | 652 | // since for registers encoding only 'lo' is used. |
kvn@4007 | 653 | // Second reg from pair is used in ScheduleAndBundle on SPARC where |
kvn@4007 | 654 | // vector max size is 8 which corresponds to registers pair. |
kvn@4007 | 655 | // It is also used in BuildOopMaps but oop operations are not |
kvn@4007 | 656 | // vectorized. |
kvn@4007 | 657 | set2(i, lo); |
duke@435 | 658 | } else { // Misaligned; extract 2 bits |
duke@435 | 659 | OptoReg::Name hi = lrg.reg(); // Get hi register |
duke@435 | 660 | lrg.Remove(hi); // Yank from mask |
duke@435 | 661 | int lo = lrg.mask().find_first_elem(); // Find lo |
kvn@4007 | 662 | set_pair(i, hi, lo); |
duke@435 | 663 | } |
duke@435 | 664 | } |
duke@435 | 665 | if( lrg._is_oop ) _node_oops.set(i); |
duke@435 | 666 | } else { |
kvn@4007 | 667 | set_bad(i); |
duke@435 | 668 | } |
duke@435 | 669 | } |
duke@435 | 670 | |
duke@435 | 671 | // Done! |
duke@435 | 672 | _live = NULL; |
duke@435 | 673 | _ifg = NULL; |
duke@435 | 674 | C->set_indexSet_arena(NULL); // ResourceArea is at end of scope |
duke@435 | 675 | } |
duke@435 | 676 | |
duke@435 | 677 | void PhaseChaitin::de_ssa() { |
duke@435 | 678 | // Set initial Names for all Nodes. Most Nodes get the virtual register |
duke@435 | 679 | // number. A few get the ZERO live range number. These do not |
duke@435 | 680 | // get allocated, but instead rely on correct scheduling to ensure that |
duke@435 | 681 | // only one instance is simultaneously live at a time. |
duke@435 | 682 | uint lr_counter = 1; |
adlertz@5539 | 683 | for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { |
adlertz@5539 | 684 | Block* block = _cfg.get_block(i); |
adlertz@5539 | 685 | uint cnt = block->_nodes.size(); |
duke@435 | 686 | |
duke@435 | 687 | // Handle all the normal Nodes in the block |
duke@435 | 688 | for( uint j = 0; j < cnt; j++ ) { |
adlertz@5539 | 689 | Node *n = block->_nodes[j]; |
duke@435 | 690 | // Pre-color to the zero live range, or pick virtual register |
duke@435 | 691 | const RegMask &rm = n->out_RegMask(); |
neliasso@4949 | 692 | _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); |
duke@435 | 693 | } |
duke@435 | 694 | } |
duke@435 | 695 | // Reset the Union-Find mapping to be identity |
neliasso@4949 | 696 | _lrg_map.reset_uf_map(lr_counter); |
duke@435 | 697 | } |
duke@435 | 698 | |
duke@435 | 699 | |
duke@435 | 700 | // Gather LiveRanGe information, including register masks. Modification of |
duke@435 | 701 | // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. |
duke@435 | 702 | void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { |
duke@435 | 703 | |
duke@435 | 704 | // Nail down the frame pointer live range |
adlertz@5539 | 705 | uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); |
duke@435 | 706 | lrgs(fp_lrg)._cost += 1e12; // Cost is infinite |
duke@435 | 707 | |
duke@435 | 708 | // For all blocks |
adlertz@5539 | 709 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 710 | Block* block = _cfg.get_block(i); |
duke@435 | 711 | |
duke@435 | 712 | // For all instructions |
adlertz@5539 | 713 | for (uint j = 1; j < block->_nodes.size(); j++) { |
adlertz@5539 | 714 | Node* n = block->_nodes[j]; |
duke@435 | 715 | uint input_edge_start =1; // Skip control most nodes |
adlertz@5539 | 716 | if (n->is_Mach()) { |
adlertz@5539 | 717 | input_edge_start = n->as_Mach()->oper_input_base(); |
adlertz@5539 | 718 | } |
duke@435 | 719 | uint idx = n->is_Copy(); |
duke@435 | 720 | |
duke@435 | 721 | // Get virtual register number, same as LiveRanGe index |
neliasso@4949 | 722 | uint vreg = _lrg_map.live_range_id(n); |
adlertz@5539 | 723 | LRG& lrg = lrgs(vreg); |
adlertz@5539 | 724 | if (vreg) { // No vreg means un-allocable (e.g. memory) |
duke@435 | 725 | |
duke@435 | 726 | // Collect has-copy bit |
adlertz@5539 | 727 | if (idx) { |
duke@435 | 728 | lrg._has_copy = 1; |
neliasso@4949 | 729 | uint clidx = _lrg_map.live_range_id(n->in(idx)); |
adlertz@5539 | 730 | LRG& copy_src = lrgs(clidx); |
duke@435 | 731 | copy_src._has_copy = 1; |
duke@435 | 732 | } |
duke@435 | 733 | |
duke@435 | 734 | // Check for float-vs-int live range (used in register-pressure |
duke@435 | 735 | // calculations) |
duke@435 | 736 | const Type *n_type = n->bottom_type(); |
adlertz@5539 | 737 | if (n_type->is_floatingpoint()) { |
duke@435 | 738 | lrg._is_float = 1; |
adlertz@5539 | 739 | } |
duke@435 | 740 | |
duke@435 | 741 | // Check for twice prior spilling. Once prior spilling might have |
duke@435 | 742 | // spilled 'soft', 2nd prior spill should have spilled 'hard' and |
duke@435 | 743 | // further spilling is unlikely to make progress. |
adlertz@5539 | 744 | if (_spilled_once.test(n->_idx)) { |
duke@435 | 745 | lrg._was_spilled1 = 1; |
adlertz@5539 | 746 | if (_spilled_twice.test(n->_idx)) { |
duke@435 | 747 | lrg._was_spilled2 = 1; |
adlertz@5539 | 748 | } |
duke@435 | 749 | } |
duke@435 | 750 | |
duke@435 | 751 | #ifndef PRODUCT |
duke@435 | 752 | if (trace_spilling() && lrg._def != NULL) { |
duke@435 | 753 | // collect defs for MultiDef printing |
duke@435 | 754 | if (lrg._defs == NULL) { |
kvn@2040 | 755 | lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL); |
duke@435 | 756 | lrg._defs->append(lrg._def); |
duke@435 | 757 | } |
duke@435 | 758 | lrg._defs->append(n); |
duke@435 | 759 | } |
duke@435 | 760 | #endif |
duke@435 | 761 | |
duke@435 | 762 | // Check for a single def LRG; these can spill nicely |
duke@435 | 763 | // via rematerialization. Flag as NULL for no def found |
duke@435 | 764 | // yet, or 'n' for single def or -1 for many defs. |
duke@435 | 765 | lrg._def = lrg._def ? NodeSentinel : n; |
duke@435 | 766 | |
duke@435 | 767 | // Limit result register mask to acceptable registers |
duke@435 | 768 | const RegMask &rm = n->out_RegMask(); |
duke@435 | 769 | lrg.AND( rm ); |
duke@435 | 770 | |
duke@435 | 771 | int ireg = n->ideal_reg(); |
duke@435 | 772 | assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, |
duke@435 | 773 | "oops must be in Op_RegP's" ); |
kvn@3882 | 774 | |
kvn@3882 | 775 | // Check for vector live range (only if vector register is used). |
kvn@3882 | 776 | // On SPARC vector uses RegD which could be misaligned so it is not |
kvn@3882 | 777 | // processes as vector in RA. |
kvn@3882 | 778 | if (RegMask::is_vector(ireg)) |
kvn@3882 | 779 | lrg._is_vector = 1; |
kvn@3882 | 780 | assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
kvn@3882 | 781 | "vector must be in vector registers"); |
kvn@3882 | 782 | |
kvn@3882 | 783 | // Check for bound register masks |
kvn@3882 | 784 | const RegMask &lrgmask = lrg.mask(); |
adlertz@5539 | 785 | if (lrgmask.is_bound(ireg)) { |
kvn@3882 | 786 | lrg._is_bound = 1; |
adlertz@5539 | 787 | } |
kvn@3882 | 788 | |
kvn@3882 | 789 | // Check for maximum frequency value |
adlertz@5539 | 790 | if (lrg._maxfreq < block->_freq) { |
adlertz@5539 | 791 | lrg._maxfreq = block->_freq; |
adlertz@5539 | 792 | } |
kvn@3882 | 793 | |
duke@435 | 794 | // Check for oop-iness, or long/double |
duke@435 | 795 | // Check for multi-kill projection |
adlertz@5539 | 796 | switch (ireg) { |
duke@435 | 797 | case MachProjNode::fat_proj: |
duke@435 | 798 | // Fat projections have size equal to number of registers killed |
duke@435 | 799 | lrg.set_num_regs(rm.Size()); |
duke@435 | 800 | lrg.set_reg_pressure(lrg.num_regs()); |
duke@435 | 801 | lrg._fat_proj = 1; |
duke@435 | 802 | lrg._is_bound = 1; |
duke@435 | 803 | break; |
duke@435 | 804 | case Op_RegP: |
duke@435 | 805 | #ifdef _LP64 |
duke@435 | 806 | lrg.set_num_regs(2); // Size is 2 stack words |
duke@435 | 807 | #else |
duke@435 | 808 | lrg.set_num_regs(1); // Size is 1 stack word |
duke@435 | 809 | #endif |
duke@435 | 810 | // Register pressure is tracked relative to the maximum values |
duke@435 | 811 | // suggested for that platform, INTPRESSURE and FLOATPRESSURE, |
duke@435 | 812 | // and relative to other types which compete for the same regs. |
duke@435 | 813 | // |
duke@435 | 814 | // The following table contains suggested values based on the |
duke@435 | 815 | // architectures as defined in each .ad file. |
duke@435 | 816 | // INTPRESSURE and FLOATPRESSURE may be tuned differently for |
duke@435 | 817 | // compile-speed or performance. |
duke@435 | 818 | // Note1: |
duke@435 | 819 | // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 |
duke@435 | 820 | // since .ad registers are defined as high and low halves. |
duke@435 | 821 | // These reg_pressure values remain compatible with the code |
duke@435 | 822 | // in is_high_pressure() which relates get_invalid_mask_size(), |
duke@435 | 823 | // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. |
duke@435 | 824 | // Note2: |
duke@435 | 825 | // SPARC -d32 has 24 registers available for integral values, |
duke@435 | 826 | // but only 10 of these are safe for 64-bit longs. |
duke@435 | 827 | // Using set_reg_pressure(2) for both int and long means |
duke@435 | 828 | // the allocator will believe it can fit 26 longs into |
duke@435 | 829 | // registers. Using 2 for longs and 1 for ints means the |
duke@435 | 830 | // allocator will attempt to put 52 integers into registers. |
duke@435 | 831 | // The settings below limit this problem to methods with |
duke@435 | 832 | // many long values which are being run on 32-bit SPARC. |
duke@435 | 833 | // |
duke@435 | 834 | // ------------------- reg_pressure -------------------- |
duke@435 | 835 | // Each entry is reg_pressure_per_value,number_of_regs |
duke@435 | 836 | // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE |
duke@435 | 837 | // IA32 2 1 1 1 1 6 6 |
duke@435 | 838 | // IA64 1 1 1 1 1 50 41 |
duke@435 | 839 | // SPARC 2 2 2 2 2 48 (24) 52 (26) |
duke@435 | 840 | // SPARCV9 2 2 2 2 2 48 (24) 52 (26) |
duke@435 | 841 | // AMD64 1 1 1 1 1 14 15 |
duke@435 | 842 | // ----------------------------------------------------- |
duke@435 | 843 | #if defined(SPARC) |
duke@435 | 844 | lrg.set_reg_pressure(2); // use for v9 as well |
duke@435 | 845 | #else |
duke@435 | 846 | lrg.set_reg_pressure(1); // normally one value per register |
duke@435 | 847 | #endif |
duke@435 | 848 | if( n_type->isa_oop_ptr() ) { |
duke@435 | 849 | lrg._is_oop = 1; |
duke@435 | 850 | } |
duke@435 | 851 | break; |
duke@435 | 852 | case Op_RegL: // Check for long or double |
duke@435 | 853 | case Op_RegD: |
duke@435 | 854 | lrg.set_num_regs(2); |
duke@435 | 855 | // Define platform specific register pressure |
roland@2683 | 856 | #if defined(SPARC) || defined(ARM) |
duke@435 | 857 | lrg.set_reg_pressure(2); |
duke@435 | 858 | #elif defined(IA32) |
duke@435 | 859 | if( ireg == Op_RegL ) { |
duke@435 | 860 | lrg.set_reg_pressure(2); |
duke@435 | 861 | } else { |
duke@435 | 862 | lrg.set_reg_pressure(1); |
duke@435 | 863 | } |
duke@435 | 864 | #else |
duke@435 | 865 | lrg.set_reg_pressure(1); // normally one value per register |
duke@435 | 866 | #endif |
duke@435 | 867 | // If this def of a double forces a mis-aligned double, |
duke@435 | 868 | // flag as '_fat_proj' - really flag as allowing misalignment |
duke@435 | 869 | // AND changes how we count interferences. A mis-aligned |
duke@435 | 870 | // double can interfere with TWO aligned pairs, or effectively |
duke@435 | 871 | // FOUR registers! |
kvn@3882 | 872 | if (rm.is_misaligned_pair()) { |
duke@435 | 873 | lrg._fat_proj = 1; |
duke@435 | 874 | lrg._is_bound = 1; |
duke@435 | 875 | } |
duke@435 | 876 | break; |
duke@435 | 877 | case Op_RegF: |
duke@435 | 878 | case Op_RegI: |
coleenp@548 | 879 | case Op_RegN: |
duke@435 | 880 | case Op_RegFlags: |
duke@435 | 881 | case 0: // not an ideal register |
duke@435 | 882 | lrg.set_num_regs(1); |
duke@435 | 883 | #ifdef SPARC |
duke@435 | 884 | lrg.set_reg_pressure(2); |
duke@435 | 885 | #else |
duke@435 | 886 | lrg.set_reg_pressure(1); |
duke@435 | 887 | #endif |
duke@435 | 888 | break; |
kvn@3882 | 889 | case Op_VecS: |
kvn@3882 | 890 | assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); |
kvn@3882 | 891 | assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); |
kvn@3882 | 892 | lrg.set_num_regs(RegMask::SlotsPerVecS); |
kvn@3882 | 893 | lrg.set_reg_pressure(1); |
kvn@3882 | 894 | break; |
kvn@3882 | 895 | case Op_VecD: |
kvn@3882 | 896 | assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); |
kvn@3882 | 897 | assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); |
kvn@3882 | 898 | assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); |
kvn@3882 | 899 | lrg.set_num_regs(RegMask::SlotsPerVecD); |
kvn@3882 | 900 | lrg.set_reg_pressure(1); |
kvn@3882 | 901 | break; |
kvn@3882 | 902 | case Op_VecX: |
kvn@3882 | 903 | assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); |
kvn@3882 | 904 | assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); |
kvn@3882 | 905 | assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); |
kvn@3882 | 906 | lrg.set_num_regs(RegMask::SlotsPerVecX); |
kvn@3882 | 907 | lrg.set_reg_pressure(1); |
kvn@3882 | 908 | break; |
kvn@3882 | 909 | case Op_VecY: |
kvn@3882 | 910 | assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); |
kvn@3882 | 911 | assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); |
kvn@3882 | 912 | assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); |
kvn@3882 | 913 | lrg.set_num_regs(RegMask::SlotsPerVecY); |
kvn@3882 | 914 | lrg.set_reg_pressure(1); |
kvn@3882 | 915 | break; |
duke@435 | 916 | default: |
duke@435 | 917 | ShouldNotReachHere(); |
duke@435 | 918 | } |
duke@435 | 919 | } |
duke@435 | 920 | |
duke@435 | 921 | // Now do the same for inputs |
duke@435 | 922 | uint cnt = n->req(); |
duke@435 | 923 | // Setup for CISC SPILLING |
duke@435 | 924 | uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; |
duke@435 | 925 | if( UseCISCSpill && after_aggressive ) { |
duke@435 | 926 | inp = n->cisc_operand(); |
duke@435 | 927 | if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) |
duke@435 | 928 | // Convert operand number to edge index number |
duke@435 | 929 | inp = n->as_Mach()->operand_index(inp); |
duke@435 | 930 | } |
duke@435 | 931 | // Prepare register mask for each input |
duke@435 | 932 | for( uint k = input_edge_start; k < cnt; k++ ) { |
neliasso@4949 | 933 | uint vreg = _lrg_map.live_range_id(n->in(k)); |
neliasso@4949 | 934 | if (!vreg) { |
neliasso@4949 | 935 | continue; |
neliasso@4949 | 936 | } |
duke@435 | 937 | |
duke@435 | 938 | // If this instruction is CISC Spillable, add the flags |
duke@435 | 939 | // bit to its appropriate input |
duke@435 | 940 | if( UseCISCSpill && after_aggressive && inp == k ) { |
duke@435 | 941 | #ifndef PRODUCT |
duke@435 | 942 | if( TraceCISCSpill ) { |
duke@435 | 943 | tty->print(" use_cisc_RegMask: "); |
duke@435 | 944 | n->dump(); |
duke@435 | 945 | } |
duke@435 | 946 | #endif |
duke@435 | 947 | n->as_Mach()->use_cisc_RegMask(); |
duke@435 | 948 | } |
duke@435 | 949 | |
duke@435 | 950 | LRG &lrg = lrgs(vreg); |
duke@435 | 951 | // // Testing for floating point code shape |
duke@435 | 952 | // Node *test = n->in(k); |
duke@435 | 953 | // if( test->is_Mach() ) { |
duke@435 | 954 | // MachNode *m = test->as_Mach(); |
duke@435 | 955 | // int op = m->ideal_Opcode(); |
duke@435 | 956 | // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { |
duke@435 | 957 | // int zzz = 1; |
duke@435 | 958 | // } |
duke@435 | 959 | // } |
duke@435 | 960 | |
duke@435 | 961 | // Limit result register mask to acceptable registers. |
duke@435 | 962 | // Do not limit registers from uncommon uses before |
duke@435 | 963 | // AggressiveCoalesce. This effectively pre-virtual-splits |
duke@435 | 964 | // around uncommon uses of common defs. |
duke@435 | 965 | const RegMask &rm = n->in_RegMask(k); |
adlertz@5539 | 966 | if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { |
duke@435 | 967 | // Since we are BEFORE aggressive coalesce, leave the register |
duke@435 | 968 | // mask untrimmed by the call. This encourages more coalescing. |
duke@435 | 969 | // Later, AFTER aggressive, this live range will have to spill |
duke@435 | 970 | // but the spiller handles slow-path calls very nicely. |
duke@435 | 971 | } else { |
duke@435 | 972 | lrg.AND( rm ); |
duke@435 | 973 | } |
kvn@3882 | 974 | |
duke@435 | 975 | // Check for bound register masks |
duke@435 | 976 | const RegMask &lrgmask = lrg.mask(); |
kvn@3882 | 977 | int kreg = n->in(k)->ideal_reg(); |
kvn@3882 | 978 | bool is_vect = RegMask::is_vector(kreg); |
kvn@3882 | 979 | assert(n->in(k)->bottom_type()->isa_vect() == NULL || |
kvn@3882 | 980 | is_vect || kreg == Op_RegD, |
kvn@3882 | 981 | "vector must be in vector registers"); |
kvn@3882 | 982 | if (lrgmask.is_bound(kreg)) |
duke@435 | 983 | lrg._is_bound = 1; |
kvn@3882 | 984 | |
duke@435 | 985 | // If this use of a double forces a mis-aligned double, |
duke@435 | 986 | // flag as '_fat_proj' - really flag as allowing misalignment |
duke@435 | 987 | // AND changes how we count interferences. A mis-aligned |
duke@435 | 988 | // double can interfere with TWO aligned pairs, or effectively |
duke@435 | 989 | // FOUR registers! |
kvn@3882 | 990 | #ifdef ASSERT |
kvn@3882 | 991 | if (is_vect) { |
kvn@3882 | 992 | assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); |
kvn@3882 | 993 | assert(!lrg._fat_proj, "sanity"); |
kvn@3882 | 994 | assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); |
kvn@3882 | 995 | } |
kvn@3882 | 996 | #endif |
kvn@3882 | 997 | if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { |
duke@435 | 998 | lrg._fat_proj = 1; |
duke@435 | 999 | lrg._is_bound = 1; |
duke@435 | 1000 | } |
duke@435 | 1001 | // if the LRG is an unaligned pair, we will have to spill |
duke@435 | 1002 | // so clear the LRG's register mask if it is not already spilled |
kvn@3882 | 1003 | if (!is_vect && !n->is_SpillCopy() && |
kvn@3882 | 1004 | (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
kvn@3882 | 1005 | lrgmask.is_misaligned_pair()) { |
duke@435 | 1006 | lrg.Clear(); |
duke@435 | 1007 | } |
duke@435 | 1008 | |
duke@435 | 1009 | // Check for maximum frequency value |
adlertz@5539 | 1010 | if (lrg._maxfreq < block->_freq) { |
adlertz@5539 | 1011 | lrg._maxfreq = block->_freq; |
adlertz@5539 | 1012 | } |
duke@435 | 1013 | |
duke@435 | 1014 | } // End for all allocated inputs |
duke@435 | 1015 | } // end for all instructions |
duke@435 | 1016 | } // end for all blocks |
duke@435 | 1017 | |
duke@435 | 1018 | // Final per-liverange setup |
neliasso@4949 | 1019 | for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) { |
duke@435 | 1020 | LRG &lrg = lrgs(i2); |
kvn@3882 | 1021 | assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); |
kvn@3882 | 1022 | if (lrg.num_regs() > 1 && !lrg._fat_proj) { |
kvn@3882 | 1023 | lrg.clear_to_sets(); |
kvn@3882 | 1024 | } |
duke@435 | 1025 | lrg.compute_set_mask_size(); |
kvn@3882 | 1026 | if (lrg.not_free()) { // Handle case where we lose from the start |
duke@435 | 1027 | lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
duke@435 | 1028 | lrg._direct_conflict = 1; |
duke@435 | 1029 | } |
duke@435 | 1030 | lrg.set_degree(0); // no neighbors in IFG yet |
duke@435 | 1031 | } |
duke@435 | 1032 | } |
duke@435 | 1033 | |
duke@435 | 1034 | // Set the was-lo-degree bit. Conservative coalescing should not change the |
duke@435 | 1035 | // colorability of the graph. If any live range was of low-degree before |
duke@435 | 1036 | // coalescing, it should Simplify. This call sets the was-lo-degree bit. |
duke@435 | 1037 | // The bit is checked in Simplify. |
duke@435 | 1038 | void PhaseChaitin::set_was_low() { |
duke@435 | 1039 | #ifdef ASSERT |
neliasso@4949 | 1040 | for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
duke@435 | 1041 | int size = lrgs(i).num_regs(); |
duke@435 | 1042 | uint old_was_lo = lrgs(i)._was_lo; |
duke@435 | 1043 | lrgs(i)._was_lo = 0; |
duke@435 | 1044 | if( lrgs(i).lo_degree() ) { |
duke@435 | 1045 | lrgs(i)._was_lo = 1; // Trivially of low degree |
duke@435 | 1046 | } else { // Else check the Brigg's assertion |
duke@435 | 1047 | // Brigg's observation is that the lo-degree neighbors of a |
duke@435 | 1048 | // hi-degree live range will not interfere with the color choices |
duke@435 | 1049 | // of said hi-degree live range. The Simplify reverse-stack-coloring |
duke@435 | 1050 | // order takes care of the details. Hence you do not have to count |
duke@435 | 1051 | // low-degree neighbors when determining if this guy colors. |
duke@435 | 1052 | int briggs_degree = 0; |
duke@435 | 1053 | IndexSet *s = _ifg->neighbors(i); |
duke@435 | 1054 | IndexSetIterator elements(s); |
duke@435 | 1055 | uint lidx; |
duke@435 | 1056 | while((lidx = elements.next()) != 0) { |
duke@435 | 1057 | if( !lrgs(lidx).lo_degree() ) |
duke@435 | 1058 | briggs_degree += MAX2(size,lrgs(lidx).num_regs()); |
duke@435 | 1059 | } |
duke@435 | 1060 | if( briggs_degree < lrgs(i).degrees_of_freedom() ) |
duke@435 | 1061 | lrgs(i)._was_lo = 1; // Low degree via the briggs assertion |
duke@435 | 1062 | } |
duke@435 | 1063 | assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); |
duke@435 | 1064 | } |
duke@435 | 1065 | #endif |
duke@435 | 1066 | } |
duke@435 | 1067 | |
duke@435 | 1068 | #define REGISTER_CONSTRAINED 16 |
duke@435 | 1069 | |
duke@435 | 1070 | // Compute cost/area ratio, in case we spill. Build the lo-degree list. |
duke@435 | 1071 | void PhaseChaitin::cache_lrg_info( ) { |
duke@435 | 1072 | |
neliasso@4949 | 1073 | for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
duke@435 | 1074 | LRG &lrg = lrgs(i); |
duke@435 | 1075 | |
duke@435 | 1076 | // Check for being of low degree: means we can be trivially colored. |
duke@435 | 1077 | // Low degree, dead or must-spill guys just get to simplify right away |
duke@435 | 1078 | if( lrg.lo_degree() || |
duke@435 | 1079 | !lrg.alive() || |
duke@435 | 1080 | lrg._must_spill ) { |
duke@435 | 1081 | // Split low degree list into those guys that must get a |
duke@435 | 1082 | // register and those that can go to register or stack. |
duke@435 | 1083 | // The idea is LRGs that can go register or stack color first when |
duke@435 | 1084 | // they have a good chance of getting a register. The register-only |
duke@435 | 1085 | // lo-degree live ranges always get a register. |
duke@435 | 1086 | OptoReg::Name hi_reg = lrg.mask().find_last_elem(); |
duke@435 | 1087 | if( OptoReg::is_stack(hi_reg)) { // Can go to stack? |
duke@435 | 1088 | lrg._next = _lo_stk_degree; |
duke@435 | 1089 | _lo_stk_degree = i; |
duke@435 | 1090 | } else { |
duke@435 | 1091 | lrg._next = _lo_degree; |
duke@435 | 1092 | _lo_degree = i; |
duke@435 | 1093 | } |
duke@435 | 1094 | } else { // Else high degree |
duke@435 | 1095 | lrgs(_hi_degree)._prev = i; |
duke@435 | 1096 | lrg._next = _hi_degree; |
duke@435 | 1097 | lrg._prev = 0; |
duke@435 | 1098 | _hi_degree = i; |
duke@435 | 1099 | } |
duke@435 | 1100 | } |
duke@435 | 1101 | } |
duke@435 | 1102 | |
duke@435 | 1103 | // Simplify the IFG by removing LRGs of low degree that have NO copies |
duke@435 | 1104 | void PhaseChaitin::Pre_Simplify( ) { |
duke@435 | 1105 | |
duke@435 | 1106 | // Warm up the lo-degree no-copy list |
duke@435 | 1107 | int lo_no_copy = 0; |
neliasso@4949 | 1108 | for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
neliasso@4949 | 1109 | if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) || |
duke@435 | 1110 | !lrgs(i).alive() || |
neliasso@4949 | 1111 | lrgs(i)._must_spill) { |
duke@435 | 1112 | lrgs(i)._next = lo_no_copy; |
duke@435 | 1113 | lo_no_copy = i; |
duke@435 | 1114 | } |
duke@435 | 1115 | } |
duke@435 | 1116 | |
duke@435 | 1117 | while( lo_no_copy ) { |
duke@435 | 1118 | uint lo = lo_no_copy; |
duke@435 | 1119 | lo_no_copy = lrgs(lo)._next; |
duke@435 | 1120 | int size = lrgs(lo).num_regs(); |
duke@435 | 1121 | |
duke@435 | 1122 | // Put the simplified guy on the simplified list. |
duke@435 | 1123 | lrgs(lo)._next = _simplified; |
duke@435 | 1124 | _simplified = lo; |
duke@435 | 1125 | |
duke@435 | 1126 | // Yank this guy from the IFG. |
duke@435 | 1127 | IndexSet *adj = _ifg->remove_node( lo ); |
duke@435 | 1128 | |
duke@435 | 1129 | // If any neighbors' degrees fall below their number of |
duke@435 | 1130 | // allowed registers, then put that neighbor on the low degree |
duke@435 | 1131 | // list. Note that 'degree' can only fall and 'numregs' is |
duke@435 | 1132 | // unchanged by this action. Thus the two are equal at most once, |
duke@435 | 1133 | // so LRGs hit the lo-degree worklists at most once. |
duke@435 | 1134 | IndexSetIterator elements(adj); |
duke@435 | 1135 | uint neighbor; |
duke@435 | 1136 | while ((neighbor = elements.next()) != 0) { |
duke@435 | 1137 | LRG *n = &lrgs(neighbor); |
duke@435 | 1138 | assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); |
duke@435 | 1139 | |
duke@435 | 1140 | // Check for just becoming of-low-degree |
duke@435 | 1141 | if( n->just_lo_degree() && !n->_has_copy ) { |
duke@435 | 1142 | assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); |
duke@435 | 1143 | // Put on lo-degree list |
duke@435 | 1144 | n->_next = lo_no_copy; |
duke@435 | 1145 | lo_no_copy = neighbor; |
duke@435 | 1146 | } |
duke@435 | 1147 | } |
duke@435 | 1148 | } // End of while lo-degree no_copy worklist not empty |
duke@435 | 1149 | |
duke@435 | 1150 | // No more lo-degree no-copy live ranges to simplify |
duke@435 | 1151 | } |
duke@435 | 1152 | |
duke@435 | 1153 | // Simplify the IFG by removing LRGs of low degree. |
duke@435 | 1154 | void PhaseChaitin::Simplify( ) { |
duke@435 | 1155 | |
duke@435 | 1156 | while( 1 ) { // Repeat till simplified it all |
duke@435 | 1157 | // May want to explore simplifying lo_degree before _lo_stk_degree. |
duke@435 | 1158 | // This might result in more spills coloring into registers during |
duke@435 | 1159 | // Select(). |
duke@435 | 1160 | while( _lo_degree || _lo_stk_degree ) { |
duke@435 | 1161 | // If possible, pull from lo_stk first |
duke@435 | 1162 | uint lo; |
duke@435 | 1163 | if( _lo_degree ) { |
duke@435 | 1164 | lo = _lo_degree; |
duke@435 | 1165 | _lo_degree = lrgs(lo)._next; |
duke@435 | 1166 | } else { |
duke@435 | 1167 | lo = _lo_stk_degree; |
duke@435 | 1168 | _lo_stk_degree = lrgs(lo)._next; |
duke@435 | 1169 | } |
duke@435 | 1170 | |
duke@435 | 1171 | // Put the simplified guy on the simplified list. |
duke@435 | 1172 | lrgs(lo)._next = _simplified; |
duke@435 | 1173 | _simplified = lo; |
duke@435 | 1174 | // If this guy is "at risk" then mark his current neighbors |
duke@435 | 1175 | if( lrgs(lo)._at_risk ) { |
duke@435 | 1176 | IndexSetIterator elements(_ifg->neighbors(lo)); |
duke@435 | 1177 | uint datum; |
duke@435 | 1178 | while ((datum = elements.next()) != 0) { |
duke@435 | 1179 | lrgs(datum)._risk_bias = lo; |
duke@435 | 1180 | } |
duke@435 | 1181 | } |
duke@435 | 1182 | |
duke@435 | 1183 | // Yank this guy from the IFG. |
duke@435 | 1184 | IndexSet *adj = _ifg->remove_node( lo ); |
duke@435 | 1185 | |
duke@435 | 1186 | // If any neighbors' degrees fall below their number of |
duke@435 | 1187 | // allowed registers, then put that neighbor on the low degree |
duke@435 | 1188 | // list. Note that 'degree' can only fall and 'numregs' is |
duke@435 | 1189 | // unchanged by this action. Thus the two are equal at most once, |
duke@435 | 1190 | // so LRGs hit the lo-degree worklist at most once. |
duke@435 | 1191 | IndexSetIterator elements(adj); |
duke@435 | 1192 | uint neighbor; |
duke@435 | 1193 | while ((neighbor = elements.next()) != 0) { |
duke@435 | 1194 | LRG *n = &lrgs(neighbor); |
duke@435 | 1195 | #ifdef ASSERT |
kvn@985 | 1196 | if( VerifyOpto || VerifyRegisterAllocator ) { |
duke@435 | 1197 | assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); |
duke@435 | 1198 | } |
duke@435 | 1199 | #endif |
duke@435 | 1200 | |
duke@435 | 1201 | // Check for just becoming of-low-degree just counting registers. |
duke@435 | 1202 | // _must_spill live ranges are already on the low degree list. |
duke@435 | 1203 | if( n->just_lo_degree() && !n->_must_spill ) { |
duke@435 | 1204 | assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); |
duke@435 | 1205 | // Pull from hi-degree list |
duke@435 | 1206 | uint prev = n->_prev; |
duke@435 | 1207 | uint next = n->_next; |
duke@435 | 1208 | if( prev ) lrgs(prev)._next = next; |
duke@435 | 1209 | else _hi_degree = next; |
duke@435 | 1210 | lrgs(next)._prev = prev; |
duke@435 | 1211 | n->_next = _lo_degree; |
duke@435 | 1212 | _lo_degree = neighbor; |
duke@435 | 1213 | } |
duke@435 | 1214 | } |
duke@435 | 1215 | } // End of while lo-degree/lo_stk_degree worklist not empty |
duke@435 | 1216 | |
duke@435 | 1217 | // Check for got everything: is hi-degree list empty? |
duke@435 | 1218 | if( !_hi_degree ) break; |
duke@435 | 1219 | |
duke@435 | 1220 | // Time to pick a potential spill guy |
duke@435 | 1221 | uint lo_score = _hi_degree; |
duke@435 | 1222 | double score = lrgs(lo_score).score(); |
duke@435 | 1223 | double area = lrgs(lo_score)._area; |
kvn@1443 | 1224 | double cost = lrgs(lo_score)._cost; |
kvn@1443 | 1225 | bool bound = lrgs(lo_score)._is_bound; |
duke@435 | 1226 | |
duke@435 | 1227 | // Find cheapest guy |
duke@435 | 1228 | debug_only( int lo_no_simplify=0; ); |
kvn@1447 | 1229 | for( uint i = _hi_degree; i; i = lrgs(i)._next ) { |
duke@435 | 1230 | assert( !(*_ifg->_yanked)[i], "" ); |
duke@435 | 1231 | // It's just vaguely possible to move hi-degree to lo-degree without |
duke@435 | 1232 | // going through a just-lo-degree stage: If you remove a double from |
duke@435 | 1233 | // a float live range it's degree will drop by 2 and you can skip the |
duke@435 | 1234 | // just-lo-degree stage. It's very rare (shows up after 5000+ methods |
duke@435 | 1235 | // in -Xcomp of Java2Demo). So just choose this guy to simplify next. |
duke@435 | 1236 | if( lrgs(i).lo_degree() ) { |
duke@435 | 1237 | lo_score = i; |
duke@435 | 1238 | break; |
duke@435 | 1239 | } |
duke@435 | 1240 | debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); |
duke@435 | 1241 | double iscore = lrgs(i).score(); |
duke@435 | 1242 | double iarea = lrgs(i)._area; |
kvn@1443 | 1243 | double icost = lrgs(i)._cost; |
kvn@1443 | 1244 | bool ibound = lrgs(i)._is_bound; |
duke@435 | 1245 | |
duke@435 | 1246 | // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area |
duke@435 | 1247 | // wins. Ties happen because all live ranges in question have spilled |
duke@435 | 1248 | // a few times before and the spill-score adds a huge number which |
duke@435 | 1249 | // washes out the low order bits. We are choosing the lesser of 2 |
duke@435 | 1250 | // evils; in this case pick largest area to spill. |
kvn@1443 | 1251 | // Ties also happen when live ranges are defined and used only inside |
kvn@1443 | 1252 | // one block. In which case their area is 0 and score set to max. |
kvn@1443 | 1253 | // In such case choose bound live range over unbound to free registers |
kvn@1443 | 1254 | // or with smaller cost to spill. |
duke@435 | 1255 | if( iscore < score || |
kvn@1443 | 1256 | (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) || |
kvn@1443 | 1257 | (iscore == score && iarea == area && |
kvn@1443 | 1258 | ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) { |
duke@435 | 1259 | lo_score = i; |
duke@435 | 1260 | score = iscore; |
duke@435 | 1261 | area = iarea; |
kvn@1443 | 1262 | cost = icost; |
kvn@1443 | 1263 | bound = ibound; |
duke@435 | 1264 | } |
duke@435 | 1265 | } |
duke@435 | 1266 | LRG *lo_lrg = &lrgs(lo_score); |
duke@435 | 1267 | // The live range we choose for spilling is either hi-degree, or very |
duke@435 | 1268 | // rarely it can be low-degree. If we choose a hi-degree live range |
duke@435 | 1269 | // there better not be any lo-degree choices. |
duke@435 | 1270 | assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); |
duke@435 | 1271 | |
duke@435 | 1272 | // Pull from hi-degree list |
duke@435 | 1273 | uint prev = lo_lrg->_prev; |
duke@435 | 1274 | uint next = lo_lrg->_next; |
duke@435 | 1275 | if( prev ) lrgs(prev)._next = next; |
duke@435 | 1276 | else _hi_degree = next; |
duke@435 | 1277 | lrgs(next)._prev = prev; |
duke@435 | 1278 | // Jam him on the lo-degree list, despite his high degree. |
duke@435 | 1279 | // Maybe he'll get a color, and maybe he'll spill. |
duke@435 | 1280 | // Only Select() will know. |
duke@435 | 1281 | lrgs(lo_score)._at_risk = true; |
duke@435 | 1282 | _lo_degree = lo_score; |
duke@435 | 1283 | lo_lrg->_next = 0; |
duke@435 | 1284 | |
duke@435 | 1285 | } // End of while not simplified everything |
duke@435 | 1286 | |
duke@435 | 1287 | } |
duke@435 | 1288 | |
kvn@4007 | 1289 | // Is 'reg' register legal for 'lrg'? |
kvn@4007 | 1290 | static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { |
kvn@4007 | 1291 | if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && |
kvn@4007 | 1292 | lrg.mask().Member(OptoReg::add(reg,-chunk))) { |
kvn@4007 | 1293 | // RA uses OptoReg which represent the highest element of a registers set. |
kvn@4007 | 1294 | // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set |
kvn@4007 | 1295 | // in which XMMd is used by RA to represent such vectors. A double value |
kvn@4007 | 1296 | // uses [XMM,XMMb] pairs and XMMb is used by RA for it. |
kvn@4007 | 1297 | // The register mask uses largest bits set of overlapping register sets. |
kvn@4007 | 1298 | // On x86 with AVX it uses 8 bits for each XMM registers set. |
kvn@4007 | 1299 | // |
kvn@4007 | 1300 | // The 'lrg' already has cleared-to-set register mask (done in Select() |
kvn@4007 | 1301 | // before calling choose_color()). Passing mask.Member(reg) check above |
kvn@4007 | 1302 | // indicates that the size (num_regs) of 'reg' set is less or equal to |
kvn@4007 | 1303 | // 'lrg' set size. |
kvn@4007 | 1304 | // For set size 1 any register which is member of 'lrg' mask is legal. |
kvn@4007 | 1305 | if (lrg.num_regs()==1) |
kvn@4007 | 1306 | return true; |
kvn@4007 | 1307 | // For larger sets only an aligned register with the same set size is legal. |
kvn@4007 | 1308 | int mask = lrg.num_regs()-1; |
kvn@4007 | 1309 | if ((reg&mask) == mask) |
kvn@4007 | 1310 | return true; |
kvn@4007 | 1311 | } |
kvn@4007 | 1312 | return false; |
kvn@4007 | 1313 | } |
kvn@4007 | 1314 | |
duke@435 | 1315 | // Choose a color using the biasing heuristic |
duke@435 | 1316 | OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { |
duke@435 | 1317 | |
duke@435 | 1318 | // Check for "at_risk" LRG's |
neliasso@4949 | 1319 | uint risk_lrg = _lrg_map.find(lrg._risk_bias); |
duke@435 | 1320 | if( risk_lrg != 0 ) { |
duke@435 | 1321 | // Walk the colored neighbors of the "at_risk" candidate |
duke@435 | 1322 | // Choose a color which is both legal and already taken by a neighbor |
duke@435 | 1323 | // of the "at_risk" candidate in order to improve the chances of the |
duke@435 | 1324 | // "at_risk" candidate of coloring |
duke@435 | 1325 | IndexSetIterator elements(_ifg->neighbors(risk_lrg)); |
duke@435 | 1326 | uint datum; |
duke@435 | 1327 | while ((datum = elements.next()) != 0) { |
duke@435 | 1328 | OptoReg::Name reg = lrgs(datum).reg(); |
duke@435 | 1329 | // If this LRG's register is legal for us, choose it |
kvn@4007 | 1330 | if (is_legal_reg(lrg, reg, chunk)) |
duke@435 | 1331 | return reg; |
duke@435 | 1332 | } |
duke@435 | 1333 | } |
duke@435 | 1334 | |
neliasso@4949 | 1335 | uint copy_lrg = _lrg_map.find(lrg._copy_bias); |
duke@435 | 1336 | if( copy_lrg != 0 ) { |
duke@435 | 1337 | // If he has a color, |
duke@435 | 1338 | if( !(*(_ifg->_yanked))[copy_lrg] ) { |
duke@435 | 1339 | OptoReg::Name reg = lrgs(copy_lrg).reg(); |
duke@435 | 1340 | // And it is legal for you, |
kvn@4007 | 1341 | if (is_legal_reg(lrg, reg, chunk)) |
duke@435 | 1342 | return reg; |
duke@435 | 1343 | } else if( chunk == 0 ) { |
duke@435 | 1344 | // Choose a color which is legal for him |
duke@435 | 1345 | RegMask tempmask = lrg.mask(); |
duke@435 | 1346 | tempmask.AND(lrgs(copy_lrg).mask()); |
kvn@3882 | 1347 | tempmask.clear_to_sets(lrg.num_regs()); |
kvn@3882 | 1348 | OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); |
kvn@3882 | 1349 | if (OptoReg::is_valid(reg)) |
duke@435 | 1350 | return reg; |
duke@435 | 1351 | } |
duke@435 | 1352 | } |
duke@435 | 1353 | |
duke@435 | 1354 | // If no bias info exists, just go with the register selection ordering |
kvn@3882 | 1355 | if (lrg._is_vector || lrg.num_regs() == 2) { |
kvn@3882 | 1356 | // Find an aligned set |
kvn@3882 | 1357 | return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); |
duke@435 | 1358 | } |
duke@435 | 1359 | |
duke@435 | 1360 | // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate |
duke@435 | 1361 | // copy removal to remove many more copies, by preventing a just-assigned |
duke@435 | 1362 | // register from being repeatedly assigned. |
duke@435 | 1363 | OptoReg::Name reg = lrg.mask().find_first_elem(); |
duke@435 | 1364 | if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { |
duke@435 | 1365 | // This 'Remove; find; Insert' idiom is an expensive way to find the |
duke@435 | 1366 | // SECOND element in the mask. |
duke@435 | 1367 | lrg.Remove(reg); |
duke@435 | 1368 | OptoReg::Name reg2 = lrg.mask().find_first_elem(); |
duke@435 | 1369 | lrg.Insert(reg); |
duke@435 | 1370 | if( OptoReg::is_reg(reg2)) |
duke@435 | 1371 | reg = reg2; |
duke@435 | 1372 | } |
duke@435 | 1373 | return OptoReg::add( reg, chunk ); |
duke@435 | 1374 | } |
duke@435 | 1375 | |
duke@435 | 1376 | // Choose a color in the current chunk |
duke@435 | 1377 | OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { |
duke@435 | 1378 | assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); |
duke@435 | 1379 | assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); |
duke@435 | 1380 | |
duke@435 | 1381 | if( lrg.num_regs() == 1 || // Common Case |
duke@435 | 1382 | !lrg._fat_proj ) // Aligned+adjacent pairs ok |
duke@435 | 1383 | // Use a heuristic to "bias" the color choice |
duke@435 | 1384 | return bias_color(lrg, chunk); |
duke@435 | 1385 | |
kvn@3882 | 1386 | assert(!lrg._is_vector, "should be not vector here" ); |
duke@435 | 1387 | assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
duke@435 | 1388 | |
duke@435 | 1389 | // Fat-proj case or misaligned double argument. |
duke@435 | 1390 | assert(lrg.compute_mask_size() == lrg.num_regs() || |
duke@435 | 1391 | lrg.num_regs() == 2,"fat projs exactly color" ); |
duke@435 | 1392 | assert( !chunk, "always color in 1st chunk" ); |
duke@435 | 1393 | // Return the highest element in the set. |
duke@435 | 1394 | return lrg.mask().find_last_elem(); |
duke@435 | 1395 | } |
duke@435 | 1396 | |
duke@435 | 1397 | // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted |
duke@435 | 1398 | // in reverse order of removal. As long as nothing of hi-degree was yanked, |
duke@435 | 1399 | // everything going back is guaranteed a color. Select that color. If some |
duke@435 | 1400 | // hi-degree LRG cannot get a color then we record that we must spill. |
duke@435 | 1401 | uint PhaseChaitin::Select( ) { |
duke@435 | 1402 | uint spill_reg = LRG::SPILL_REG; |
duke@435 | 1403 | _max_reg = OptoReg::Name(0); // Past max register used |
duke@435 | 1404 | while( _simplified ) { |
duke@435 | 1405 | // Pull next LRG from the simplified list - in reverse order of removal |
duke@435 | 1406 | uint lidx = _simplified; |
duke@435 | 1407 | LRG *lrg = &lrgs(lidx); |
duke@435 | 1408 | _simplified = lrg->_next; |
duke@435 | 1409 | |
duke@435 | 1410 | |
duke@435 | 1411 | #ifndef PRODUCT |
duke@435 | 1412 | if (trace_spilling()) { |
duke@435 | 1413 | ttyLocker ttyl; |
duke@435 | 1414 | tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), |
duke@435 | 1415 | lrg->degrees_of_freedom()); |
duke@435 | 1416 | lrg->dump(); |
duke@435 | 1417 | } |
duke@435 | 1418 | #endif |
duke@435 | 1419 | |
duke@435 | 1420 | // Re-insert into the IFG |
duke@435 | 1421 | _ifg->re_insert(lidx); |
duke@435 | 1422 | if( !lrg->alive() ) continue; |
duke@435 | 1423 | // capture allstackedness flag before mask is hacked |
duke@435 | 1424 | const int is_allstack = lrg->mask().is_AllStack(); |
duke@435 | 1425 | |
duke@435 | 1426 | // Yeah, yeah, yeah, I know, I know. I can refactor this |
duke@435 | 1427 | // to avoid the GOTO, although the refactored code will not |
duke@435 | 1428 | // be much clearer. We arrive here IFF we have a stack-based |
duke@435 | 1429 | // live range that cannot color in the current chunk, and it |
duke@435 | 1430 | // has to move into the next free stack chunk. |
duke@435 | 1431 | int chunk = 0; // Current chunk is first chunk |
duke@435 | 1432 | retry_next_chunk: |
duke@435 | 1433 | |
duke@435 | 1434 | // Remove neighbor colors |
duke@435 | 1435 | IndexSet *s = _ifg->neighbors(lidx); |
duke@435 | 1436 | |
duke@435 | 1437 | debug_only(RegMask orig_mask = lrg->mask();) |
duke@435 | 1438 | IndexSetIterator elements(s); |
duke@435 | 1439 | uint neighbor; |
duke@435 | 1440 | while ((neighbor = elements.next()) != 0) { |
duke@435 | 1441 | // Note that neighbor might be a spill_reg. In this case, exclusion |
duke@435 | 1442 | // of its color will be a no-op, since the spill_reg chunk is in outer |
duke@435 | 1443 | // space. Also, if neighbor is in a different chunk, this exclusion |
duke@435 | 1444 | // will be a no-op. (Later on, if lrg runs out of possible colors in |
duke@435 | 1445 | // its chunk, a new chunk of color may be tried, in which case |
duke@435 | 1446 | // examination of neighbors is started again, at retry_next_chunk.) |
duke@435 | 1447 | LRG &nlrg = lrgs(neighbor); |
duke@435 | 1448 | OptoReg::Name nreg = nlrg.reg(); |
duke@435 | 1449 | // Only subtract masks in the same chunk |
duke@435 | 1450 | if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { |
duke@435 | 1451 | #ifndef PRODUCT |
duke@435 | 1452 | uint size = lrg->mask().Size(); |
duke@435 | 1453 | RegMask rm = lrg->mask(); |
duke@435 | 1454 | #endif |
duke@435 | 1455 | lrg->SUBTRACT(nlrg.mask()); |
duke@435 | 1456 | #ifndef PRODUCT |
duke@435 | 1457 | if (trace_spilling() && lrg->mask().Size() != size) { |
duke@435 | 1458 | ttyLocker ttyl; |
duke@435 | 1459 | tty->print("L%d ", lidx); |
duke@435 | 1460 | rm.dump(); |
duke@435 | 1461 | tty->print(" intersected L%d ", neighbor); |
duke@435 | 1462 | nlrg.mask().dump(); |
duke@435 | 1463 | tty->print(" removed "); |
duke@435 | 1464 | rm.SUBTRACT(lrg->mask()); |
duke@435 | 1465 | rm.dump(); |
duke@435 | 1466 | tty->print(" leaving "); |
duke@435 | 1467 | lrg->mask().dump(); |
duke@435 | 1468 | tty->cr(); |
duke@435 | 1469 | } |
duke@435 | 1470 | #endif |
duke@435 | 1471 | } |
duke@435 | 1472 | } |
duke@435 | 1473 | //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); |
duke@435 | 1474 | // Aligned pairs need aligned masks |
kvn@3882 | 1475 | assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
kvn@3882 | 1476 | if (lrg->num_regs() > 1 && !lrg->_fat_proj) { |
kvn@3882 | 1477 | lrg->clear_to_sets(); |
kvn@3882 | 1478 | } |
duke@435 | 1479 | |
duke@435 | 1480 | // Check if a color is available and if so pick the color |
duke@435 | 1481 | OptoReg::Name reg = choose_color( *lrg, chunk ); |
duke@435 | 1482 | #ifdef SPARC |
duke@435 | 1483 | debug_only(lrg->compute_set_mask_size()); |
kvn@3882 | 1484 | assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
duke@435 | 1485 | #endif |
duke@435 | 1486 | |
duke@435 | 1487 | //--------------- |
duke@435 | 1488 | // If we fail to color and the AllStack flag is set, trigger |
duke@435 | 1489 | // a chunk-rollover event |
duke@435 | 1490 | if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { |
duke@435 | 1491 | // Bump register mask up to next stack chunk |
duke@435 | 1492 | chunk += RegMask::CHUNK_SIZE; |
duke@435 | 1493 | lrg->Set_All(); |
duke@435 | 1494 | |
duke@435 | 1495 | goto retry_next_chunk; |
duke@435 | 1496 | } |
duke@435 | 1497 | |
duke@435 | 1498 | //--------------- |
duke@435 | 1499 | // Did we get a color? |
duke@435 | 1500 | else if( OptoReg::is_valid(reg)) { |
duke@435 | 1501 | #ifndef PRODUCT |
duke@435 | 1502 | RegMask avail_rm = lrg->mask(); |
duke@435 | 1503 | #endif |
duke@435 | 1504 | |
duke@435 | 1505 | // Record selected register |
duke@435 | 1506 | lrg->set_reg(reg); |
duke@435 | 1507 | |
duke@435 | 1508 | if( reg >= _max_reg ) // Compute max register limit |
duke@435 | 1509 | _max_reg = OptoReg::add(reg,1); |
duke@435 | 1510 | // Fold reg back into normal space |
duke@435 | 1511 | reg = OptoReg::add(reg,-chunk); |
duke@435 | 1512 | |
duke@435 | 1513 | // If the live range is not bound, then we actually had some choices |
duke@435 | 1514 | // to make. In this case, the mask has more bits in it than the colors |
twisti@1040 | 1515 | // chosen. Restrict the mask to just what was picked. |
kvn@3882 | 1516 | int n_regs = lrg->num_regs(); |
kvn@3882 | 1517 | assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
kvn@3882 | 1518 | if (n_regs == 1 || !lrg->_fat_proj) { |
kvn@3882 | 1519 | assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity"); |
duke@435 | 1520 | lrg->Clear(); // Clear the mask |
duke@435 | 1521 | lrg->Insert(reg); // Set regmask to match selected reg |
kvn@3882 | 1522 | // For vectors and pairs, also insert the low bit of the pair |
kvn@3882 | 1523 | for (int i = 1; i < n_regs; i++) |
kvn@3882 | 1524 | lrg->Insert(OptoReg::add(reg,-i)); |
kvn@3882 | 1525 | lrg->set_mask_size(n_regs); |
duke@435 | 1526 | } else { // Else fatproj |
duke@435 | 1527 | // mask must be equal to fatproj bits, by definition |
duke@435 | 1528 | } |
duke@435 | 1529 | #ifndef PRODUCT |
duke@435 | 1530 | if (trace_spilling()) { |
duke@435 | 1531 | ttyLocker ttyl; |
duke@435 | 1532 | tty->print("L%d selected ", lidx); |
duke@435 | 1533 | lrg->mask().dump(); |
duke@435 | 1534 | tty->print(" from "); |
duke@435 | 1535 | avail_rm.dump(); |
duke@435 | 1536 | tty->cr(); |
duke@435 | 1537 | } |
duke@435 | 1538 | #endif |
duke@435 | 1539 | // Note that reg is the highest-numbered register in the newly-bound mask. |
duke@435 | 1540 | } // end color available case |
duke@435 | 1541 | |
duke@435 | 1542 | //--------------- |
duke@435 | 1543 | // Live range is live and no colors available |
duke@435 | 1544 | else { |
duke@435 | 1545 | assert( lrg->alive(), "" ); |
never@730 | 1546 | assert( !lrg->_fat_proj || lrg->is_multidef() || |
duke@435 | 1547 | lrg->_def->outcnt() > 0, "fat_proj cannot spill"); |
duke@435 | 1548 | assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); |
duke@435 | 1549 | |
duke@435 | 1550 | // Assign the special spillreg register |
duke@435 | 1551 | lrg->set_reg(OptoReg::Name(spill_reg++)); |
duke@435 | 1552 | // Do not empty the regmask; leave mask_size lying around |
duke@435 | 1553 | // for use during Spilling |
duke@435 | 1554 | #ifndef PRODUCT |
duke@435 | 1555 | if( trace_spilling() ) { |
duke@435 | 1556 | ttyLocker ttyl; |
duke@435 | 1557 | tty->print("L%d spilling with neighbors: ", lidx); |
duke@435 | 1558 | s->dump(); |
duke@435 | 1559 | debug_only(tty->print(" original mask: ")); |
duke@435 | 1560 | debug_only(orig_mask.dump()); |
duke@435 | 1561 | dump_lrg(lidx); |
duke@435 | 1562 | } |
duke@435 | 1563 | #endif |
duke@435 | 1564 | } // end spill case |
duke@435 | 1565 | |
duke@435 | 1566 | } |
duke@435 | 1567 | |
duke@435 | 1568 | return spill_reg-LRG::SPILL_REG; // Return number of spills |
duke@435 | 1569 | } |
duke@435 | 1570 | |
duke@435 | 1571 | // Copy 'was_spilled'-edness from the source Node to the dst Node. |
duke@435 | 1572 | void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { |
duke@435 | 1573 | if( _spilled_once.test(src->_idx) ) { |
duke@435 | 1574 | _spilled_once.set(dst->_idx); |
neliasso@4949 | 1575 | lrgs(_lrg_map.find(dst))._was_spilled1 = 1; |
duke@435 | 1576 | if( _spilled_twice.test(src->_idx) ) { |
duke@435 | 1577 | _spilled_twice.set(dst->_idx); |
neliasso@4949 | 1578 | lrgs(_lrg_map.find(dst))._was_spilled2 = 1; |
duke@435 | 1579 | } |
duke@435 | 1580 | } |
duke@435 | 1581 | } |
duke@435 | 1582 | |
duke@435 | 1583 | // Set the 'spilled_once' or 'spilled_twice' flag on a node. |
duke@435 | 1584 | void PhaseChaitin::set_was_spilled( Node *n ) { |
duke@435 | 1585 | if( _spilled_once.test_set(n->_idx) ) |
duke@435 | 1586 | _spilled_twice.set(n->_idx); |
duke@435 | 1587 | } |
duke@435 | 1588 | |
duke@435 | 1589 | // Convert Ideal spill instructions into proper FramePtr + offset Loads and |
duke@435 | 1590 | // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. |
duke@435 | 1591 | void PhaseChaitin::fixup_spills() { |
duke@435 | 1592 | // This function does only cisc spill work. |
duke@435 | 1593 | if( !UseCISCSpill ) return; |
duke@435 | 1594 | |
duke@435 | 1595 | NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) |
duke@435 | 1596 | |
duke@435 | 1597 | // Grab the Frame Pointer |
adlertz@5539 | 1598 | Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); |
duke@435 | 1599 | |
duke@435 | 1600 | // For all blocks |
adlertz@5539 | 1601 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 1602 | Block* block = _cfg.get_block(i); |
duke@435 | 1603 | |
duke@435 | 1604 | // For all instructions in block |
adlertz@5539 | 1605 | uint last_inst = block->end_idx(); |
adlertz@5539 | 1606 | for (uint j = 1; j <= last_inst; j++) { |
adlertz@5539 | 1607 | Node* n = block->_nodes[j]; |
duke@435 | 1608 | |
duke@435 | 1609 | // Dead instruction??? |
duke@435 | 1610 | assert( n->outcnt() != 0 ||// Nothing dead after post alloc |
duke@435 | 1611 | C->top() == n || // Or the random TOP node |
duke@435 | 1612 | n->is_Proj(), // Or a fat-proj kill node |
duke@435 | 1613 | "No dead instructions after post-alloc" ); |
duke@435 | 1614 | |
duke@435 | 1615 | int inp = n->cisc_operand(); |
duke@435 | 1616 | if( inp != AdlcVMDeps::Not_cisc_spillable ) { |
duke@435 | 1617 | // Convert operand number to edge index number |
duke@435 | 1618 | MachNode *mach = n->as_Mach(); |
duke@435 | 1619 | inp = mach->operand_index(inp); |
duke@435 | 1620 | Node *src = n->in(inp); // Value to load or store |
neliasso@4949 | 1621 | LRG &lrg_cisc = lrgs(_lrg_map.find_const(src)); |
duke@435 | 1622 | OptoReg::Name src_reg = lrg_cisc.reg(); |
duke@435 | 1623 | // Doubles record the HIGH register of an adjacent pair. |
duke@435 | 1624 | src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); |
duke@435 | 1625 | if( OptoReg::is_stack(src_reg) ) { // If input is on stack |
duke@435 | 1626 | // This is a CISC Spill, get stack offset and construct new node |
duke@435 | 1627 | #ifndef PRODUCT |
duke@435 | 1628 | if( TraceCISCSpill ) { |
duke@435 | 1629 | tty->print(" reg-instr: "); |
duke@435 | 1630 | n->dump(); |
duke@435 | 1631 | } |
duke@435 | 1632 | #endif |
duke@435 | 1633 | int stk_offset = reg2offset(src_reg); |
duke@435 | 1634 | // Bailout if we might exceed node limit when spilling this instruction |
duke@435 | 1635 | C->check_node_count(0, "out of nodes fixing spills"); |
duke@435 | 1636 | if (C->failing()) return; |
duke@435 | 1637 | // Transform node |
duke@435 | 1638 | MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach(); |
duke@435 | 1639 | cisc->set_req(inp,fp); // Base register is frame pointer |
duke@435 | 1640 | if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { |
duke@435 | 1641 | assert( cisc->oper_input_base() == 2, "Only adding one edge"); |
duke@435 | 1642 | cisc->ins_req(1,src); // Requires a memory edge |
duke@435 | 1643 | } |
adlertz@5539 | 1644 | block->_nodes.map(j,cisc); // Insert into basic block |
bharadwaj@4315 | 1645 | n->subsume_by(cisc, C); // Correct graph |
duke@435 | 1646 | // |
duke@435 | 1647 | ++_used_cisc_instructions; |
duke@435 | 1648 | #ifndef PRODUCT |
duke@435 | 1649 | if( TraceCISCSpill ) { |
duke@435 | 1650 | tty->print(" cisc-instr: "); |
duke@435 | 1651 | cisc->dump(); |
duke@435 | 1652 | } |
duke@435 | 1653 | #endif |
duke@435 | 1654 | } else { |
duke@435 | 1655 | #ifndef PRODUCT |
duke@435 | 1656 | if( TraceCISCSpill ) { |
duke@435 | 1657 | tty->print(" using reg-instr: "); |
duke@435 | 1658 | n->dump(); |
duke@435 | 1659 | } |
duke@435 | 1660 | #endif |
duke@435 | 1661 | ++_unused_cisc_instructions; // input can be on stack |
duke@435 | 1662 | } |
duke@435 | 1663 | } |
duke@435 | 1664 | |
duke@435 | 1665 | } // End of for all instructions |
duke@435 | 1666 | |
duke@435 | 1667 | } // End of for all blocks |
duke@435 | 1668 | } |
duke@435 | 1669 | |
duke@435 | 1670 | // Helper to stretch above; recursively discover the base Node for a |
duke@435 | 1671 | // given derived Node. Easy for AddP-related machine nodes, but needs |
duke@435 | 1672 | // to be recursive for derived Phis. |
duke@435 | 1673 | Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { |
duke@435 | 1674 | // See if already computed; if so return it |
duke@435 | 1675 | if( derived_base_map[derived->_idx] ) |
duke@435 | 1676 | return derived_base_map[derived->_idx]; |
duke@435 | 1677 | |
duke@435 | 1678 | // See if this happens to be a base. |
duke@435 | 1679 | // NOTE: we use TypePtr instead of TypeOopPtr because we can have |
duke@435 | 1680 | // pointers derived from NULL! These are always along paths that |
duke@435 | 1681 | // can't happen at run-time but the optimizer cannot deduce it so |
duke@435 | 1682 | // we have to handle it gracefully. |
kvn@1164 | 1683 | assert(!derived->bottom_type()->isa_narrowoop() || |
kvn@1164 | 1684 | derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
duke@435 | 1685 | const TypePtr *tj = derived->bottom_type()->isa_ptr(); |
duke@435 | 1686 | // If its an OOP with a non-zero offset, then it is derived. |
kvn@1164 | 1687 | if( tj == NULL || tj->_offset == 0 ) { |
duke@435 | 1688 | derived_base_map[derived->_idx] = derived; |
duke@435 | 1689 | return derived; |
duke@435 | 1690 | } |
duke@435 | 1691 | // Derived is NULL+offset? Base is NULL! |
duke@435 | 1692 | if( derived->is_Con() ) { |
kvn@1164 | 1693 | Node *base = _matcher.mach_null(); |
kvn@1164 | 1694 | assert(base != NULL, "sanity"); |
kvn@1164 | 1695 | if (base->in(0) == NULL) { |
kvn@1164 | 1696 | // Initialize it once and make it shared: |
kvn@1164 | 1697 | // set control to _root and place it into Start block |
kvn@1164 | 1698 | // (where top() node is placed). |
adlertz@5539 | 1699 | base->init_req(0, _cfg.get_root_node()); |
adlertz@5509 | 1700 | Block *startb = _cfg.get_block_for_node(C->top()); |
kvn@1164 | 1701 | startb->_nodes.insert(startb->find_node(C->top()), base ); |
adlertz@5509 | 1702 | _cfg.map_node_to_block(base, startb); |
neliasso@4949 | 1703 | assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); |
kvn@1164 | 1704 | } |
neliasso@4949 | 1705 | if (_lrg_map.live_range_id(base) == 0) { |
kvn@1164 | 1706 | new_lrg(base, maxlrg++); |
kvn@1164 | 1707 | } |
adlertz@5539 | 1708 | assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); |
duke@435 | 1709 | derived_base_map[derived->_idx] = base; |
duke@435 | 1710 | return base; |
duke@435 | 1711 | } |
duke@435 | 1712 | |
duke@435 | 1713 | // Check for AddP-related opcodes |
neliasso@4949 | 1714 | if (!derived->is_Phi()) { |
kvn@3971 | 1715 | assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name())); |
duke@435 | 1716 | Node *base = derived->in(AddPNode::Base); |
duke@435 | 1717 | derived_base_map[derived->_idx] = base; |
duke@435 | 1718 | return base; |
duke@435 | 1719 | } |
duke@435 | 1720 | |
duke@435 | 1721 | // Recursively find bases for Phis. |
duke@435 | 1722 | // First check to see if we can avoid a base Phi here. |
duke@435 | 1723 | Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); |
duke@435 | 1724 | uint i; |
duke@435 | 1725 | for( i = 2; i < derived->req(); i++ ) |
duke@435 | 1726 | if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) |
duke@435 | 1727 | break; |
duke@435 | 1728 | // Went to the end without finding any different bases? |
duke@435 | 1729 | if( i == derived->req() ) { // No need for a base Phi here |
duke@435 | 1730 | derived_base_map[derived->_idx] = base; |
duke@435 | 1731 | return base; |
duke@435 | 1732 | } |
duke@435 | 1733 | |
duke@435 | 1734 | // Now we see we need a base-Phi here to merge the bases |
kvn@1164 | 1735 | const Type *t = base->bottom_type(); |
kvn@4115 | 1736 | base = new (C) PhiNode( derived->in(0), t ); |
kvn@1164 | 1737 | for( i = 1; i < derived->req(); i++ ) { |
duke@435 | 1738 | base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); |
kvn@1164 | 1739 | t = t->meet(base->in(i)->bottom_type()); |
kvn@1164 | 1740 | } |
kvn@1164 | 1741 | base->as_Phi()->set_type(t); |
duke@435 | 1742 | |
duke@435 | 1743 | // Search the current block for an existing base-Phi |
adlertz@5509 | 1744 | Block *b = _cfg.get_block_for_node(derived); |
duke@435 | 1745 | for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi |
duke@435 | 1746 | Node *phi = b->_nodes[i]; |
duke@435 | 1747 | if( !phi->is_Phi() ) { // Found end of Phis with no match? |
duke@435 | 1748 | b->_nodes.insert( i, base ); // Must insert created Phi here as base |
adlertz@5509 | 1749 | _cfg.map_node_to_block(base, b); |
duke@435 | 1750 | new_lrg(base,maxlrg++); |
duke@435 | 1751 | break; |
duke@435 | 1752 | } |
duke@435 | 1753 | // See if Phi matches. |
duke@435 | 1754 | uint j; |
duke@435 | 1755 | for( j = 1; j < base->req(); j++ ) |
duke@435 | 1756 | if( phi->in(j) != base->in(j) && |
duke@435 | 1757 | !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs |
duke@435 | 1758 | break; |
duke@435 | 1759 | if( j == base->req() ) { // All inputs match? |
duke@435 | 1760 | base = phi; // Then use existing 'phi' and drop 'base' |
duke@435 | 1761 | break; |
duke@435 | 1762 | } |
duke@435 | 1763 | } |
duke@435 | 1764 | |
duke@435 | 1765 | |
duke@435 | 1766 | // Cache info for later passes |
duke@435 | 1767 | derived_base_map[derived->_idx] = base; |
duke@435 | 1768 | return base; |
duke@435 | 1769 | } |
duke@435 | 1770 | |
duke@435 | 1771 | // At each Safepoint, insert extra debug edges for each pair of derived value/ |
duke@435 | 1772 | // base pointer that is live across the Safepoint for oopmap building. The |
duke@435 | 1773 | // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the |
duke@435 | 1774 | // required edge set. |
neliasso@4949 | 1775 | bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { |
duke@435 | 1776 | int must_recompute_live = false; |
neliasso@4949 | 1777 | uint maxlrg = _lrg_map.max_lrg_id(); |
duke@435 | 1778 | Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); |
duke@435 | 1779 | memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); |
duke@435 | 1780 | |
duke@435 | 1781 | // For all blocks in RPO do... |
adlertz@5539 | 1782 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 1783 | Block* block = _cfg.get_block(i); |
duke@435 | 1784 | // Note use of deep-copy constructor. I cannot hammer the original |
duke@435 | 1785 | // liveout bits, because they are needed by the following coalesce pass. |
adlertz@5539 | 1786 | IndexSet liveout(_live->live(block)); |
duke@435 | 1787 | |
adlertz@5539 | 1788 | for (uint j = block->end_idx() + 1; j > 1; j--) { |
adlertz@5539 | 1789 | Node* n = block->_nodes[j - 1]; |
duke@435 | 1790 | |
duke@435 | 1791 | // Pre-split compares of loop-phis. Loop-phis form a cycle we would |
duke@435 | 1792 | // like to see in the same register. Compare uses the loop-phi and so |
duke@435 | 1793 | // extends its live range BUT cannot be part of the cycle. If this |
duke@435 | 1794 | // extended live range overlaps with the update of the loop-phi value |
duke@435 | 1795 | // we need both alive at the same time -- which requires at least 1 |
duke@435 | 1796 | // copy. But because Intel has only 2-address registers we end up with |
duke@435 | 1797 | // at least 2 copies, one before the loop-phi update instruction and |
duke@435 | 1798 | // one after. Instead we split the input to the compare just after the |
duke@435 | 1799 | // phi. |
duke@435 | 1800 | if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { |
duke@435 | 1801 | Node *phi = n->in(1); |
duke@435 | 1802 | if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { |
adlertz@5509 | 1803 | Block *phi_block = _cfg.get_block_for_node(phi); |
adlertz@5539 | 1804 | if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { |
duke@435 | 1805 | const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; |
duke@435 | 1806 | Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); |
duke@435 | 1807 | insert_proj( phi_block, 1, spill, maxlrg++ ); |
duke@435 | 1808 | n->set_req(1,spill); |
duke@435 | 1809 | must_recompute_live = true; |
duke@435 | 1810 | } |
duke@435 | 1811 | } |
duke@435 | 1812 | } |
duke@435 | 1813 | |
duke@435 | 1814 | // Get value being defined |
neliasso@4949 | 1815 | uint lidx = _lrg_map.live_range_id(n); |
neliasso@4949 | 1816 | // Ignore the occasional brand-new live range |
neliasso@4949 | 1817 | if (lidx && lidx < _lrg_map.max_lrg_id()) { |
duke@435 | 1818 | // Remove from live-out set |
duke@435 | 1819 | liveout.remove(lidx); |
duke@435 | 1820 | |
duke@435 | 1821 | // Copies do not define a new value and so do not interfere. |
duke@435 | 1822 | // Remove the copies source from the liveout set before interfering. |
duke@435 | 1823 | uint idx = n->is_Copy(); |
neliasso@4949 | 1824 | if (idx) { |
neliasso@4949 | 1825 | liveout.remove(_lrg_map.live_range_id(n->in(idx))); |
neliasso@4949 | 1826 | } |
duke@435 | 1827 | } |
duke@435 | 1828 | |
duke@435 | 1829 | // Found a safepoint? |
duke@435 | 1830 | JVMState *jvms = n->jvms(); |
duke@435 | 1831 | if( jvms ) { |
duke@435 | 1832 | // Now scan for a live derived pointer |
duke@435 | 1833 | IndexSetIterator elements(&liveout); |
duke@435 | 1834 | uint neighbor; |
duke@435 | 1835 | while ((neighbor = elements.next()) != 0) { |
duke@435 | 1836 | // Find reaching DEF for base and derived values |
duke@435 | 1837 | // This works because we are still in SSA during this call. |
duke@435 | 1838 | Node *derived = lrgs(neighbor)._def; |
duke@435 | 1839 | const TypePtr *tj = derived->bottom_type()->isa_ptr(); |
kvn@1164 | 1840 | assert(!derived->bottom_type()->isa_narrowoop() || |
kvn@1164 | 1841 | derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
duke@435 | 1842 | // If its an OOP with a non-zero offset, then it is derived. |
duke@435 | 1843 | if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { |
neliasso@4949 | 1844 | Node *base = find_base_for_derived(derived_base_map, derived, maxlrg); |
neliasso@4949 | 1845 | assert(base->_idx < _lrg_map.size(), ""); |
duke@435 | 1846 | // Add reaching DEFs of derived pointer and base pointer as a |
duke@435 | 1847 | // pair of inputs |
neliasso@4949 | 1848 | n->add_req(derived); |
neliasso@4949 | 1849 | n->add_req(base); |
duke@435 | 1850 | |
duke@435 | 1851 | // See if the base pointer is already live to this point. |
duke@435 | 1852 | // Since I'm working on the SSA form, live-ness amounts to |
duke@435 | 1853 | // reaching def's. So if I find the base's live range then |
duke@435 | 1854 | // I know the base's def reaches here. |
neliasso@4949 | 1855 | if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or |
neliasso@4949 | 1856 | !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND |
neliasso@4949 | 1857 | (_lrg_map.live_range_id(base) > 0) && // not a constant |
adlertz@5539 | 1858 | _cfg.get_block_for_node(base) != block) { // base not def'd in blk) |
duke@435 | 1859 | // Base pointer is not currently live. Since I stretched |
duke@435 | 1860 | // the base pointer to here and it crosses basic-block |
duke@435 | 1861 | // boundaries, the global live info is now incorrect. |
duke@435 | 1862 | // Recompute live. |
duke@435 | 1863 | must_recompute_live = true; |
duke@435 | 1864 | } // End of if base pointer is not live to debug info |
duke@435 | 1865 | } |
duke@435 | 1866 | } // End of scan all live data for derived ptrs crossing GC point |
duke@435 | 1867 | } // End of if found a GC point |
duke@435 | 1868 | |
duke@435 | 1869 | // Make all inputs live |
neliasso@4949 | 1870 | if (!n->is_Phi()) { // Phi function uses come from prior block |
neliasso@4949 | 1871 | for (uint k = 1; k < n->req(); k++) { |
neliasso@4949 | 1872 | uint lidx = _lrg_map.live_range_id(n->in(k)); |
neliasso@4949 | 1873 | if (lidx < _lrg_map.max_lrg_id()) { |
neliasso@4949 | 1874 | liveout.insert(lidx); |
neliasso@4949 | 1875 | } |
duke@435 | 1876 | } |
duke@435 | 1877 | } |
duke@435 | 1878 | |
duke@435 | 1879 | } // End of forall instructions in block |
duke@435 | 1880 | liveout.clear(); // Free the memory used by liveout. |
duke@435 | 1881 | |
duke@435 | 1882 | } // End of forall blocks |
neliasso@4949 | 1883 | _lrg_map.set_max_lrg_id(maxlrg); |
duke@435 | 1884 | |
duke@435 | 1885 | // If I created a new live range I need to recompute live |
neliasso@4949 | 1886 | if (maxlrg != _ifg->_maxlrg) { |
duke@435 | 1887 | must_recompute_live = true; |
neliasso@4949 | 1888 | } |
duke@435 | 1889 | |
duke@435 | 1890 | return must_recompute_live != 0; |
duke@435 | 1891 | } |
duke@435 | 1892 | |
duke@435 | 1893 | // Extend the node to LRG mapping |
neliasso@4949 | 1894 | |
neliasso@4949 | 1895 | void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { |
neliasso@4949 | 1896 | _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); |
duke@435 | 1897 | } |
duke@435 | 1898 | |
duke@435 | 1899 | #ifndef PRODUCT |
neliasso@4949 | 1900 | void PhaseChaitin::dump(const Node *n) const { |
neliasso@4949 | 1901 | uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; |
duke@435 | 1902 | tty->print("L%d",r); |
neliasso@4949 | 1903 | if (r && n->Opcode() != Op_Phi) { |
duke@435 | 1904 | if( _node_regs ) { // Got a post-allocation copy of allocation? |
duke@435 | 1905 | tty->print("["); |
duke@435 | 1906 | OptoReg::Name second = get_reg_second(n); |
duke@435 | 1907 | if( OptoReg::is_valid(second) ) { |
duke@435 | 1908 | if( OptoReg::is_reg(second) ) |
duke@435 | 1909 | tty->print("%s:",Matcher::regName[second]); |
duke@435 | 1910 | else |
duke@435 | 1911 | tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); |
duke@435 | 1912 | } |
duke@435 | 1913 | OptoReg::Name first = get_reg_first(n); |
duke@435 | 1914 | if( OptoReg::is_reg(first) ) |
duke@435 | 1915 | tty->print("%s]",Matcher::regName[first]); |
duke@435 | 1916 | else |
duke@435 | 1917 | tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); |
duke@435 | 1918 | } else |
duke@435 | 1919 | n->out_RegMask().dump(); |
duke@435 | 1920 | } |
duke@435 | 1921 | tty->print("/N%d\t",n->_idx); |
duke@435 | 1922 | tty->print("%s === ", n->Name()); |
duke@435 | 1923 | uint k; |
neliasso@4949 | 1924 | for (k = 0; k < n->req(); k++) { |
duke@435 | 1925 | Node *m = n->in(k); |
neliasso@4949 | 1926 | if (!m) { |
neliasso@4949 | 1927 | tty->print("_ "); |
neliasso@4949 | 1928 | } |
duke@435 | 1929 | else { |
neliasso@4949 | 1930 | uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; |
duke@435 | 1931 | tty->print("L%d",r); |
duke@435 | 1932 | // Data MultiNode's can have projections with no real registers. |
duke@435 | 1933 | // Don't die while dumping them. |
duke@435 | 1934 | int op = n->Opcode(); |
duke@435 | 1935 | if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { |
duke@435 | 1936 | if( _node_regs ) { |
duke@435 | 1937 | tty->print("["); |
duke@435 | 1938 | OptoReg::Name second = get_reg_second(n->in(k)); |
duke@435 | 1939 | if( OptoReg::is_valid(second) ) { |
duke@435 | 1940 | if( OptoReg::is_reg(second) ) |
duke@435 | 1941 | tty->print("%s:",Matcher::regName[second]); |
duke@435 | 1942 | else |
duke@435 | 1943 | tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), |
duke@435 | 1944 | reg2offset_unchecked(second)); |
duke@435 | 1945 | } |
duke@435 | 1946 | OptoReg::Name first = get_reg_first(n->in(k)); |
duke@435 | 1947 | if( OptoReg::is_reg(first) ) |
duke@435 | 1948 | tty->print("%s]",Matcher::regName[first]); |
duke@435 | 1949 | else |
duke@435 | 1950 | tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), |
duke@435 | 1951 | reg2offset_unchecked(first)); |
duke@435 | 1952 | } else |
duke@435 | 1953 | n->in_RegMask(k).dump(); |
duke@435 | 1954 | } |
duke@435 | 1955 | tty->print("/N%d ",m->_idx); |
duke@435 | 1956 | } |
duke@435 | 1957 | } |
duke@435 | 1958 | if( k < n->len() && n->in(k) ) tty->print("| "); |
duke@435 | 1959 | for( ; k < n->len(); k++ ) { |
duke@435 | 1960 | Node *m = n->in(k); |
neliasso@4949 | 1961 | if(!m) { |
neliasso@4949 | 1962 | break; |
neliasso@4949 | 1963 | } |
neliasso@4949 | 1964 | uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; |
duke@435 | 1965 | tty->print("L%d",r); |
duke@435 | 1966 | tty->print("/N%d ",m->_idx); |
duke@435 | 1967 | } |
duke@435 | 1968 | if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); |
duke@435 | 1969 | else n->dump_spec(tty); |
duke@435 | 1970 | if( _spilled_once.test(n->_idx ) ) { |
duke@435 | 1971 | tty->print(" Spill_1"); |
duke@435 | 1972 | if( _spilled_twice.test(n->_idx ) ) |
duke@435 | 1973 | tty->print(" Spill_2"); |
duke@435 | 1974 | } |
duke@435 | 1975 | tty->print("\n"); |
duke@435 | 1976 | } |
duke@435 | 1977 | |
adlertz@5509 | 1978 | void PhaseChaitin::dump(const Block *b) const { |
adlertz@5509 | 1979 | b->dump_head(&_cfg); |
duke@435 | 1980 | |
duke@435 | 1981 | // For all instructions |
duke@435 | 1982 | for( uint j = 0; j < b->_nodes.size(); j++ ) |
duke@435 | 1983 | dump(b->_nodes[j]); |
duke@435 | 1984 | // Print live-out info at end of block |
duke@435 | 1985 | if( _live ) { |
duke@435 | 1986 | tty->print("Liveout: "); |
duke@435 | 1987 | IndexSet *live = _live->live(b); |
duke@435 | 1988 | IndexSetIterator elements(live); |
duke@435 | 1989 | tty->print("{"); |
duke@435 | 1990 | uint i; |
duke@435 | 1991 | while ((i = elements.next()) != 0) { |
neliasso@4949 | 1992 | tty->print("L%d ", _lrg_map.find_const(i)); |
duke@435 | 1993 | } |
duke@435 | 1994 | tty->print_cr("}"); |
duke@435 | 1995 | } |
duke@435 | 1996 | tty->print("\n"); |
duke@435 | 1997 | } |
duke@435 | 1998 | |
duke@435 | 1999 | void PhaseChaitin::dump() const { |
duke@435 | 2000 | tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", |
duke@435 | 2001 | _matcher._new_SP, _framesize ); |
duke@435 | 2002 | |
duke@435 | 2003 | // For all blocks |
adlertz@5539 | 2004 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 2005 | dump(_cfg.get_block(i)); |
adlertz@5539 | 2006 | } |
duke@435 | 2007 | // End of per-block dump |
duke@435 | 2008 | tty->print("\n"); |
duke@435 | 2009 | |
duke@435 | 2010 | if (!_ifg) { |
duke@435 | 2011 | tty->print("(No IFG.)\n"); |
duke@435 | 2012 | return; |
duke@435 | 2013 | } |
duke@435 | 2014 | |
duke@435 | 2015 | // Dump LRG array |
duke@435 | 2016 | tty->print("--- Live RanGe Array ---\n"); |
neliasso@4949 | 2017 | for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) { |
duke@435 | 2018 | tty->print("L%d: ",i2); |
neliasso@4949 | 2019 | if (i2 < _ifg->_maxlrg) { |
neliasso@4949 | 2020 | lrgs(i2).dump(); |
neliasso@4949 | 2021 | } |
neliasso@4949 | 2022 | else { |
neliasso@4949 | 2023 | tty->print_cr("new LRG"); |
neliasso@4949 | 2024 | } |
duke@435 | 2025 | } |
duke@435 | 2026 | tty->print_cr(""); |
duke@435 | 2027 | |
duke@435 | 2028 | // Dump lo-degree list |
duke@435 | 2029 | tty->print("Lo degree: "); |
duke@435 | 2030 | for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) |
duke@435 | 2031 | tty->print("L%d ",i3); |
duke@435 | 2032 | tty->print_cr(""); |
duke@435 | 2033 | |
duke@435 | 2034 | // Dump lo-stk-degree list |
duke@435 | 2035 | tty->print("Lo stk degree: "); |
duke@435 | 2036 | for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) |
duke@435 | 2037 | tty->print("L%d ",i4); |
duke@435 | 2038 | tty->print_cr(""); |
duke@435 | 2039 | |
duke@435 | 2040 | // Dump lo-degree list |
duke@435 | 2041 | tty->print("Hi degree: "); |
duke@435 | 2042 | for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) |
duke@435 | 2043 | tty->print("L%d ",i5); |
duke@435 | 2044 | tty->print_cr(""); |
duke@435 | 2045 | } |
duke@435 | 2046 | |
duke@435 | 2047 | void PhaseChaitin::dump_degree_lists() const { |
duke@435 | 2048 | // Dump lo-degree list |
duke@435 | 2049 | tty->print("Lo degree: "); |
duke@435 | 2050 | for( uint i = _lo_degree; i; i = lrgs(i)._next ) |
duke@435 | 2051 | tty->print("L%d ",i); |
duke@435 | 2052 | tty->print_cr(""); |
duke@435 | 2053 | |
duke@435 | 2054 | // Dump lo-stk-degree list |
duke@435 | 2055 | tty->print("Lo stk degree: "); |
duke@435 | 2056 | for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) |
duke@435 | 2057 | tty->print("L%d ",i2); |
duke@435 | 2058 | tty->print_cr(""); |
duke@435 | 2059 | |
duke@435 | 2060 | // Dump lo-degree list |
duke@435 | 2061 | tty->print("Hi degree: "); |
duke@435 | 2062 | for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) |
duke@435 | 2063 | tty->print("L%d ",i3); |
duke@435 | 2064 | tty->print_cr(""); |
duke@435 | 2065 | } |
duke@435 | 2066 | |
duke@435 | 2067 | void PhaseChaitin::dump_simplified() const { |
duke@435 | 2068 | tty->print("Simplified: "); |
duke@435 | 2069 | for( uint i = _simplified; i; i = lrgs(i)._next ) |
duke@435 | 2070 | tty->print("L%d ",i); |
duke@435 | 2071 | tty->print_cr(""); |
duke@435 | 2072 | } |
duke@435 | 2073 | |
duke@435 | 2074 | static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { |
duke@435 | 2075 | if ((int)reg < 0) |
duke@435 | 2076 | sprintf(buf, "<OptoReg::%d>", (int)reg); |
duke@435 | 2077 | else if (OptoReg::is_reg(reg)) |
duke@435 | 2078 | strcpy(buf, Matcher::regName[reg]); |
duke@435 | 2079 | else |
duke@435 | 2080 | sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), |
duke@435 | 2081 | pc->reg2offset(reg)); |
duke@435 | 2082 | return buf+strlen(buf); |
duke@435 | 2083 | } |
duke@435 | 2084 | |
duke@435 | 2085 | // Dump a register name into a buffer. Be intelligent if we get called |
duke@435 | 2086 | // before allocation is complete. |
duke@435 | 2087 | char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { |
duke@435 | 2088 | if( !this ) { // Not got anything? |
duke@435 | 2089 | sprintf(buf,"N%d",n->_idx); // Then use Node index |
duke@435 | 2090 | } else if( _node_regs ) { |
duke@435 | 2091 | // Post allocation, use direct mappings, no LRG info available |
duke@435 | 2092 | print_reg( get_reg_first(n), this, buf ); |
duke@435 | 2093 | } else { |
neliasso@4949 | 2094 | uint lidx = _lrg_map.find_const(n); // Grab LRG number |
duke@435 | 2095 | if( !_ifg ) { |
duke@435 | 2096 | sprintf(buf,"L%d",lidx); // No register binding yet |
duke@435 | 2097 | } else if( !lidx ) { // Special, not allocated value |
duke@435 | 2098 | strcpy(buf,"Special"); |
kvn@3882 | 2099 | } else { |
kvn@3882 | 2100 | if (lrgs(lidx)._is_vector) { |
kvn@3882 | 2101 | if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) |
kvn@3882 | 2102 | print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register |
kvn@3882 | 2103 | else |
kvn@3882 | 2104 | sprintf(buf,"L%d",lidx); // No register binding yet |
kvn@3882 | 2105 | } else if( (lrgs(lidx).num_regs() == 1) |
kvn@3882 | 2106 | ? lrgs(lidx).mask().is_bound1() |
kvn@3882 | 2107 | : lrgs(lidx).mask().is_bound_pair() ) { |
kvn@3882 | 2108 | // Hah! We have a bound machine register |
kvn@3882 | 2109 | print_reg( lrgs(lidx).reg(), this, buf ); |
kvn@3882 | 2110 | } else { |
kvn@3882 | 2111 | sprintf(buf,"L%d",lidx); // No register binding yet |
kvn@3882 | 2112 | } |
duke@435 | 2113 | } |
duke@435 | 2114 | } |
duke@435 | 2115 | return buf+strlen(buf); |
duke@435 | 2116 | } |
duke@435 | 2117 | |
duke@435 | 2118 | void PhaseChaitin::dump_for_spill_split_recycle() const { |
duke@435 | 2119 | if( WizardMode && (PrintCompilation || PrintOpto) ) { |
duke@435 | 2120 | // Display which live ranges need to be split and the allocator's state |
duke@435 | 2121 | tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); |
neliasso@4949 | 2122 | for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { |
duke@435 | 2123 | if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { |
duke@435 | 2124 | tty->print("L%d: ", bidx); |
duke@435 | 2125 | lrgs(bidx).dump(); |
duke@435 | 2126 | } |
duke@435 | 2127 | } |
duke@435 | 2128 | tty->cr(); |
duke@435 | 2129 | dump(); |
duke@435 | 2130 | } |
duke@435 | 2131 | } |
duke@435 | 2132 | |
duke@435 | 2133 | void PhaseChaitin::dump_frame() const { |
duke@435 | 2134 | const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); |
duke@435 | 2135 | const TypeTuple *domain = C->tf()->domain(); |
duke@435 | 2136 | const int argcnt = domain->cnt() - TypeFunc::Parms; |
duke@435 | 2137 | |
duke@435 | 2138 | // Incoming arguments in registers dump |
duke@435 | 2139 | for( int k = 0; k < argcnt; k++ ) { |
duke@435 | 2140 | OptoReg::Name parmreg = _matcher._parm_regs[k].first(); |
duke@435 | 2141 | if( OptoReg::is_reg(parmreg)) { |
duke@435 | 2142 | const char *reg_name = OptoReg::regname(parmreg); |
duke@435 | 2143 | tty->print("#r%3.3d %s", parmreg, reg_name); |
duke@435 | 2144 | parmreg = _matcher._parm_regs[k].second(); |
duke@435 | 2145 | if( OptoReg::is_reg(parmreg)) { |
duke@435 | 2146 | tty->print(":%s", OptoReg::regname(parmreg)); |
duke@435 | 2147 | } |
duke@435 | 2148 | tty->print(" : parm %d: ", k); |
duke@435 | 2149 | domain->field_at(k + TypeFunc::Parms)->dump(); |
duke@435 | 2150 | tty->print_cr(""); |
duke@435 | 2151 | } |
duke@435 | 2152 | } |
duke@435 | 2153 | |
duke@435 | 2154 | // Check for un-owned padding above incoming args |
duke@435 | 2155 | OptoReg::Name reg = _matcher._new_SP; |
duke@435 | 2156 | if( reg > _matcher._in_arg_limit ) { |
duke@435 | 2157 | reg = OptoReg::add(reg, -1); |
duke@435 | 2158 | tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); |
duke@435 | 2159 | } |
duke@435 | 2160 | |
duke@435 | 2161 | // Incoming argument area dump |
duke@435 | 2162 | OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); |
duke@435 | 2163 | while( reg > begin_in_arg ) { |
duke@435 | 2164 | reg = OptoReg::add(reg, -1); |
duke@435 | 2165 | tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); |
duke@435 | 2166 | int j; |
duke@435 | 2167 | for( j = 0; j < argcnt; j++) { |
duke@435 | 2168 | if( _matcher._parm_regs[j].first() == reg || |
duke@435 | 2169 | _matcher._parm_regs[j].second() == reg ) { |
duke@435 | 2170 | tty->print("parm %d: ",j); |
duke@435 | 2171 | domain->field_at(j + TypeFunc::Parms)->dump(); |
duke@435 | 2172 | tty->print_cr(""); |
duke@435 | 2173 | break; |
duke@435 | 2174 | } |
duke@435 | 2175 | } |
duke@435 | 2176 | if( j >= argcnt ) |
duke@435 | 2177 | tty->print_cr("HOLE, owned by SELF"); |
duke@435 | 2178 | } |
duke@435 | 2179 | |
duke@435 | 2180 | // Old outgoing preserve area |
duke@435 | 2181 | while( reg > _matcher._old_SP ) { |
duke@435 | 2182 | reg = OptoReg::add(reg, -1); |
duke@435 | 2183 | tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); |
duke@435 | 2184 | } |
duke@435 | 2185 | |
duke@435 | 2186 | // Old SP |
duke@435 | 2187 | tty->print_cr("# -- Old %s -- Framesize: %d --",fp, |
duke@435 | 2188 | reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); |
duke@435 | 2189 | |
duke@435 | 2190 | // Preserve area dump |
kvn@3577 | 2191 | int fixed_slots = C->fixed_slots(); |
kvn@3577 | 2192 | OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots()); |
kvn@3577 | 2193 | OptoReg::Name return_addr = _matcher.return_addr(); |
kvn@3577 | 2194 | |
duke@435 | 2195 | reg = OptoReg::add(reg, -1); |
kvn@3577 | 2196 | while (OptoReg::is_stack(reg)) { |
duke@435 | 2197 | tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); |
kvn@3577 | 2198 | if (return_addr == reg) { |
duke@435 | 2199 | tty->print_cr("return address"); |
kvn@3577 | 2200 | } else if (reg >= begin_in_preserve) { |
kvn@3577 | 2201 | // Preserved slots are present on x86 |
kvn@3577 | 2202 | if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word)) |
kvn@3577 | 2203 | tty->print_cr("saved fp register"); |
kvn@3577 | 2204 | else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) && |
kvn@3577 | 2205 | VerifyStackAtCalls) |
kvn@3577 | 2206 | tty->print_cr("0xBADB100D +VerifyStackAtCalls"); |
kvn@3577 | 2207 | else |
kvn@3577 | 2208 | tty->print_cr("in_preserve"); |
kvn@3577 | 2209 | } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) { |
duke@435 | 2210 | tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); |
kvn@3577 | 2211 | } else { |
kvn@3577 | 2212 | tty->print_cr("pad2, stack alignment"); |
kvn@3577 | 2213 | } |
duke@435 | 2214 | reg = OptoReg::add(reg, -1); |
duke@435 | 2215 | } |
duke@435 | 2216 | |
duke@435 | 2217 | // Spill area dump |
duke@435 | 2218 | reg = OptoReg::add(_matcher._new_SP, _framesize ); |
duke@435 | 2219 | while( reg > _matcher._out_arg_limit ) { |
duke@435 | 2220 | reg = OptoReg::add(reg, -1); |
duke@435 | 2221 | tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); |
duke@435 | 2222 | } |
duke@435 | 2223 | |
duke@435 | 2224 | // Outgoing argument area dump |
duke@435 | 2225 | while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { |
duke@435 | 2226 | reg = OptoReg::add(reg, -1); |
duke@435 | 2227 | tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); |
duke@435 | 2228 | } |
duke@435 | 2229 | |
duke@435 | 2230 | // Outgoing new preserve area |
duke@435 | 2231 | while( reg > _matcher._new_SP ) { |
duke@435 | 2232 | reg = OptoReg::add(reg, -1); |
duke@435 | 2233 | tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); |
duke@435 | 2234 | } |
duke@435 | 2235 | tty->print_cr("#"); |
duke@435 | 2236 | } |
duke@435 | 2237 | |
duke@435 | 2238 | void PhaseChaitin::dump_bb( uint pre_order ) const { |
duke@435 | 2239 | tty->print_cr("---dump of B%d---",pre_order); |
adlertz@5539 | 2240 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 2241 | Block* block = _cfg.get_block(i); |
adlertz@5539 | 2242 | if (block->_pre_order == pre_order) { |
adlertz@5539 | 2243 | dump(block); |
adlertz@5539 | 2244 | } |
duke@435 | 2245 | } |
duke@435 | 2246 | } |
duke@435 | 2247 | |
never@2358 | 2248 | void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
duke@435 | 2249 | tty->print_cr("---dump of L%d---",lidx); |
duke@435 | 2250 | |
neliasso@4949 | 2251 | if (_ifg) { |
neliasso@4949 | 2252 | if (lidx >= _lrg_map.max_lrg_id()) { |
duke@435 | 2253 | tty->print("Attempt to print live range index beyond max live range.\n"); |
duke@435 | 2254 | return; |
duke@435 | 2255 | } |
duke@435 | 2256 | tty->print("L%d: ",lidx); |
neliasso@4949 | 2257 | if (lidx < _ifg->_maxlrg) { |
neliasso@4949 | 2258 | lrgs(lidx).dump(); |
neliasso@4949 | 2259 | } else { |
neliasso@4949 | 2260 | tty->print_cr("new LRG"); |
neliasso@4949 | 2261 | } |
duke@435 | 2262 | } |
never@2358 | 2263 | if( _ifg && lidx < _ifg->_maxlrg) { |
never@2358 | 2264 | tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
duke@435 | 2265 | _ifg->neighbors(lidx)->dump(); |
duke@435 | 2266 | tty->cr(); |
duke@435 | 2267 | } |
duke@435 | 2268 | // For all blocks |
adlertz@5539 | 2269 | for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adlertz@5539 | 2270 | Block* block = _cfg.get_block(i); |
duke@435 | 2271 | int dump_once = 0; |
duke@435 | 2272 | |
duke@435 | 2273 | // For all instructions |
adlertz@5539 | 2274 | for( uint j = 0; j < block->_nodes.size(); j++ ) { |
adlertz@5539 | 2275 | Node *n = block->_nodes[j]; |
neliasso@4949 | 2276 | if (_lrg_map.find_const(n) == lidx) { |
neliasso@4949 | 2277 | if (!dump_once++) { |
duke@435 | 2278 | tty->cr(); |
adlertz@5539 | 2279 | block->dump_head(&_cfg); |
duke@435 | 2280 | } |
duke@435 | 2281 | dump(n); |
duke@435 | 2282 | continue; |
duke@435 | 2283 | } |
never@2358 | 2284 | if (!defs_only) { |
never@2358 | 2285 | uint cnt = n->req(); |
never@2358 | 2286 | for( uint k = 1; k < cnt; k++ ) { |
never@2358 | 2287 | Node *m = n->in(k); |
neliasso@4949 | 2288 | if (!m) { |
neliasso@4949 | 2289 | continue; // be robust in the dumper |
neliasso@4949 | 2290 | } |
neliasso@4949 | 2291 | if (_lrg_map.find_const(m) == lidx) { |
neliasso@4949 | 2292 | if (!dump_once++) { |
never@2358 | 2293 | tty->cr(); |
adlertz@5539 | 2294 | block->dump_head(&_cfg); |
never@2358 | 2295 | } |
never@2358 | 2296 | dump(n); |
duke@435 | 2297 | } |
duke@435 | 2298 | } |
duke@435 | 2299 | } |
duke@435 | 2300 | } |
duke@435 | 2301 | } // End of per-block dump |
duke@435 | 2302 | tty->cr(); |
duke@435 | 2303 | } |
duke@435 | 2304 | #endif // not PRODUCT |
duke@435 | 2305 | |
duke@435 | 2306 | int PhaseChaitin::_final_loads = 0; |
duke@435 | 2307 | int PhaseChaitin::_final_stores = 0; |
duke@435 | 2308 | int PhaseChaitin::_final_memoves= 0; |
duke@435 | 2309 | int PhaseChaitin::_final_copies = 0; |
duke@435 | 2310 | double PhaseChaitin::_final_load_cost = 0; |
duke@435 | 2311 | double PhaseChaitin::_final_store_cost = 0; |
duke@435 | 2312 | double PhaseChaitin::_final_memove_cost= 0; |
duke@435 | 2313 | double PhaseChaitin::_final_copy_cost = 0; |
duke@435 | 2314 | int PhaseChaitin::_conserv_coalesce = 0; |
duke@435 | 2315 | int PhaseChaitin::_conserv_coalesce_pair = 0; |
duke@435 | 2316 | int PhaseChaitin::_conserv_coalesce_trie = 0; |
duke@435 | 2317 | int PhaseChaitin::_conserv_coalesce_quad = 0; |
duke@435 | 2318 | int PhaseChaitin::_post_alloc = 0; |
duke@435 | 2319 | int PhaseChaitin::_lost_opp_pp_coalesce = 0; |
duke@435 | 2320 | int PhaseChaitin::_lost_opp_cflow_coalesce = 0; |
duke@435 | 2321 | int PhaseChaitin::_used_cisc_instructions = 0; |
duke@435 | 2322 | int PhaseChaitin::_unused_cisc_instructions = 0; |
duke@435 | 2323 | int PhaseChaitin::_allocator_attempts = 0; |
duke@435 | 2324 | int PhaseChaitin::_allocator_successes = 0; |
duke@435 | 2325 | |
duke@435 | 2326 | #ifndef PRODUCT |
duke@435 | 2327 | uint PhaseChaitin::_high_pressure = 0; |
duke@435 | 2328 | uint PhaseChaitin::_low_pressure = 0; |
duke@435 | 2329 | |
duke@435 | 2330 | void PhaseChaitin::print_chaitin_statistics() { |
duke@435 | 2331 | tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); |
duke@435 | 2332 | tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); |
duke@435 | 2333 | tty->print_cr("Adjusted spill cost = %7.0f.", |
duke@435 | 2334 | _final_load_cost*4.0 + _final_store_cost * 2.0 + |
duke@435 | 2335 | _final_copy_cost*1.0 + _final_memove_cost*12.0); |
duke@435 | 2336 | tty->print("Conservatively coalesced %d copies, %d pairs", |
duke@435 | 2337 | _conserv_coalesce, _conserv_coalesce_pair); |
duke@435 | 2338 | if( _conserv_coalesce_trie || _conserv_coalesce_quad ) |
duke@435 | 2339 | tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); |
duke@435 | 2340 | tty->print_cr(", %d post alloc.", _post_alloc); |
duke@435 | 2341 | if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) |
duke@435 | 2342 | tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", |
duke@435 | 2343 | _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); |
duke@435 | 2344 | if( _used_cisc_instructions || _unused_cisc_instructions ) |
duke@435 | 2345 | tty->print_cr("Used cisc instruction %d, remained in register %d", |
duke@435 | 2346 | _used_cisc_instructions, _unused_cisc_instructions); |
duke@435 | 2347 | if( _allocator_successes != 0 ) |
duke@435 | 2348 | tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); |
duke@435 | 2349 | tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); |
duke@435 | 2350 | } |
duke@435 | 2351 | #endif // not PRODUCT |