Wed, 18 Sep 2013 14:34:56 -0700
8024342: PPC64 (part 111): Support for C calling conventions that require 64-bit ints.
Summary: Some platforms, as ppc and s390x/zArch require that 32-bit ints are passed as 64-bit values to C functions. This change adds support to adapt the signature and to issue proper casts to c2-compiled stubs. The functions are used in generate_native_wrapper(). Adapt signature used by the compiler as in PhaseIdealLoop::intrinsify_fill().
Reviewed-by: kvn
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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13 * accompanied this code).
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23 */
25 #include "precompiled.hpp"
26 #include "compiler/compileLog.hpp"
27 #include "compiler/oopMap.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/block.hpp"
31 #include "opto/callnode.hpp"
32 #include "opto/cfgnode.hpp"
33 #include "opto/chaitin.hpp"
34 #include "opto/coalesce.hpp"
35 #include "opto/connode.hpp"
36 #include "opto/idealGraphPrinter.hpp"
37 #include "opto/indexSet.hpp"
38 #include "opto/machnode.hpp"
39 #include "opto/memnode.hpp"
40 #include "opto/opcodes.hpp"
41 #include "opto/rootnode.hpp"
43 #ifndef PRODUCT
44 void LRG::dump() const {
45 ttyLocker ttyl;
46 tty->print("%d ",num_regs());
47 _mask.dump();
48 if( _msize_valid ) {
49 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
50 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
51 } else {
52 tty->print(", #?(%d) ",_mask.Size());
53 }
55 tty->print("EffDeg: ");
56 if( _degree_valid ) tty->print( "%d ", _eff_degree );
57 else tty->print("? ");
59 if( is_multidef() ) {
60 tty->print("MultiDef ");
61 if (_defs != NULL) {
62 tty->print("(");
63 for (int i = 0; i < _defs->length(); i++) {
64 tty->print("N%d ", _defs->at(i)->_idx);
65 }
66 tty->print(") ");
67 }
68 }
69 else if( _def == 0 ) tty->print("Dead ");
70 else tty->print("Def: N%d ",_def->_idx);
72 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
73 // Flags
74 if( _is_oop ) tty->print("Oop ");
75 if( _is_float ) tty->print("Float ");
76 if( _is_vector ) tty->print("Vector ");
77 if( _was_spilled1 ) tty->print("Spilled ");
78 if( _was_spilled2 ) tty->print("Spilled2 ");
79 if( _direct_conflict ) tty->print("Direct_conflict ");
80 if( _fat_proj ) tty->print("Fat ");
81 if( _was_lo ) tty->print("Lo ");
82 if( _has_copy ) tty->print("Copy ");
83 if( _at_risk ) tty->print("Risk ");
85 if( _must_spill ) tty->print("Must_spill ");
86 if( _is_bound ) tty->print("Bound ");
87 if( _msize_valid ) {
88 if( _degree_valid && lo_degree() ) tty->print("Trivial ");
89 }
91 tty->cr();
92 }
93 #endif
95 // Compute score from cost and area. Low score is best to spill.
96 static double raw_score( double cost, double area ) {
97 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
98 }
100 double LRG::score() const {
101 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
102 // Bigger area lowers score, encourages spilling this live range.
103 // Bigger cost raise score, prevents spilling this live range.
104 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
105 // to turn a divide by a constant into a multiply by the reciprical).
106 double score = raw_score( _cost, _area);
108 // Account for area. Basically, LRGs covering large areas are better
109 // to spill because more other LRGs get freed up.
110 if( _area == 0.0 ) // No area? Then no progress to spill
111 return 1e35;
113 if( _was_spilled2 ) // If spilled once before, we are unlikely
114 return score + 1e30; // to make progress again.
116 if( _cost >= _area*3.0 ) // Tiny area relative to cost
117 return score + 1e17; // Probably no progress to spill
119 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
120 return score + 1e10; // Likely no progress to spill
122 return score;
123 }
125 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
126 memset( _lidxs, 0, sizeof(uint)*max );
127 }
129 void LRG_List::extend( uint nidx, uint lidx ) {
130 _nesting.check();
131 if( nidx >= _max ) {
132 uint size = 16;
133 while( size <= nidx ) size <<=1;
134 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );
135 _max = size;
136 }
137 while( _cnt <= nidx )
138 _lidxs[_cnt++] = 0;
139 _lidxs[nidx] = lidx;
140 }
142 #define NUMBUCKS 3
144 // Straight out of Tarjan's union-find algorithm
145 uint LiveRangeMap::find_compress(uint lrg) {
146 uint cur = lrg;
147 uint next = _uf_map[cur];
148 while (next != cur) { // Scan chain of equivalences
149 assert( next < cur, "always union smaller");
150 cur = next; // until find a fixed-point
151 next = _uf_map[cur];
152 }
154 // Core of union-find algorithm: update chain of
155 // equivalences to be equal to the root.
156 while (lrg != next) {
157 uint tmp = _uf_map[lrg];
158 _uf_map.map(lrg, next);
159 lrg = tmp;
160 }
161 return lrg;
162 }
164 // Reset the Union-Find map to identity
165 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
166 _max_lrg_id= max_lrg_id;
167 // Force the Union-Find mapping to be at least this large
168 _uf_map.extend(_max_lrg_id, 0);
169 // Initialize it to be the ID mapping.
170 for (uint i = 0; i < _max_lrg_id; ++i) {
171 _uf_map.map(i, i);
172 }
173 }
175 // Make all Nodes map directly to their final live range; no need for
176 // the Union-Find mapping after this call.
177 void LiveRangeMap::compress_uf_map_for_nodes() {
178 // For all Nodes, compress mapping
179 uint unique = _names.Size();
180 for (uint i = 0; i < unique; ++i) {
181 uint lrg = _names[i];
182 uint compressed_lrg = find(lrg);
183 if (lrg != compressed_lrg) {
184 _names.map(i, compressed_lrg);
185 }
186 }
187 }
189 // Like Find above, but no path compress, so bad asymptotic behavior
190 uint LiveRangeMap::find_const(uint lrg) const {
191 if (!lrg) {
192 return lrg; // Ignore the zero LRG
193 }
195 // Off the end? This happens during debugging dumps when you got
196 // brand new live ranges but have not told the allocator yet.
197 if (lrg >= _max_lrg_id) {
198 return lrg;
199 }
201 uint next = _uf_map[lrg];
202 while (next != lrg) { // Scan chain of equivalences
203 assert(next < lrg, "always union smaller");
204 lrg = next; // until find a fixed-point
205 next = _uf_map[lrg];
206 }
207 return next;
208 }
210 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
211 : PhaseRegAlloc(unique, cfg, matcher,
212 #ifndef PRODUCT
213 print_chaitin_statistics
214 #else
215 NULL
216 #endif
217 )
218 , _lrg_map(unique)
219 , _live(0)
220 , _spilled_once(Thread::current()->resource_area())
221 , _spilled_twice(Thread::current()->resource_area())
222 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
223 , _oldphi(unique)
224 #ifndef PRODUCT
225 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
226 #endif
227 {
228 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
230 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
232 // Build a list of basic blocks, sorted by frequency
233 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
234 // Experiment with sorting strategies to speed compilation
235 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
236 Block **buckets[NUMBUCKS]; // Array of buckets
237 uint buckcnt[NUMBUCKS]; // Array of bucket counters
238 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
239 for (uint i = 0; i < NUMBUCKS; i++) {
240 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
241 buckcnt[i] = 0;
242 // Bump by three orders of magnitude each time
243 cutoff *= 0.001;
244 buckval[i] = cutoff;
245 for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
246 buckets[i][j] = NULL;
247 }
248 }
249 // Sort blocks into buckets
250 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
251 for (uint j = 0; j < NUMBUCKS; j++) {
252 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
253 // Assign block to end of list for appropriate bucket
254 buckets[j][buckcnt[j]++] = _cfg.get_block(i);
255 break; // kick out of inner loop
256 }
257 }
258 }
259 // Dump buckets into final block array
260 uint blkcnt = 0;
261 for (uint i = 0; i < NUMBUCKS; i++) {
262 for (uint j = 0; j < buckcnt[i]; j++) {
263 _blks[blkcnt++] = buckets[i][j];
264 }
265 }
267 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
268 }
270 // union 2 sets together.
271 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
272 uint src = _lrg_map.find(src_n);
273 uint dst = _lrg_map.find(dst_n);
274 assert(src, "");
275 assert(dst, "");
276 assert(src < _lrg_map.max_lrg_id(), "oob");
277 assert(dst < _lrg_map.max_lrg_id(), "oob");
278 assert(src < dst, "always union smaller");
279 _lrg_map.uf_map(dst, src);
280 }
282 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
283 // Make the Node->LRG mapping
284 _lrg_map.extend(x->_idx,lrg);
285 // Make the Union-Find mapping an identity function
286 _lrg_map.uf_extend(lrg, lrg);
287 }
290 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
291 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
292 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
293 int found_projs = 0;
294 uint cnt = orig->outcnt();
295 for (uint i = 0; i < cnt; i++) {
296 Node* proj = orig->raw_out(i);
297 if (proj->is_MachProj()) {
298 assert(proj->outcnt() == 0, "only kill projections are expected here");
299 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
300 found_projs++;
301 // Copy kill projections after the cloned node
302 Node* kills = proj->clone();
303 kills->set_req(0, copy);
304 b->_nodes.insert(idx++, kills);
305 _cfg.map_node_to_block(kills, b);
306 new_lrg(kills, max_lrg_id++);
307 }
308 }
309 return found_projs;
310 }
312 // Renumber the live ranges to compact them. Makes the IFG smaller.
313 void PhaseChaitin::compact() {
314 // Current the _uf_map contains a series of short chains which are headed
315 // by a self-cycle. All the chains run from big numbers to little numbers.
316 // The Find() call chases the chains & shortens them for the next Find call.
317 // We are going to change this structure slightly. Numbers above a moving
318 // wave 'i' are unchanged. Numbers below 'j' point directly to their
319 // compacted live range with no further chaining. There are no chains or
320 // cycles below 'i', so the Find call no longer works.
321 uint j=1;
322 uint i;
323 for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
324 uint lr = _lrg_map.uf_live_range_id(i);
325 // Ignore unallocated live ranges
326 if (!lr) {
327 continue;
328 }
329 assert(lr <= i, "");
330 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
331 }
332 // Now change the Node->LR mapping to reflect the compacted names
333 uint unique = _lrg_map.size();
334 for (i = 0; i < unique; i++) {
335 uint lrg_id = _lrg_map.live_range_id(i);
336 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
337 }
339 // Reset the Union-Find mapping
340 _lrg_map.reset_uf_map(j);
341 }
343 void PhaseChaitin::Register_Allocate() {
345 // Above the OLD FP (and in registers) are the incoming arguments. Stack
346 // slots in this area are called "arg_slots". Above the NEW FP (and in
347 // registers) is the outgoing argument area; above that is the spill/temp
348 // area. These are all "frame_slots". Arg_slots start at the zero
349 // stack_slots and count up to the known arg_size. Frame_slots start at
350 // the stack_slot #arg_size and go up. After allocation I map stack
351 // slots to actual offsets. Stack-slots in the arg_slot area are biased
352 // by the frame_size; stack-slots in the frame_slot area are biased by 0.
354 _trip_cnt = 0;
355 _alternate = 0;
356 _matcher._allocation_started = true;
358 ResourceArea split_arena; // Arena for Split local resources
359 ResourceArea live_arena; // Arena for liveness & IFG info
360 ResourceMark rm(&live_arena);
362 // Need live-ness for the IFG; need the IFG for coalescing. If the
363 // liveness is JUST for coalescing, then I can get some mileage by renaming
364 // all copy-related live ranges low and then using the max copy-related
365 // live range as a cut-off for LIVE and the IFG. In other words, I can
366 // build a subset of LIVE and IFG just for copies.
367 PhaseLive live(_cfg, _lrg_map.names(), &live_arena);
369 // Need IFG for coalescing and coloring
370 PhaseIFG ifg(&live_arena);
371 _ifg = &ifg;
373 // Come out of SSA world to the Named world. Assign (virtual) registers to
374 // Nodes. Use the same register for all inputs and the output of PhiNodes
375 // - effectively ending SSA form. This requires either coalescing live
376 // ranges or inserting copies. For the moment, we insert "virtual copies"
377 // - we pretend there is a copy prior to each Phi in predecessor blocks.
378 // We will attempt to coalesce such "virtual copies" before we manifest
379 // them for real.
380 de_ssa();
382 #ifdef ASSERT
383 // Veify the graph before RA.
384 verify(&live_arena);
385 #endif
387 {
388 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
389 _live = NULL; // Mark live as being not available
390 rm.reset_to_mark(); // Reclaim working storage
391 IndexSet::reset_memory(C, &live_arena);
392 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
393 gather_lrg_masks( false ); // Collect LRG masks
394 live.compute(_lrg_map.max_lrg_id()); // Compute liveness
395 _live = &live; // Mark LIVE as being available
396 }
398 // Base pointers are currently "used" by instructions which define new
399 // derived pointers. This makes base pointers live up to the where the
400 // derived pointer is made, but not beyond. Really, they need to be live
401 // across any GC point where the derived value is live. So this code looks
402 // at all the GC points, and "stretches" the live range of any base pointer
403 // to the GC point.
404 if (stretch_base_pointer_live_ranges(&live_arena)) {
405 NOT_PRODUCT(Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler);)
406 // Since some live range stretched, I need to recompute live
407 _live = NULL;
408 rm.reset_to_mark(); // Reclaim working storage
409 IndexSet::reset_memory(C, &live_arena);
410 ifg.init(_lrg_map.max_lrg_id());
411 gather_lrg_masks(false);
412 live.compute(_lrg_map.max_lrg_id());
413 _live = &live;
414 }
415 // Create the interference graph using virtual copies
416 build_ifg_virtual(); // Include stack slots this time
418 // Aggressive (but pessimistic) copy coalescing.
419 // This pass works on virtual copies. Any virtual copies which are not
420 // coalesced get manifested as actual copies
421 {
422 // The IFG is/was triangular. I am 'squaring it up' so Union can run
423 // faster. Union requires a 'for all' operation which is slow on the
424 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
425 // meaning I can visit all the Nodes neighbors less than a Node in time
426 // O(# of neighbors), but I have to visit all the Nodes greater than a
427 // given Node and search them for an instance, i.e., time O(#MaxLRG)).
428 _ifg->SquareUp();
430 PhaseAggressiveCoalesce coalesce(*this);
431 coalesce.coalesce_driver();
432 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
433 // not match the Phi itself, insert a copy.
434 coalesce.insert_copies(_matcher);
435 if (C->failing()) {
436 return;
437 }
438 }
440 // After aggressive coalesce, attempt a first cut at coloring.
441 // To color, we need the IFG and for that we need LIVE.
442 {
443 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
444 _live = NULL;
445 rm.reset_to_mark(); // Reclaim working storage
446 IndexSet::reset_memory(C, &live_arena);
447 ifg.init(_lrg_map.max_lrg_id());
448 gather_lrg_masks( true );
449 live.compute(_lrg_map.max_lrg_id());
450 _live = &live;
451 }
453 // Build physical interference graph
454 uint must_spill = 0;
455 must_spill = build_ifg_physical(&live_arena);
456 // If we have a guaranteed spill, might as well spill now
457 if (must_spill) {
458 if(!_lrg_map.max_lrg_id()) {
459 return;
460 }
461 // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
462 C->check_node_count(10*must_spill, "out of nodes before split");
463 if (C->failing()) {
464 return;
465 }
467 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
468 _lrg_map.set_max_lrg_id(new_max_lrg_id);
469 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
470 // or we failed to split
471 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
472 if (C->failing()) {
473 return;
474 }
476 NOT_PRODUCT(C->verify_graph_edges();)
478 compact(); // Compact LRGs; return new lower max lrg
480 {
481 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
482 _live = NULL;
483 rm.reset_to_mark(); // Reclaim working storage
484 IndexSet::reset_memory(C, &live_arena);
485 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
486 gather_lrg_masks( true ); // Collect intersect mask
487 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
488 _live = &live;
489 }
490 build_ifg_physical(&live_arena);
491 _ifg->SquareUp();
492 _ifg->Compute_Effective_Degree();
493 // Only do conservative coalescing if requested
494 if (OptoCoalesce) {
495 // Conservative (and pessimistic) copy coalescing of those spills
496 PhaseConservativeCoalesce coalesce(*this);
497 // If max live ranges greater than cutoff, don't color the stack.
498 // This cutoff can be larger than below since it is only done once.
499 coalesce.coalesce_driver();
500 }
501 _lrg_map.compress_uf_map_for_nodes();
503 #ifdef ASSERT
504 verify(&live_arena, true);
505 #endif
506 } else {
507 ifg.SquareUp();
508 ifg.Compute_Effective_Degree();
509 #ifdef ASSERT
510 set_was_low();
511 #endif
512 }
514 // Prepare for Simplify & Select
515 cache_lrg_info(); // Count degree of LRGs
517 // Simplify the InterFerence Graph by removing LRGs of low degree.
518 // LRGs of low degree are trivially colorable.
519 Simplify();
521 // Select colors by re-inserting LRGs back into the IFG in reverse order.
522 // Return whether or not something spills.
523 uint spills = Select( );
525 // If we spill, split and recycle the entire thing
526 while( spills ) {
527 if( _trip_cnt++ > 24 ) {
528 DEBUG_ONLY( dump_for_spill_split_recycle(); )
529 if( _trip_cnt > 27 ) {
530 C->record_method_not_compilable("failed spill-split-recycle sanity check");
531 return;
532 }
533 }
535 if (!_lrg_map.max_lrg_id()) {
536 return;
537 }
538 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
539 _lrg_map.set_max_lrg_id(new_max_lrg_id);
540 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
541 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
542 if (C->failing()) {
543 return;
544 }
546 compact(); // Compact LRGs; return new lower max lrg
548 // Nuke the live-ness and interference graph and LiveRanGe info
549 {
550 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
551 _live = NULL;
552 rm.reset_to_mark(); // Reclaim working storage
553 IndexSet::reset_memory(C, &live_arena);
554 ifg.init(_lrg_map.max_lrg_id());
556 // Create LiveRanGe array.
557 // Intersect register masks for all USEs and DEFs
558 gather_lrg_masks(true);
559 live.compute(_lrg_map.max_lrg_id());
560 _live = &live;
561 }
562 must_spill = build_ifg_physical(&live_arena);
563 _ifg->SquareUp();
564 _ifg->Compute_Effective_Degree();
566 // Only do conservative coalescing if requested
567 if (OptoCoalesce) {
568 // Conservative (and pessimistic) copy coalescing
569 PhaseConservativeCoalesce coalesce(*this);
570 // Check for few live ranges determines how aggressive coalesce is.
571 coalesce.coalesce_driver();
572 }
573 _lrg_map.compress_uf_map_for_nodes();
574 #ifdef ASSERT
575 verify(&live_arena, true);
576 #endif
577 cache_lrg_info(); // Count degree of LRGs
579 // Simplify the InterFerence Graph by removing LRGs of low degree.
580 // LRGs of low degree are trivially colorable.
581 Simplify();
583 // Select colors by re-inserting LRGs back into the IFG in reverse order.
584 // Return whether or not something spills.
585 spills = Select();
586 }
588 // Count number of Simplify-Select trips per coloring success.
589 _allocator_attempts += _trip_cnt + 1;
590 _allocator_successes += 1;
592 // Peephole remove copies
593 post_allocate_copy_removal();
595 #ifdef ASSERT
596 // Veify the graph after RA.
597 verify(&live_arena);
598 #endif
600 // max_reg is past the largest *register* used.
601 // Convert that to a frame_slot number.
602 if (_max_reg <= _matcher._new_SP) {
603 _framesize = C->out_preserve_stack_slots();
604 }
605 else {
606 _framesize = _max_reg -_matcher._new_SP;
607 }
608 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
610 // This frame must preserve the required fp alignment
611 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
612 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
613 #ifndef PRODUCT
614 _total_framesize += _framesize;
615 if ((int)_framesize > _max_framesize) {
616 _max_framesize = _framesize;
617 }
618 #endif
620 // Convert CISC spills
621 fixup_spills();
623 // Log regalloc results
624 CompileLog* log = Compile::current()->log();
625 if (log != NULL) {
626 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
627 }
629 if (C->failing()) {
630 return;
631 }
633 NOT_PRODUCT(C->verify_graph_edges();)
635 // Move important info out of the live_arena to longer lasting storage.
636 alloc_node_regs(_lrg_map.size());
637 for (uint i=0; i < _lrg_map.size(); i++) {
638 if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
639 LRG &lrg = lrgs(_lrg_map.live_range_id(i));
640 if (!lrg.alive()) {
641 set_bad(i);
642 } else if (lrg.num_regs() == 1) {
643 set1(i, lrg.reg());
644 } else { // Must be a register-set
645 if (!lrg._fat_proj) { // Must be aligned adjacent register set
646 // Live ranges record the highest register in their mask.
647 // We want the low register for the AD file writer's convenience.
648 OptoReg::Name hi = lrg.reg(); // Get hi register
649 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
650 // We have to use pair [lo,lo+1] even for wide vectors because
651 // the rest of code generation works only with pairs. It is safe
652 // since for registers encoding only 'lo' is used.
653 // Second reg from pair is used in ScheduleAndBundle on SPARC where
654 // vector max size is 8 which corresponds to registers pair.
655 // It is also used in BuildOopMaps but oop operations are not
656 // vectorized.
657 set2(i, lo);
658 } else { // Misaligned; extract 2 bits
659 OptoReg::Name hi = lrg.reg(); // Get hi register
660 lrg.Remove(hi); // Yank from mask
661 int lo = lrg.mask().find_first_elem(); // Find lo
662 set_pair(i, hi, lo);
663 }
664 }
665 if( lrg._is_oop ) _node_oops.set(i);
666 } else {
667 set_bad(i);
668 }
669 }
671 // Done!
672 _live = NULL;
673 _ifg = NULL;
674 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
675 }
677 void PhaseChaitin::de_ssa() {
678 // Set initial Names for all Nodes. Most Nodes get the virtual register
679 // number. A few get the ZERO live range number. These do not
680 // get allocated, but instead rely on correct scheduling to ensure that
681 // only one instance is simultaneously live at a time.
682 uint lr_counter = 1;
683 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
684 Block* block = _cfg.get_block(i);
685 uint cnt = block->_nodes.size();
687 // Handle all the normal Nodes in the block
688 for( uint j = 0; j < cnt; j++ ) {
689 Node *n = block->_nodes[j];
690 // Pre-color to the zero live range, or pick virtual register
691 const RegMask &rm = n->out_RegMask();
692 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
693 }
694 }
695 // Reset the Union-Find mapping to be identity
696 _lrg_map.reset_uf_map(lr_counter);
697 }
700 // Gather LiveRanGe information, including register masks. Modification of
701 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
702 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
704 // Nail down the frame pointer live range
705 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
706 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
708 // For all blocks
709 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
710 Block* block = _cfg.get_block(i);
712 // For all instructions
713 for (uint j = 1; j < block->_nodes.size(); j++) {
714 Node* n = block->_nodes[j];
715 uint input_edge_start =1; // Skip control most nodes
716 if (n->is_Mach()) {
717 input_edge_start = n->as_Mach()->oper_input_base();
718 }
719 uint idx = n->is_Copy();
721 // Get virtual register number, same as LiveRanGe index
722 uint vreg = _lrg_map.live_range_id(n);
723 LRG& lrg = lrgs(vreg);
724 if (vreg) { // No vreg means un-allocable (e.g. memory)
726 // Collect has-copy bit
727 if (idx) {
728 lrg._has_copy = 1;
729 uint clidx = _lrg_map.live_range_id(n->in(idx));
730 LRG& copy_src = lrgs(clidx);
731 copy_src._has_copy = 1;
732 }
734 // Check for float-vs-int live range (used in register-pressure
735 // calculations)
736 const Type *n_type = n->bottom_type();
737 if (n_type->is_floatingpoint()) {
738 lrg._is_float = 1;
739 }
741 // Check for twice prior spilling. Once prior spilling might have
742 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
743 // further spilling is unlikely to make progress.
744 if (_spilled_once.test(n->_idx)) {
745 lrg._was_spilled1 = 1;
746 if (_spilled_twice.test(n->_idx)) {
747 lrg._was_spilled2 = 1;
748 }
749 }
751 #ifndef PRODUCT
752 if (trace_spilling() && lrg._def != NULL) {
753 // collect defs for MultiDef printing
754 if (lrg._defs == NULL) {
755 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
756 lrg._defs->append(lrg._def);
757 }
758 lrg._defs->append(n);
759 }
760 #endif
762 // Check for a single def LRG; these can spill nicely
763 // via rematerialization. Flag as NULL for no def found
764 // yet, or 'n' for single def or -1 for many defs.
765 lrg._def = lrg._def ? NodeSentinel : n;
767 // Limit result register mask to acceptable registers
768 const RegMask &rm = n->out_RegMask();
769 lrg.AND( rm );
771 int ireg = n->ideal_reg();
772 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
773 "oops must be in Op_RegP's" );
775 // Check for vector live range (only if vector register is used).
776 // On SPARC vector uses RegD which could be misaligned so it is not
777 // processes as vector in RA.
778 if (RegMask::is_vector(ireg))
779 lrg._is_vector = 1;
780 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
781 "vector must be in vector registers");
783 // Check for bound register masks
784 const RegMask &lrgmask = lrg.mask();
785 if (lrgmask.is_bound(ireg)) {
786 lrg._is_bound = 1;
787 }
789 // Check for maximum frequency value
790 if (lrg._maxfreq < block->_freq) {
791 lrg._maxfreq = block->_freq;
792 }
794 // Check for oop-iness, or long/double
795 // Check for multi-kill projection
796 switch (ireg) {
797 case MachProjNode::fat_proj:
798 // Fat projections have size equal to number of registers killed
799 lrg.set_num_regs(rm.Size());
800 lrg.set_reg_pressure(lrg.num_regs());
801 lrg._fat_proj = 1;
802 lrg._is_bound = 1;
803 break;
804 case Op_RegP:
805 #ifdef _LP64
806 lrg.set_num_regs(2); // Size is 2 stack words
807 #else
808 lrg.set_num_regs(1); // Size is 1 stack word
809 #endif
810 // Register pressure is tracked relative to the maximum values
811 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
812 // and relative to other types which compete for the same regs.
813 //
814 // The following table contains suggested values based on the
815 // architectures as defined in each .ad file.
816 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
817 // compile-speed or performance.
818 // Note1:
819 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
820 // since .ad registers are defined as high and low halves.
821 // These reg_pressure values remain compatible with the code
822 // in is_high_pressure() which relates get_invalid_mask_size(),
823 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
824 // Note2:
825 // SPARC -d32 has 24 registers available for integral values,
826 // but only 10 of these are safe for 64-bit longs.
827 // Using set_reg_pressure(2) for both int and long means
828 // the allocator will believe it can fit 26 longs into
829 // registers. Using 2 for longs and 1 for ints means the
830 // allocator will attempt to put 52 integers into registers.
831 // The settings below limit this problem to methods with
832 // many long values which are being run on 32-bit SPARC.
833 //
834 // ------------------- reg_pressure --------------------
835 // Each entry is reg_pressure_per_value,number_of_regs
836 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
837 // IA32 2 1 1 1 1 6 6
838 // IA64 1 1 1 1 1 50 41
839 // SPARC 2 2 2 2 2 48 (24) 52 (26)
840 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
841 // AMD64 1 1 1 1 1 14 15
842 // -----------------------------------------------------
843 #if defined(SPARC)
844 lrg.set_reg_pressure(2); // use for v9 as well
845 #else
846 lrg.set_reg_pressure(1); // normally one value per register
847 #endif
848 if( n_type->isa_oop_ptr() ) {
849 lrg._is_oop = 1;
850 }
851 break;
852 case Op_RegL: // Check for long or double
853 case Op_RegD:
854 lrg.set_num_regs(2);
855 // Define platform specific register pressure
856 #if defined(SPARC) || defined(ARM)
857 lrg.set_reg_pressure(2);
858 #elif defined(IA32)
859 if( ireg == Op_RegL ) {
860 lrg.set_reg_pressure(2);
861 } else {
862 lrg.set_reg_pressure(1);
863 }
864 #else
865 lrg.set_reg_pressure(1); // normally one value per register
866 #endif
867 // If this def of a double forces a mis-aligned double,
868 // flag as '_fat_proj' - really flag as allowing misalignment
869 // AND changes how we count interferences. A mis-aligned
870 // double can interfere with TWO aligned pairs, or effectively
871 // FOUR registers!
872 if (rm.is_misaligned_pair()) {
873 lrg._fat_proj = 1;
874 lrg._is_bound = 1;
875 }
876 break;
877 case Op_RegF:
878 case Op_RegI:
879 case Op_RegN:
880 case Op_RegFlags:
881 case 0: // not an ideal register
882 lrg.set_num_regs(1);
883 #ifdef SPARC
884 lrg.set_reg_pressure(2);
885 #else
886 lrg.set_reg_pressure(1);
887 #endif
888 break;
889 case Op_VecS:
890 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
891 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
892 lrg.set_num_regs(RegMask::SlotsPerVecS);
893 lrg.set_reg_pressure(1);
894 break;
895 case Op_VecD:
896 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
897 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
898 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
899 lrg.set_num_regs(RegMask::SlotsPerVecD);
900 lrg.set_reg_pressure(1);
901 break;
902 case Op_VecX:
903 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
904 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
905 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
906 lrg.set_num_regs(RegMask::SlotsPerVecX);
907 lrg.set_reg_pressure(1);
908 break;
909 case Op_VecY:
910 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
911 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
912 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
913 lrg.set_num_regs(RegMask::SlotsPerVecY);
914 lrg.set_reg_pressure(1);
915 break;
916 default:
917 ShouldNotReachHere();
918 }
919 }
921 // Now do the same for inputs
922 uint cnt = n->req();
923 // Setup for CISC SPILLING
924 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
925 if( UseCISCSpill && after_aggressive ) {
926 inp = n->cisc_operand();
927 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
928 // Convert operand number to edge index number
929 inp = n->as_Mach()->operand_index(inp);
930 }
931 // Prepare register mask for each input
932 for( uint k = input_edge_start; k < cnt; k++ ) {
933 uint vreg = _lrg_map.live_range_id(n->in(k));
934 if (!vreg) {
935 continue;
936 }
938 // If this instruction is CISC Spillable, add the flags
939 // bit to its appropriate input
940 if( UseCISCSpill && after_aggressive && inp == k ) {
941 #ifndef PRODUCT
942 if( TraceCISCSpill ) {
943 tty->print(" use_cisc_RegMask: ");
944 n->dump();
945 }
946 #endif
947 n->as_Mach()->use_cisc_RegMask();
948 }
950 LRG &lrg = lrgs(vreg);
951 // // Testing for floating point code shape
952 // Node *test = n->in(k);
953 // if( test->is_Mach() ) {
954 // MachNode *m = test->as_Mach();
955 // int op = m->ideal_Opcode();
956 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
957 // int zzz = 1;
958 // }
959 // }
961 // Limit result register mask to acceptable registers.
962 // Do not limit registers from uncommon uses before
963 // AggressiveCoalesce. This effectively pre-virtual-splits
964 // around uncommon uses of common defs.
965 const RegMask &rm = n->in_RegMask(k);
966 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
967 // Since we are BEFORE aggressive coalesce, leave the register
968 // mask untrimmed by the call. This encourages more coalescing.
969 // Later, AFTER aggressive, this live range will have to spill
970 // but the spiller handles slow-path calls very nicely.
971 } else {
972 lrg.AND( rm );
973 }
975 // Check for bound register masks
976 const RegMask &lrgmask = lrg.mask();
977 int kreg = n->in(k)->ideal_reg();
978 bool is_vect = RegMask::is_vector(kreg);
979 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
980 is_vect || kreg == Op_RegD,
981 "vector must be in vector registers");
982 if (lrgmask.is_bound(kreg))
983 lrg._is_bound = 1;
985 // If this use of a double forces a mis-aligned double,
986 // flag as '_fat_proj' - really flag as allowing misalignment
987 // AND changes how we count interferences. A mis-aligned
988 // double can interfere with TWO aligned pairs, or effectively
989 // FOUR registers!
990 #ifdef ASSERT
991 if (is_vect) {
992 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
993 assert(!lrg._fat_proj, "sanity");
994 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
995 }
996 #endif
997 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
998 lrg._fat_proj = 1;
999 lrg._is_bound = 1;
1000 }
1001 // if the LRG is an unaligned pair, we will have to spill
1002 // so clear the LRG's register mask if it is not already spilled
1003 if (!is_vect && !n->is_SpillCopy() &&
1004 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1005 lrgmask.is_misaligned_pair()) {
1006 lrg.Clear();
1007 }
1009 // Check for maximum frequency value
1010 if (lrg._maxfreq < block->_freq) {
1011 lrg._maxfreq = block->_freq;
1012 }
1014 } // End for all allocated inputs
1015 } // end for all instructions
1016 } // end for all blocks
1018 // Final per-liverange setup
1019 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1020 LRG &lrg = lrgs(i2);
1021 assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1022 if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1023 lrg.clear_to_sets();
1024 }
1025 lrg.compute_set_mask_size();
1026 if (lrg.not_free()) { // Handle case where we lose from the start
1027 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1028 lrg._direct_conflict = 1;
1029 }
1030 lrg.set_degree(0); // no neighbors in IFG yet
1031 }
1032 }
1034 // Set the was-lo-degree bit. Conservative coalescing should not change the
1035 // colorability of the graph. If any live range was of low-degree before
1036 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
1037 // The bit is checked in Simplify.
1038 void PhaseChaitin::set_was_low() {
1039 #ifdef ASSERT
1040 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1041 int size = lrgs(i).num_regs();
1042 uint old_was_lo = lrgs(i)._was_lo;
1043 lrgs(i)._was_lo = 0;
1044 if( lrgs(i).lo_degree() ) {
1045 lrgs(i)._was_lo = 1; // Trivially of low degree
1046 } else { // Else check the Brigg's assertion
1047 // Brigg's observation is that the lo-degree neighbors of a
1048 // hi-degree live range will not interfere with the color choices
1049 // of said hi-degree live range. The Simplify reverse-stack-coloring
1050 // order takes care of the details. Hence you do not have to count
1051 // low-degree neighbors when determining if this guy colors.
1052 int briggs_degree = 0;
1053 IndexSet *s = _ifg->neighbors(i);
1054 IndexSetIterator elements(s);
1055 uint lidx;
1056 while((lidx = elements.next()) != 0) {
1057 if( !lrgs(lidx).lo_degree() )
1058 briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1059 }
1060 if( briggs_degree < lrgs(i).degrees_of_freedom() )
1061 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
1062 }
1063 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1064 }
1065 #endif
1066 }
1068 #define REGISTER_CONSTRAINED 16
1070 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
1071 void PhaseChaitin::cache_lrg_info( ) {
1073 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1074 LRG &lrg = lrgs(i);
1076 // Check for being of low degree: means we can be trivially colored.
1077 // Low degree, dead or must-spill guys just get to simplify right away
1078 if( lrg.lo_degree() ||
1079 !lrg.alive() ||
1080 lrg._must_spill ) {
1081 // Split low degree list into those guys that must get a
1082 // register and those that can go to register or stack.
1083 // The idea is LRGs that can go register or stack color first when
1084 // they have a good chance of getting a register. The register-only
1085 // lo-degree live ranges always get a register.
1086 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1087 if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1088 lrg._next = _lo_stk_degree;
1089 _lo_stk_degree = i;
1090 } else {
1091 lrg._next = _lo_degree;
1092 _lo_degree = i;
1093 }
1094 } else { // Else high degree
1095 lrgs(_hi_degree)._prev = i;
1096 lrg._next = _hi_degree;
1097 lrg._prev = 0;
1098 _hi_degree = i;
1099 }
1100 }
1101 }
1103 // Simplify the IFG by removing LRGs of low degree that have NO copies
1104 void PhaseChaitin::Pre_Simplify( ) {
1106 // Warm up the lo-degree no-copy list
1107 int lo_no_copy = 0;
1108 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1109 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1110 !lrgs(i).alive() ||
1111 lrgs(i)._must_spill) {
1112 lrgs(i)._next = lo_no_copy;
1113 lo_no_copy = i;
1114 }
1115 }
1117 while( lo_no_copy ) {
1118 uint lo = lo_no_copy;
1119 lo_no_copy = lrgs(lo)._next;
1120 int size = lrgs(lo).num_regs();
1122 // Put the simplified guy on the simplified list.
1123 lrgs(lo)._next = _simplified;
1124 _simplified = lo;
1126 // Yank this guy from the IFG.
1127 IndexSet *adj = _ifg->remove_node( lo );
1129 // If any neighbors' degrees fall below their number of
1130 // allowed registers, then put that neighbor on the low degree
1131 // list. Note that 'degree' can only fall and 'numregs' is
1132 // unchanged by this action. Thus the two are equal at most once,
1133 // so LRGs hit the lo-degree worklists at most once.
1134 IndexSetIterator elements(adj);
1135 uint neighbor;
1136 while ((neighbor = elements.next()) != 0) {
1137 LRG *n = &lrgs(neighbor);
1138 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1140 // Check for just becoming of-low-degree
1141 if( n->just_lo_degree() && !n->_has_copy ) {
1142 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1143 // Put on lo-degree list
1144 n->_next = lo_no_copy;
1145 lo_no_copy = neighbor;
1146 }
1147 }
1148 } // End of while lo-degree no_copy worklist not empty
1150 // No more lo-degree no-copy live ranges to simplify
1151 }
1153 // Simplify the IFG by removing LRGs of low degree.
1154 void PhaseChaitin::Simplify( ) {
1156 while( 1 ) { // Repeat till simplified it all
1157 // May want to explore simplifying lo_degree before _lo_stk_degree.
1158 // This might result in more spills coloring into registers during
1159 // Select().
1160 while( _lo_degree || _lo_stk_degree ) {
1161 // If possible, pull from lo_stk first
1162 uint lo;
1163 if( _lo_degree ) {
1164 lo = _lo_degree;
1165 _lo_degree = lrgs(lo)._next;
1166 } else {
1167 lo = _lo_stk_degree;
1168 _lo_stk_degree = lrgs(lo)._next;
1169 }
1171 // Put the simplified guy on the simplified list.
1172 lrgs(lo)._next = _simplified;
1173 _simplified = lo;
1174 // If this guy is "at risk" then mark his current neighbors
1175 if( lrgs(lo)._at_risk ) {
1176 IndexSetIterator elements(_ifg->neighbors(lo));
1177 uint datum;
1178 while ((datum = elements.next()) != 0) {
1179 lrgs(datum)._risk_bias = lo;
1180 }
1181 }
1183 // Yank this guy from the IFG.
1184 IndexSet *adj = _ifg->remove_node( lo );
1186 // If any neighbors' degrees fall below their number of
1187 // allowed registers, then put that neighbor on the low degree
1188 // list. Note that 'degree' can only fall and 'numregs' is
1189 // unchanged by this action. Thus the two are equal at most once,
1190 // so LRGs hit the lo-degree worklist at most once.
1191 IndexSetIterator elements(adj);
1192 uint neighbor;
1193 while ((neighbor = elements.next()) != 0) {
1194 LRG *n = &lrgs(neighbor);
1195 #ifdef ASSERT
1196 if( VerifyOpto || VerifyRegisterAllocator ) {
1197 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1198 }
1199 #endif
1201 // Check for just becoming of-low-degree just counting registers.
1202 // _must_spill live ranges are already on the low degree list.
1203 if( n->just_lo_degree() && !n->_must_spill ) {
1204 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1205 // Pull from hi-degree list
1206 uint prev = n->_prev;
1207 uint next = n->_next;
1208 if( prev ) lrgs(prev)._next = next;
1209 else _hi_degree = next;
1210 lrgs(next)._prev = prev;
1211 n->_next = _lo_degree;
1212 _lo_degree = neighbor;
1213 }
1214 }
1215 } // End of while lo-degree/lo_stk_degree worklist not empty
1217 // Check for got everything: is hi-degree list empty?
1218 if( !_hi_degree ) break;
1220 // Time to pick a potential spill guy
1221 uint lo_score = _hi_degree;
1222 double score = lrgs(lo_score).score();
1223 double area = lrgs(lo_score)._area;
1224 double cost = lrgs(lo_score)._cost;
1225 bool bound = lrgs(lo_score)._is_bound;
1227 // Find cheapest guy
1228 debug_only( int lo_no_simplify=0; );
1229 for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1230 assert( !(*_ifg->_yanked)[i], "" );
1231 // It's just vaguely possible to move hi-degree to lo-degree without
1232 // going through a just-lo-degree stage: If you remove a double from
1233 // a float live range it's degree will drop by 2 and you can skip the
1234 // just-lo-degree stage. It's very rare (shows up after 5000+ methods
1235 // in -Xcomp of Java2Demo). So just choose this guy to simplify next.
1236 if( lrgs(i).lo_degree() ) {
1237 lo_score = i;
1238 break;
1239 }
1240 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1241 double iscore = lrgs(i).score();
1242 double iarea = lrgs(i)._area;
1243 double icost = lrgs(i)._cost;
1244 bool ibound = lrgs(i)._is_bound;
1246 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
1247 // wins. Ties happen because all live ranges in question have spilled
1248 // a few times before and the spill-score adds a huge number which
1249 // washes out the low order bits. We are choosing the lesser of 2
1250 // evils; in this case pick largest area to spill.
1251 // Ties also happen when live ranges are defined and used only inside
1252 // one block. In which case their area is 0 and score set to max.
1253 // In such case choose bound live range over unbound to free registers
1254 // or with smaller cost to spill.
1255 if( iscore < score ||
1256 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1257 (iscore == score && iarea == area &&
1258 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1259 lo_score = i;
1260 score = iscore;
1261 area = iarea;
1262 cost = icost;
1263 bound = ibound;
1264 }
1265 }
1266 LRG *lo_lrg = &lrgs(lo_score);
1267 // The live range we choose for spilling is either hi-degree, or very
1268 // rarely it can be low-degree. If we choose a hi-degree live range
1269 // there better not be any lo-degree choices.
1270 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1272 // Pull from hi-degree list
1273 uint prev = lo_lrg->_prev;
1274 uint next = lo_lrg->_next;
1275 if( prev ) lrgs(prev)._next = next;
1276 else _hi_degree = next;
1277 lrgs(next)._prev = prev;
1278 // Jam him on the lo-degree list, despite his high degree.
1279 // Maybe he'll get a color, and maybe he'll spill.
1280 // Only Select() will know.
1281 lrgs(lo_score)._at_risk = true;
1282 _lo_degree = lo_score;
1283 lo_lrg->_next = 0;
1285 } // End of while not simplified everything
1287 }
1289 // Is 'reg' register legal for 'lrg'?
1290 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1291 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1292 lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1293 // RA uses OptoReg which represent the highest element of a registers set.
1294 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1295 // in which XMMd is used by RA to represent such vectors. A double value
1296 // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1297 // The register mask uses largest bits set of overlapping register sets.
1298 // On x86 with AVX it uses 8 bits for each XMM registers set.
1299 //
1300 // The 'lrg' already has cleared-to-set register mask (done in Select()
1301 // before calling choose_color()). Passing mask.Member(reg) check above
1302 // indicates that the size (num_regs) of 'reg' set is less or equal to
1303 // 'lrg' set size.
1304 // For set size 1 any register which is member of 'lrg' mask is legal.
1305 if (lrg.num_regs()==1)
1306 return true;
1307 // For larger sets only an aligned register with the same set size is legal.
1308 int mask = lrg.num_regs()-1;
1309 if ((reg&mask) == mask)
1310 return true;
1311 }
1312 return false;
1313 }
1315 // Choose a color using the biasing heuristic
1316 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1318 // Check for "at_risk" LRG's
1319 uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1320 if( risk_lrg != 0 ) {
1321 // Walk the colored neighbors of the "at_risk" candidate
1322 // Choose a color which is both legal and already taken by a neighbor
1323 // of the "at_risk" candidate in order to improve the chances of the
1324 // "at_risk" candidate of coloring
1325 IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1326 uint datum;
1327 while ((datum = elements.next()) != 0) {
1328 OptoReg::Name reg = lrgs(datum).reg();
1329 // If this LRG's register is legal for us, choose it
1330 if (is_legal_reg(lrg, reg, chunk))
1331 return reg;
1332 }
1333 }
1335 uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1336 if( copy_lrg != 0 ) {
1337 // If he has a color,
1338 if( !(*(_ifg->_yanked))[copy_lrg] ) {
1339 OptoReg::Name reg = lrgs(copy_lrg).reg();
1340 // And it is legal for you,
1341 if (is_legal_reg(lrg, reg, chunk))
1342 return reg;
1343 } else if( chunk == 0 ) {
1344 // Choose a color which is legal for him
1345 RegMask tempmask = lrg.mask();
1346 tempmask.AND(lrgs(copy_lrg).mask());
1347 tempmask.clear_to_sets(lrg.num_regs());
1348 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1349 if (OptoReg::is_valid(reg))
1350 return reg;
1351 }
1352 }
1354 // If no bias info exists, just go with the register selection ordering
1355 if (lrg._is_vector || lrg.num_regs() == 2) {
1356 // Find an aligned set
1357 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1358 }
1360 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1361 // copy removal to remove many more copies, by preventing a just-assigned
1362 // register from being repeatedly assigned.
1363 OptoReg::Name reg = lrg.mask().find_first_elem();
1364 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1365 // This 'Remove; find; Insert' idiom is an expensive way to find the
1366 // SECOND element in the mask.
1367 lrg.Remove(reg);
1368 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1369 lrg.Insert(reg);
1370 if( OptoReg::is_reg(reg2))
1371 reg = reg2;
1372 }
1373 return OptoReg::add( reg, chunk );
1374 }
1376 // Choose a color in the current chunk
1377 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1378 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1379 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1381 if( lrg.num_regs() == 1 || // Common Case
1382 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1383 // Use a heuristic to "bias" the color choice
1384 return bias_color(lrg, chunk);
1386 assert(!lrg._is_vector, "should be not vector here" );
1387 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1389 // Fat-proj case or misaligned double argument.
1390 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1391 lrg.num_regs() == 2,"fat projs exactly color" );
1392 assert( !chunk, "always color in 1st chunk" );
1393 // Return the highest element in the set.
1394 return lrg.mask().find_last_elem();
1395 }
1397 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1398 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1399 // everything going back is guaranteed a color. Select that color. If some
1400 // hi-degree LRG cannot get a color then we record that we must spill.
1401 uint PhaseChaitin::Select( ) {
1402 uint spill_reg = LRG::SPILL_REG;
1403 _max_reg = OptoReg::Name(0); // Past max register used
1404 while( _simplified ) {
1405 // Pull next LRG from the simplified list - in reverse order of removal
1406 uint lidx = _simplified;
1407 LRG *lrg = &lrgs(lidx);
1408 _simplified = lrg->_next;
1411 #ifndef PRODUCT
1412 if (trace_spilling()) {
1413 ttyLocker ttyl;
1414 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1415 lrg->degrees_of_freedom());
1416 lrg->dump();
1417 }
1418 #endif
1420 // Re-insert into the IFG
1421 _ifg->re_insert(lidx);
1422 if( !lrg->alive() ) continue;
1423 // capture allstackedness flag before mask is hacked
1424 const int is_allstack = lrg->mask().is_AllStack();
1426 // Yeah, yeah, yeah, I know, I know. I can refactor this
1427 // to avoid the GOTO, although the refactored code will not
1428 // be much clearer. We arrive here IFF we have a stack-based
1429 // live range that cannot color in the current chunk, and it
1430 // has to move into the next free stack chunk.
1431 int chunk = 0; // Current chunk is first chunk
1432 retry_next_chunk:
1434 // Remove neighbor colors
1435 IndexSet *s = _ifg->neighbors(lidx);
1437 debug_only(RegMask orig_mask = lrg->mask();)
1438 IndexSetIterator elements(s);
1439 uint neighbor;
1440 while ((neighbor = elements.next()) != 0) {
1441 // Note that neighbor might be a spill_reg. In this case, exclusion
1442 // of its color will be a no-op, since the spill_reg chunk is in outer
1443 // space. Also, if neighbor is in a different chunk, this exclusion
1444 // will be a no-op. (Later on, if lrg runs out of possible colors in
1445 // its chunk, a new chunk of color may be tried, in which case
1446 // examination of neighbors is started again, at retry_next_chunk.)
1447 LRG &nlrg = lrgs(neighbor);
1448 OptoReg::Name nreg = nlrg.reg();
1449 // Only subtract masks in the same chunk
1450 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1451 #ifndef PRODUCT
1452 uint size = lrg->mask().Size();
1453 RegMask rm = lrg->mask();
1454 #endif
1455 lrg->SUBTRACT(nlrg.mask());
1456 #ifndef PRODUCT
1457 if (trace_spilling() && lrg->mask().Size() != size) {
1458 ttyLocker ttyl;
1459 tty->print("L%d ", lidx);
1460 rm.dump();
1461 tty->print(" intersected L%d ", neighbor);
1462 nlrg.mask().dump();
1463 tty->print(" removed ");
1464 rm.SUBTRACT(lrg->mask());
1465 rm.dump();
1466 tty->print(" leaving ");
1467 lrg->mask().dump();
1468 tty->cr();
1469 }
1470 #endif
1471 }
1472 }
1473 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1474 // Aligned pairs need aligned masks
1475 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1476 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1477 lrg->clear_to_sets();
1478 }
1480 // Check if a color is available and if so pick the color
1481 OptoReg::Name reg = choose_color( *lrg, chunk );
1482 #ifdef SPARC
1483 debug_only(lrg->compute_set_mask_size());
1484 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1485 #endif
1487 //---------------
1488 // If we fail to color and the AllStack flag is set, trigger
1489 // a chunk-rollover event
1490 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1491 // Bump register mask up to next stack chunk
1492 chunk += RegMask::CHUNK_SIZE;
1493 lrg->Set_All();
1495 goto retry_next_chunk;
1496 }
1498 //---------------
1499 // Did we get a color?
1500 else if( OptoReg::is_valid(reg)) {
1501 #ifndef PRODUCT
1502 RegMask avail_rm = lrg->mask();
1503 #endif
1505 // Record selected register
1506 lrg->set_reg(reg);
1508 if( reg >= _max_reg ) // Compute max register limit
1509 _max_reg = OptoReg::add(reg,1);
1510 // Fold reg back into normal space
1511 reg = OptoReg::add(reg,-chunk);
1513 // If the live range is not bound, then we actually had some choices
1514 // to make. In this case, the mask has more bits in it than the colors
1515 // chosen. Restrict the mask to just what was picked.
1516 int n_regs = lrg->num_regs();
1517 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1518 if (n_regs == 1 || !lrg->_fat_proj) {
1519 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1520 lrg->Clear(); // Clear the mask
1521 lrg->Insert(reg); // Set regmask to match selected reg
1522 // For vectors and pairs, also insert the low bit of the pair
1523 for (int i = 1; i < n_regs; i++)
1524 lrg->Insert(OptoReg::add(reg,-i));
1525 lrg->set_mask_size(n_regs);
1526 } else { // Else fatproj
1527 // mask must be equal to fatproj bits, by definition
1528 }
1529 #ifndef PRODUCT
1530 if (trace_spilling()) {
1531 ttyLocker ttyl;
1532 tty->print("L%d selected ", lidx);
1533 lrg->mask().dump();
1534 tty->print(" from ");
1535 avail_rm.dump();
1536 tty->cr();
1537 }
1538 #endif
1539 // Note that reg is the highest-numbered register in the newly-bound mask.
1540 } // end color available case
1542 //---------------
1543 // Live range is live and no colors available
1544 else {
1545 assert( lrg->alive(), "" );
1546 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1547 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1548 assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1550 // Assign the special spillreg register
1551 lrg->set_reg(OptoReg::Name(spill_reg++));
1552 // Do not empty the regmask; leave mask_size lying around
1553 // for use during Spilling
1554 #ifndef PRODUCT
1555 if( trace_spilling() ) {
1556 ttyLocker ttyl;
1557 tty->print("L%d spilling with neighbors: ", lidx);
1558 s->dump();
1559 debug_only(tty->print(" original mask: "));
1560 debug_only(orig_mask.dump());
1561 dump_lrg(lidx);
1562 }
1563 #endif
1564 } // end spill case
1566 }
1568 return spill_reg-LRG::SPILL_REG; // Return number of spills
1569 }
1571 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1572 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1573 if( _spilled_once.test(src->_idx) ) {
1574 _spilled_once.set(dst->_idx);
1575 lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1576 if( _spilled_twice.test(src->_idx) ) {
1577 _spilled_twice.set(dst->_idx);
1578 lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1579 }
1580 }
1581 }
1583 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1584 void PhaseChaitin::set_was_spilled( Node *n ) {
1585 if( _spilled_once.test_set(n->_idx) )
1586 _spilled_twice.set(n->_idx);
1587 }
1589 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1590 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1591 void PhaseChaitin::fixup_spills() {
1592 // This function does only cisc spill work.
1593 if( !UseCISCSpill ) return;
1595 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
1597 // Grab the Frame Pointer
1598 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1600 // For all blocks
1601 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1602 Block* block = _cfg.get_block(i);
1604 // For all instructions in block
1605 uint last_inst = block->end_idx();
1606 for (uint j = 1; j <= last_inst; j++) {
1607 Node* n = block->_nodes[j];
1609 // Dead instruction???
1610 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1611 C->top() == n || // Or the random TOP node
1612 n->is_Proj(), // Or a fat-proj kill node
1613 "No dead instructions after post-alloc" );
1615 int inp = n->cisc_operand();
1616 if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1617 // Convert operand number to edge index number
1618 MachNode *mach = n->as_Mach();
1619 inp = mach->operand_index(inp);
1620 Node *src = n->in(inp); // Value to load or store
1621 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1622 OptoReg::Name src_reg = lrg_cisc.reg();
1623 // Doubles record the HIGH register of an adjacent pair.
1624 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1625 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1626 // This is a CISC Spill, get stack offset and construct new node
1627 #ifndef PRODUCT
1628 if( TraceCISCSpill ) {
1629 tty->print(" reg-instr: ");
1630 n->dump();
1631 }
1632 #endif
1633 int stk_offset = reg2offset(src_reg);
1634 // Bailout if we might exceed node limit when spilling this instruction
1635 C->check_node_count(0, "out of nodes fixing spills");
1636 if (C->failing()) return;
1637 // Transform node
1638 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1639 cisc->set_req(inp,fp); // Base register is frame pointer
1640 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1641 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1642 cisc->ins_req(1,src); // Requires a memory edge
1643 }
1644 block->_nodes.map(j,cisc); // Insert into basic block
1645 n->subsume_by(cisc, C); // Correct graph
1646 //
1647 ++_used_cisc_instructions;
1648 #ifndef PRODUCT
1649 if( TraceCISCSpill ) {
1650 tty->print(" cisc-instr: ");
1651 cisc->dump();
1652 }
1653 #endif
1654 } else {
1655 #ifndef PRODUCT
1656 if( TraceCISCSpill ) {
1657 tty->print(" using reg-instr: ");
1658 n->dump();
1659 }
1660 #endif
1661 ++_unused_cisc_instructions; // input can be on stack
1662 }
1663 }
1665 } // End of for all instructions
1667 } // End of for all blocks
1668 }
1670 // Helper to stretch above; recursively discover the base Node for a
1671 // given derived Node. Easy for AddP-related machine nodes, but needs
1672 // to be recursive for derived Phis.
1673 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1674 // See if already computed; if so return it
1675 if( derived_base_map[derived->_idx] )
1676 return derived_base_map[derived->_idx];
1678 // See if this happens to be a base.
1679 // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1680 // pointers derived from NULL! These are always along paths that
1681 // can't happen at run-time but the optimizer cannot deduce it so
1682 // we have to handle it gracefully.
1683 assert(!derived->bottom_type()->isa_narrowoop() ||
1684 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1685 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1686 // If its an OOP with a non-zero offset, then it is derived.
1687 if( tj == NULL || tj->_offset == 0 ) {
1688 derived_base_map[derived->_idx] = derived;
1689 return derived;
1690 }
1691 // Derived is NULL+offset? Base is NULL!
1692 if( derived->is_Con() ) {
1693 Node *base = _matcher.mach_null();
1694 assert(base != NULL, "sanity");
1695 if (base->in(0) == NULL) {
1696 // Initialize it once and make it shared:
1697 // set control to _root and place it into Start block
1698 // (where top() node is placed).
1699 base->init_req(0, _cfg.get_root_node());
1700 Block *startb = _cfg.get_block_for_node(C->top());
1701 startb->_nodes.insert(startb->find_node(C->top()), base );
1702 _cfg.map_node_to_block(base, startb);
1703 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1704 }
1705 if (_lrg_map.live_range_id(base) == 0) {
1706 new_lrg(base, maxlrg++);
1707 }
1708 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1709 derived_base_map[derived->_idx] = base;
1710 return base;
1711 }
1713 // Check for AddP-related opcodes
1714 if (!derived->is_Phi()) {
1715 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1716 Node *base = derived->in(AddPNode::Base);
1717 derived_base_map[derived->_idx] = base;
1718 return base;
1719 }
1721 // Recursively find bases for Phis.
1722 // First check to see if we can avoid a base Phi here.
1723 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1724 uint i;
1725 for( i = 2; i < derived->req(); i++ )
1726 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1727 break;
1728 // Went to the end without finding any different bases?
1729 if( i == derived->req() ) { // No need for a base Phi here
1730 derived_base_map[derived->_idx] = base;
1731 return base;
1732 }
1734 // Now we see we need a base-Phi here to merge the bases
1735 const Type *t = base->bottom_type();
1736 base = new (C) PhiNode( derived->in(0), t );
1737 for( i = 1; i < derived->req(); i++ ) {
1738 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1739 t = t->meet(base->in(i)->bottom_type());
1740 }
1741 base->as_Phi()->set_type(t);
1743 // Search the current block for an existing base-Phi
1744 Block *b = _cfg.get_block_for_node(derived);
1745 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1746 Node *phi = b->_nodes[i];
1747 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1748 b->_nodes.insert( i, base ); // Must insert created Phi here as base
1749 _cfg.map_node_to_block(base, b);
1750 new_lrg(base,maxlrg++);
1751 break;
1752 }
1753 // See if Phi matches.
1754 uint j;
1755 for( j = 1; j < base->req(); j++ )
1756 if( phi->in(j) != base->in(j) &&
1757 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1758 break;
1759 if( j == base->req() ) { // All inputs match?
1760 base = phi; // Then use existing 'phi' and drop 'base'
1761 break;
1762 }
1763 }
1766 // Cache info for later passes
1767 derived_base_map[derived->_idx] = base;
1768 return base;
1769 }
1771 // At each Safepoint, insert extra debug edges for each pair of derived value/
1772 // base pointer that is live across the Safepoint for oopmap building. The
1773 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1774 // required edge set.
1775 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1776 int must_recompute_live = false;
1777 uint maxlrg = _lrg_map.max_lrg_id();
1778 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1779 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1781 // For all blocks in RPO do...
1782 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1783 Block* block = _cfg.get_block(i);
1784 // Note use of deep-copy constructor. I cannot hammer the original
1785 // liveout bits, because they are needed by the following coalesce pass.
1786 IndexSet liveout(_live->live(block));
1788 for (uint j = block->end_idx() + 1; j > 1; j--) {
1789 Node* n = block->_nodes[j - 1];
1791 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1792 // like to see in the same register. Compare uses the loop-phi and so
1793 // extends its live range BUT cannot be part of the cycle. If this
1794 // extended live range overlaps with the update of the loop-phi value
1795 // we need both alive at the same time -- which requires at least 1
1796 // copy. But because Intel has only 2-address registers we end up with
1797 // at least 2 copies, one before the loop-phi update instruction and
1798 // one after. Instead we split the input to the compare just after the
1799 // phi.
1800 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1801 Node *phi = n->in(1);
1802 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1803 Block *phi_block = _cfg.get_block_for_node(phi);
1804 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1805 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1806 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1807 insert_proj( phi_block, 1, spill, maxlrg++ );
1808 n->set_req(1,spill);
1809 must_recompute_live = true;
1810 }
1811 }
1812 }
1814 // Get value being defined
1815 uint lidx = _lrg_map.live_range_id(n);
1816 // Ignore the occasional brand-new live range
1817 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1818 // Remove from live-out set
1819 liveout.remove(lidx);
1821 // Copies do not define a new value and so do not interfere.
1822 // Remove the copies source from the liveout set before interfering.
1823 uint idx = n->is_Copy();
1824 if (idx) {
1825 liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1826 }
1827 }
1829 // Found a safepoint?
1830 JVMState *jvms = n->jvms();
1831 if( jvms ) {
1832 // Now scan for a live derived pointer
1833 IndexSetIterator elements(&liveout);
1834 uint neighbor;
1835 while ((neighbor = elements.next()) != 0) {
1836 // Find reaching DEF for base and derived values
1837 // This works because we are still in SSA during this call.
1838 Node *derived = lrgs(neighbor)._def;
1839 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1840 assert(!derived->bottom_type()->isa_narrowoop() ||
1841 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1842 // If its an OOP with a non-zero offset, then it is derived.
1843 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1844 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1845 assert(base->_idx < _lrg_map.size(), "");
1846 // Add reaching DEFs of derived pointer and base pointer as a
1847 // pair of inputs
1848 n->add_req(derived);
1849 n->add_req(base);
1851 // See if the base pointer is already live to this point.
1852 // Since I'm working on the SSA form, live-ness amounts to
1853 // reaching def's. So if I find the base's live range then
1854 // I know the base's def reaches here.
1855 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1856 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1857 (_lrg_map.live_range_id(base) > 0) && // not a constant
1858 _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1859 // Base pointer is not currently live. Since I stretched
1860 // the base pointer to here and it crosses basic-block
1861 // boundaries, the global live info is now incorrect.
1862 // Recompute live.
1863 must_recompute_live = true;
1864 } // End of if base pointer is not live to debug info
1865 }
1866 } // End of scan all live data for derived ptrs crossing GC point
1867 } // End of if found a GC point
1869 // Make all inputs live
1870 if (!n->is_Phi()) { // Phi function uses come from prior block
1871 for (uint k = 1; k < n->req(); k++) {
1872 uint lidx = _lrg_map.live_range_id(n->in(k));
1873 if (lidx < _lrg_map.max_lrg_id()) {
1874 liveout.insert(lidx);
1875 }
1876 }
1877 }
1879 } // End of forall instructions in block
1880 liveout.clear(); // Free the memory used by liveout.
1882 } // End of forall blocks
1883 _lrg_map.set_max_lrg_id(maxlrg);
1885 // If I created a new live range I need to recompute live
1886 if (maxlrg != _ifg->_maxlrg) {
1887 must_recompute_live = true;
1888 }
1890 return must_recompute_live != 0;
1891 }
1893 // Extend the node to LRG mapping
1895 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1896 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1897 }
1899 #ifndef PRODUCT
1900 void PhaseChaitin::dump(const Node *n) const {
1901 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1902 tty->print("L%d",r);
1903 if (r && n->Opcode() != Op_Phi) {
1904 if( _node_regs ) { // Got a post-allocation copy of allocation?
1905 tty->print("[");
1906 OptoReg::Name second = get_reg_second(n);
1907 if( OptoReg::is_valid(second) ) {
1908 if( OptoReg::is_reg(second) )
1909 tty->print("%s:",Matcher::regName[second]);
1910 else
1911 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1912 }
1913 OptoReg::Name first = get_reg_first(n);
1914 if( OptoReg::is_reg(first) )
1915 tty->print("%s]",Matcher::regName[first]);
1916 else
1917 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1918 } else
1919 n->out_RegMask().dump();
1920 }
1921 tty->print("/N%d\t",n->_idx);
1922 tty->print("%s === ", n->Name());
1923 uint k;
1924 for (k = 0; k < n->req(); k++) {
1925 Node *m = n->in(k);
1926 if (!m) {
1927 tty->print("_ ");
1928 }
1929 else {
1930 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1931 tty->print("L%d",r);
1932 // Data MultiNode's can have projections with no real registers.
1933 // Don't die while dumping them.
1934 int op = n->Opcode();
1935 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1936 if( _node_regs ) {
1937 tty->print("[");
1938 OptoReg::Name second = get_reg_second(n->in(k));
1939 if( OptoReg::is_valid(second) ) {
1940 if( OptoReg::is_reg(second) )
1941 tty->print("%s:",Matcher::regName[second]);
1942 else
1943 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1944 reg2offset_unchecked(second));
1945 }
1946 OptoReg::Name first = get_reg_first(n->in(k));
1947 if( OptoReg::is_reg(first) )
1948 tty->print("%s]",Matcher::regName[first]);
1949 else
1950 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1951 reg2offset_unchecked(first));
1952 } else
1953 n->in_RegMask(k).dump();
1954 }
1955 tty->print("/N%d ",m->_idx);
1956 }
1957 }
1958 if( k < n->len() && n->in(k) ) tty->print("| ");
1959 for( ; k < n->len(); k++ ) {
1960 Node *m = n->in(k);
1961 if(!m) {
1962 break;
1963 }
1964 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1965 tty->print("L%d",r);
1966 tty->print("/N%d ",m->_idx);
1967 }
1968 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1969 else n->dump_spec(tty);
1970 if( _spilled_once.test(n->_idx ) ) {
1971 tty->print(" Spill_1");
1972 if( _spilled_twice.test(n->_idx ) )
1973 tty->print(" Spill_2");
1974 }
1975 tty->print("\n");
1976 }
1978 void PhaseChaitin::dump(const Block *b) const {
1979 b->dump_head(&_cfg);
1981 // For all instructions
1982 for( uint j = 0; j < b->_nodes.size(); j++ )
1983 dump(b->_nodes[j]);
1984 // Print live-out info at end of block
1985 if( _live ) {
1986 tty->print("Liveout: ");
1987 IndexSet *live = _live->live(b);
1988 IndexSetIterator elements(live);
1989 tty->print("{");
1990 uint i;
1991 while ((i = elements.next()) != 0) {
1992 tty->print("L%d ", _lrg_map.find_const(i));
1993 }
1994 tty->print_cr("}");
1995 }
1996 tty->print("\n");
1997 }
1999 void PhaseChaitin::dump() const {
2000 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
2001 _matcher._new_SP, _framesize );
2003 // For all blocks
2004 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2005 dump(_cfg.get_block(i));
2006 }
2007 // End of per-block dump
2008 tty->print("\n");
2010 if (!_ifg) {
2011 tty->print("(No IFG.)\n");
2012 return;
2013 }
2015 // Dump LRG array
2016 tty->print("--- Live RanGe Array ---\n");
2017 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2018 tty->print("L%d: ",i2);
2019 if (i2 < _ifg->_maxlrg) {
2020 lrgs(i2).dump();
2021 }
2022 else {
2023 tty->print_cr("new LRG");
2024 }
2025 }
2026 tty->print_cr("");
2028 // Dump lo-degree list
2029 tty->print("Lo degree: ");
2030 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2031 tty->print("L%d ",i3);
2032 tty->print_cr("");
2034 // Dump lo-stk-degree list
2035 tty->print("Lo stk degree: ");
2036 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2037 tty->print("L%d ",i4);
2038 tty->print_cr("");
2040 // Dump lo-degree list
2041 tty->print("Hi degree: ");
2042 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2043 tty->print("L%d ",i5);
2044 tty->print_cr("");
2045 }
2047 void PhaseChaitin::dump_degree_lists() const {
2048 // Dump lo-degree list
2049 tty->print("Lo degree: ");
2050 for( uint i = _lo_degree; i; i = lrgs(i)._next )
2051 tty->print("L%d ",i);
2052 tty->print_cr("");
2054 // Dump lo-stk-degree list
2055 tty->print("Lo stk degree: ");
2056 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2057 tty->print("L%d ",i2);
2058 tty->print_cr("");
2060 // Dump lo-degree list
2061 tty->print("Hi degree: ");
2062 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2063 tty->print("L%d ",i3);
2064 tty->print_cr("");
2065 }
2067 void PhaseChaitin::dump_simplified() const {
2068 tty->print("Simplified: ");
2069 for( uint i = _simplified; i; i = lrgs(i)._next )
2070 tty->print("L%d ",i);
2071 tty->print_cr("");
2072 }
2074 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2075 if ((int)reg < 0)
2076 sprintf(buf, "<OptoReg::%d>", (int)reg);
2077 else if (OptoReg::is_reg(reg))
2078 strcpy(buf, Matcher::regName[reg]);
2079 else
2080 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2081 pc->reg2offset(reg));
2082 return buf+strlen(buf);
2083 }
2085 // Dump a register name into a buffer. Be intelligent if we get called
2086 // before allocation is complete.
2087 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
2088 if( !this ) { // Not got anything?
2089 sprintf(buf,"N%d",n->_idx); // Then use Node index
2090 } else if( _node_regs ) {
2091 // Post allocation, use direct mappings, no LRG info available
2092 print_reg( get_reg_first(n), this, buf );
2093 } else {
2094 uint lidx = _lrg_map.find_const(n); // Grab LRG number
2095 if( !_ifg ) {
2096 sprintf(buf,"L%d",lidx); // No register binding yet
2097 } else if( !lidx ) { // Special, not allocated value
2098 strcpy(buf,"Special");
2099 } else {
2100 if (lrgs(lidx)._is_vector) {
2101 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2102 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2103 else
2104 sprintf(buf,"L%d",lidx); // No register binding yet
2105 } else if( (lrgs(lidx).num_regs() == 1)
2106 ? lrgs(lidx).mask().is_bound1()
2107 : lrgs(lidx).mask().is_bound_pair() ) {
2108 // Hah! We have a bound machine register
2109 print_reg( lrgs(lidx).reg(), this, buf );
2110 } else {
2111 sprintf(buf,"L%d",lidx); // No register binding yet
2112 }
2113 }
2114 }
2115 return buf+strlen(buf);
2116 }
2118 void PhaseChaitin::dump_for_spill_split_recycle() const {
2119 if( WizardMode && (PrintCompilation || PrintOpto) ) {
2120 // Display which live ranges need to be split and the allocator's state
2121 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2122 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2123 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2124 tty->print("L%d: ", bidx);
2125 lrgs(bidx).dump();
2126 }
2127 }
2128 tty->cr();
2129 dump();
2130 }
2131 }
2133 void PhaseChaitin::dump_frame() const {
2134 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2135 const TypeTuple *domain = C->tf()->domain();
2136 const int argcnt = domain->cnt() - TypeFunc::Parms;
2138 // Incoming arguments in registers dump
2139 for( int k = 0; k < argcnt; k++ ) {
2140 OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2141 if( OptoReg::is_reg(parmreg)) {
2142 const char *reg_name = OptoReg::regname(parmreg);
2143 tty->print("#r%3.3d %s", parmreg, reg_name);
2144 parmreg = _matcher._parm_regs[k].second();
2145 if( OptoReg::is_reg(parmreg)) {
2146 tty->print(":%s", OptoReg::regname(parmreg));
2147 }
2148 tty->print(" : parm %d: ", k);
2149 domain->field_at(k + TypeFunc::Parms)->dump();
2150 tty->print_cr("");
2151 }
2152 }
2154 // Check for un-owned padding above incoming args
2155 OptoReg::Name reg = _matcher._new_SP;
2156 if( reg > _matcher._in_arg_limit ) {
2157 reg = OptoReg::add(reg, -1);
2158 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2159 }
2161 // Incoming argument area dump
2162 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2163 while( reg > begin_in_arg ) {
2164 reg = OptoReg::add(reg, -1);
2165 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2166 int j;
2167 for( j = 0; j < argcnt; j++) {
2168 if( _matcher._parm_regs[j].first() == reg ||
2169 _matcher._parm_regs[j].second() == reg ) {
2170 tty->print("parm %d: ",j);
2171 domain->field_at(j + TypeFunc::Parms)->dump();
2172 tty->print_cr("");
2173 break;
2174 }
2175 }
2176 if( j >= argcnt )
2177 tty->print_cr("HOLE, owned by SELF");
2178 }
2180 // Old outgoing preserve area
2181 while( reg > _matcher._old_SP ) {
2182 reg = OptoReg::add(reg, -1);
2183 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2184 }
2186 // Old SP
2187 tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2188 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2190 // Preserve area dump
2191 int fixed_slots = C->fixed_slots();
2192 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2193 OptoReg::Name return_addr = _matcher.return_addr();
2195 reg = OptoReg::add(reg, -1);
2196 while (OptoReg::is_stack(reg)) {
2197 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2198 if (return_addr == reg) {
2199 tty->print_cr("return address");
2200 } else if (reg >= begin_in_preserve) {
2201 // Preserved slots are present on x86
2202 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2203 tty->print_cr("saved fp register");
2204 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2205 VerifyStackAtCalls)
2206 tty->print_cr("0xBADB100D +VerifyStackAtCalls");
2207 else
2208 tty->print_cr("in_preserve");
2209 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2210 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2211 } else {
2212 tty->print_cr("pad2, stack alignment");
2213 }
2214 reg = OptoReg::add(reg, -1);
2215 }
2217 // Spill area dump
2218 reg = OptoReg::add(_matcher._new_SP, _framesize );
2219 while( reg > _matcher._out_arg_limit ) {
2220 reg = OptoReg::add(reg, -1);
2221 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2222 }
2224 // Outgoing argument area dump
2225 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2226 reg = OptoReg::add(reg, -1);
2227 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2228 }
2230 // Outgoing new preserve area
2231 while( reg > _matcher._new_SP ) {
2232 reg = OptoReg::add(reg, -1);
2233 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2234 }
2235 tty->print_cr("#");
2236 }
2238 void PhaseChaitin::dump_bb( uint pre_order ) const {
2239 tty->print_cr("---dump of B%d---",pre_order);
2240 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2241 Block* block = _cfg.get_block(i);
2242 if (block->_pre_order == pre_order) {
2243 dump(block);
2244 }
2245 }
2246 }
2248 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2249 tty->print_cr("---dump of L%d---",lidx);
2251 if (_ifg) {
2252 if (lidx >= _lrg_map.max_lrg_id()) {
2253 tty->print("Attempt to print live range index beyond max live range.\n");
2254 return;
2255 }
2256 tty->print("L%d: ",lidx);
2257 if (lidx < _ifg->_maxlrg) {
2258 lrgs(lidx).dump();
2259 } else {
2260 tty->print_cr("new LRG");
2261 }
2262 }
2263 if( _ifg && lidx < _ifg->_maxlrg) {
2264 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2265 _ifg->neighbors(lidx)->dump();
2266 tty->cr();
2267 }
2268 // For all blocks
2269 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2270 Block* block = _cfg.get_block(i);
2271 int dump_once = 0;
2273 // For all instructions
2274 for( uint j = 0; j < block->_nodes.size(); j++ ) {
2275 Node *n = block->_nodes[j];
2276 if (_lrg_map.find_const(n) == lidx) {
2277 if (!dump_once++) {
2278 tty->cr();
2279 block->dump_head(&_cfg);
2280 }
2281 dump(n);
2282 continue;
2283 }
2284 if (!defs_only) {
2285 uint cnt = n->req();
2286 for( uint k = 1; k < cnt; k++ ) {
2287 Node *m = n->in(k);
2288 if (!m) {
2289 continue; // be robust in the dumper
2290 }
2291 if (_lrg_map.find_const(m) == lidx) {
2292 if (!dump_once++) {
2293 tty->cr();
2294 block->dump_head(&_cfg);
2295 }
2296 dump(n);
2297 }
2298 }
2299 }
2300 }
2301 } // End of per-block dump
2302 tty->cr();
2303 }
2304 #endif // not PRODUCT
2306 int PhaseChaitin::_final_loads = 0;
2307 int PhaseChaitin::_final_stores = 0;
2308 int PhaseChaitin::_final_memoves= 0;
2309 int PhaseChaitin::_final_copies = 0;
2310 double PhaseChaitin::_final_load_cost = 0;
2311 double PhaseChaitin::_final_store_cost = 0;
2312 double PhaseChaitin::_final_memove_cost= 0;
2313 double PhaseChaitin::_final_copy_cost = 0;
2314 int PhaseChaitin::_conserv_coalesce = 0;
2315 int PhaseChaitin::_conserv_coalesce_pair = 0;
2316 int PhaseChaitin::_conserv_coalesce_trie = 0;
2317 int PhaseChaitin::_conserv_coalesce_quad = 0;
2318 int PhaseChaitin::_post_alloc = 0;
2319 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2320 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2321 int PhaseChaitin::_used_cisc_instructions = 0;
2322 int PhaseChaitin::_unused_cisc_instructions = 0;
2323 int PhaseChaitin::_allocator_attempts = 0;
2324 int PhaseChaitin::_allocator_successes = 0;
2326 #ifndef PRODUCT
2327 uint PhaseChaitin::_high_pressure = 0;
2328 uint PhaseChaitin::_low_pressure = 0;
2330 void PhaseChaitin::print_chaitin_statistics() {
2331 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2332 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2333 tty->print_cr("Adjusted spill cost = %7.0f.",
2334 _final_load_cost*4.0 + _final_store_cost * 2.0 +
2335 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2336 tty->print("Conservatively coalesced %d copies, %d pairs",
2337 _conserv_coalesce, _conserv_coalesce_pair);
2338 if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2339 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2340 tty->print_cr(", %d post alloc.", _post_alloc);
2341 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2342 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2343 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2344 if( _used_cisc_instructions || _unused_cisc_instructions )
2345 tty->print_cr("Used cisc instruction %d, remained in register %d",
2346 _used_cisc_instructions, _unused_cisc_instructions);
2347 if( _allocator_successes != 0 )
2348 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2349 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2350 }
2351 #endif // not PRODUCT