Wed, 16 Feb 2011 13:30:31 -0800
7013964: openjdk LICENSE file needs rebranding
Reviewed-by: darcy, katleman, jjg
duke@435 | 1 | /* |
iveresov@2432 | 2 | * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "c1/c1_Compilation.hpp" |
stefank@2314 | 27 | #include "c1/c1_LIRAssembler.hpp" |
stefank@2314 | 28 | #include "c1/c1_MacroAssembler.hpp" |
stefank@2314 | 29 | #include "c1/c1_Runtime1.hpp" |
stefank@2314 | 30 | #include "c1/c1_ValueStack.hpp" |
stefank@2314 | 31 | #include "ci/ciArrayKlass.hpp" |
stefank@2314 | 32 | #include "ci/ciInstance.hpp" |
stefank@2314 | 33 | #include "gc_interface/collectedHeap.hpp" |
stefank@2314 | 34 | #include "memory/barrierSet.hpp" |
stefank@2314 | 35 | #include "memory/cardTableModRefBS.hpp" |
stefank@2314 | 36 | #include "nativeInst_x86.hpp" |
stefank@2314 | 37 | #include "oops/objArrayKlass.hpp" |
stefank@2314 | 38 | #include "runtime/sharedRuntime.hpp" |
duke@435 | 39 | |
duke@435 | 40 | |
duke@435 | 41 | // These masks are used to provide 128-bit aligned bitmasks to the XMM |
duke@435 | 42 | // instructions, to allow sign-masking or sign-bit flipping. They allow |
duke@435 | 43 | // fast versions of NegF/NegD and AbsF/AbsD. |
duke@435 | 44 | |
duke@435 | 45 | // Note: 'double' and 'long long' have 32-bits alignment on x86. |
duke@435 | 46 | static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { |
duke@435 | 47 | // Use the expression (adr)&(~0xF) to provide 128-bits aligned address |
duke@435 | 48 | // of 128-bits operands for SSE instructions. |
duke@435 | 49 | jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); |
duke@435 | 50 | // Store the value to a 128-bits operand. |
duke@435 | 51 | operand[0] = lo; |
duke@435 | 52 | operand[1] = hi; |
duke@435 | 53 | return operand; |
duke@435 | 54 | } |
duke@435 | 55 | |
duke@435 | 56 | // Buffer for 128-bits masks used by SSE instructions. |
duke@435 | 57 | static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) |
duke@435 | 58 | |
duke@435 | 59 | // Static initialization during VM startup. |
duke@435 | 60 | static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); |
duke@435 | 61 | static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); |
duke@435 | 62 | static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); |
duke@435 | 63 | static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); |
duke@435 | 64 | |
duke@435 | 65 | |
duke@435 | 66 | |
duke@435 | 67 | NEEDS_CLEANUP // remove this definitions ? |
duke@435 | 68 | const Register IC_Klass = rax; // where the IC klass is cached |
duke@435 | 69 | const Register SYNC_header = rax; // synchronization header |
duke@435 | 70 | const Register SHIFT_count = rcx; // where count for shift operations must be |
duke@435 | 71 | |
duke@435 | 72 | #define __ _masm-> |
duke@435 | 73 | |
duke@435 | 74 | |
duke@435 | 75 | static void select_different_registers(Register preserve, |
duke@435 | 76 | Register extra, |
duke@435 | 77 | Register &tmp1, |
duke@435 | 78 | Register &tmp2) { |
duke@435 | 79 | if (tmp1 == preserve) { |
duke@435 | 80 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 81 | tmp1 = extra; |
duke@435 | 82 | } else if (tmp2 == preserve) { |
duke@435 | 83 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 84 | tmp2 = extra; |
duke@435 | 85 | } |
duke@435 | 86 | assert_different_registers(preserve, tmp1, tmp2); |
duke@435 | 87 | } |
duke@435 | 88 | |
duke@435 | 89 | |
duke@435 | 90 | |
duke@435 | 91 | static void select_different_registers(Register preserve, |
duke@435 | 92 | Register extra, |
duke@435 | 93 | Register &tmp1, |
duke@435 | 94 | Register &tmp2, |
duke@435 | 95 | Register &tmp3) { |
duke@435 | 96 | if (tmp1 == preserve) { |
duke@435 | 97 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 98 | tmp1 = extra; |
duke@435 | 99 | } else if (tmp2 == preserve) { |
duke@435 | 100 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 101 | tmp2 = extra; |
duke@435 | 102 | } else if (tmp3 == preserve) { |
duke@435 | 103 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 104 | tmp3 = extra; |
duke@435 | 105 | } |
duke@435 | 106 | assert_different_registers(preserve, tmp1, tmp2, tmp3); |
duke@435 | 107 | } |
duke@435 | 108 | |
duke@435 | 109 | |
duke@435 | 110 | |
duke@435 | 111 | bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
duke@435 | 112 | if (opr->is_constant()) { |
duke@435 | 113 | LIR_Const* constant = opr->as_constant_ptr(); |
duke@435 | 114 | switch (constant->type()) { |
duke@435 | 115 | case T_INT: { |
duke@435 | 116 | return true; |
duke@435 | 117 | } |
duke@435 | 118 | |
duke@435 | 119 | default: |
duke@435 | 120 | return false; |
duke@435 | 121 | } |
duke@435 | 122 | } |
duke@435 | 123 | return false; |
duke@435 | 124 | } |
duke@435 | 125 | |
duke@435 | 126 | |
duke@435 | 127 | LIR_Opr LIR_Assembler::receiverOpr() { |
never@739 | 128 | return FrameMap::receiver_opr; |
duke@435 | 129 | } |
duke@435 | 130 | |
duke@435 | 131 | LIR_Opr LIR_Assembler::incomingReceiverOpr() { |
duke@435 | 132 | return receiverOpr(); |
duke@435 | 133 | } |
duke@435 | 134 | |
duke@435 | 135 | LIR_Opr LIR_Assembler::osrBufferPointer() { |
never@739 | 136 | return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
duke@435 | 137 | } |
duke@435 | 138 | |
duke@435 | 139 | //--------------fpu register translations----------------------- |
duke@435 | 140 | |
duke@435 | 141 | |
duke@435 | 142 | address LIR_Assembler::float_constant(float f) { |
duke@435 | 143 | address const_addr = __ float_constant(f); |
duke@435 | 144 | if (const_addr == NULL) { |
duke@435 | 145 | bailout("const section overflow"); |
duke@435 | 146 | return __ code()->consts()->start(); |
duke@435 | 147 | } else { |
duke@435 | 148 | return const_addr; |
duke@435 | 149 | } |
duke@435 | 150 | } |
duke@435 | 151 | |
duke@435 | 152 | |
duke@435 | 153 | address LIR_Assembler::double_constant(double d) { |
duke@435 | 154 | address const_addr = __ double_constant(d); |
duke@435 | 155 | if (const_addr == NULL) { |
duke@435 | 156 | bailout("const section overflow"); |
duke@435 | 157 | return __ code()->consts()->start(); |
duke@435 | 158 | } else { |
duke@435 | 159 | return const_addr; |
duke@435 | 160 | } |
duke@435 | 161 | } |
duke@435 | 162 | |
duke@435 | 163 | |
duke@435 | 164 | void LIR_Assembler::set_24bit_FPU() { |
duke@435 | 165 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
duke@435 | 166 | } |
duke@435 | 167 | |
duke@435 | 168 | void LIR_Assembler::reset_FPU() { |
duke@435 | 169 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 170 | } |
duke@435 | 171 | |
duke@435 | 172 | void LIR_Assembler::fpop() { |
duke@435 | 173 | __ fpop(); |
duke@435 | 174 | } |
duke@435 | 175 | |
duke@435 | 176 | void LIR_Assembler::fxch(int i) { |
duke@435 | 177 | __ fxch(i); |
duke@435 | 178 | } |
duke@435 | 179 | |
duke@435 | 180 | void LIR_Assembler::fld(int i) { |
duke@435 | 181 | __ fld_s(i); |
duke@435 | 182 | } |
duke@435 | 183 | |
duke@435 | 184 | void LIR_Assembler::ffree(int i) { |
duke@435 | 185 | __ ffree(i); |
duke@435 | 186 | } |
duke@435 | 187 | |
duke@435 | 188 | void LIR_Assembler::breakpoint() { |
duke@435 | 189 | __ int3(); |
duke@435 | 190 | } |
duke@435 | 191 | |
duke@435 | 192 | void LIR_Assembler::push(LIR_Opr opr) { |
duke@435 | 193 | if (opr->is_single_cpu()) { |
duke@435 | 194 | __ push_reg(opr->as_register()); |
duke@435 | 195 | } else if (opr->is_double_cpu()) { |
never@739 | 196 | NOT_LP64(__ push_reg(opr->as_register_hi())); |
duke@435 | 197 | __ push_reg(opr->as_register_lo()); |
duke@435 | 198 | } else if (opr->is_stack()) { |
duke@435 | 199 | __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); |
duke@435 | 200 | } else if (opr->is_constant()) { |
duke@435 | 201 | LIR_Const* const_opr = opr->as_constant_ptr(); |
duke@435 | 202 | if (const_opr->type() == T_OBJECT) { |
duke@435 | 203 | __ push_oop(const_opr->as_jobject()); |
duke@435 | 204 | } else if (const_opr->type() == T_INT) { |
duke@435 | 205 | __ push_jint(const_opr->as_jint()); |
duke@435 | 206 | } else { |
duke@435 | 207 | ShouldNotReachHere(); |
duke@435 | 208 | } |
duke@435 | 209 | |
duke@435 | 210 | } else { |
duke@435 | 211 | ShouldNotReachHere(); |
duke@435 | 212 | } |
duke@435 | 213 | } |
duke@435 | 214 | |
duke@435 | 215 | void LIR_Assembler::pop(LIR_Opr opr) { |
duke@435 | 216 | if (opr->is_single_cpu()) { |
never@739 | 217 | __ pop_reg(opr->as_register()); |
duke@435 | 218 | } else { |
duke@435 | 219 | ShouldNotReachHere(); |
duke@435 | 220 | } |
duke@435 | 221 | } |
duke@435 | 222 | |
never@739 | 223 | bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
never@739 | 224 | return addr->base()->is_illegal() && addr->index()->is_illegal(); |
never@739 | 225 | } |
never@739 | 226 | |
duke@435 | 227 | //------------------------------------------- |
never@739 | 228 | |
duke@435 | 229 | Address LIR_Assembler::as_Address(LIR_Address* addr) { |
never@739 | 230 | return as_Address(addr, rscratch1); |
never@739 | 231 | } |
never@739 | 232 | |
never@739 | 233 | Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { |
duke@435 | 234 | if (addr->base()->is_illegal()) { |
duke@435 | 235 | assert(addr->index()->is_illegal(), "must be illegal too"); |
never@739 | 236 | AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
never@739 | 237 | if (! __ reachable(laddr)) { |
never@739 | 238 | __ movptr(tmp, laddr.addr()); |
never@739 | 239 | Address res(tmp, 0); |
never@739 | 240 | return res; |
never@739 | 241 | } else { |
never@739 | 242 | return __ as_Address(laddr); |
never@739 | 243 | } |
duke@435 | 244 | } |
duke@435 | 245 | |
never@739 | 246 | Register base = addr->base()->as_pointer_register(); |
duke@435 | 247 | |
duke@435 | 248 | if (addr->index()->is_illegal()) { |
duke@435 | 249 | return Address( base, addr->disp()); |
never@739 | 250 | } else if (addr->index()->is_cpu_register()) { |
never@739 | 251 | Register index = addr->index()->as_pointer_register(); |
duke@435 | 252 | return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
duke@435 | 253 | } else if (addr->index()->is_constant()) { |
never@739 | 254 | intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
never@739 | 255 | assert(Assembler::is_simm32(addr_offset), "must be"); |
duke@435 | 256 | |
duke@435 | 257 | return Address(base, addr_offset); |
duke@435 | 258 | } else { |
duke@435 | 259 | Unimplemented(); |
duke@435 | 260 | return Address(); |
duke@435 | 261 | } |
duke@435 | 262 | } |
duke@435 | 263 | |
duke@435 | 264 | |
duke@435 | 265 | Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
duke@435 | 266 | Address base = as_Address(addr); |
duke@435 | 267 | return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); |
duke@435 | 268 | } |
duke@435 | 269 | |
duke@435 | 270 | |
duke@435 | 271 | Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
duke@435 | 272 | return as_Address(addr); |
duke@435 | 273 | } |
duke@435 | 274 | |
duke@435 | 275 | |
duke@435 | 276 | void LIR_Assembler::osr_entry() { |
duke@435 | 277 | offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
duke@435 | 278 | BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
duke@435 | 279 | ValueStack* entry_state = osr_entry->state(); |
duke@435 | 280 | int number_of_locks = entry_state->locks_size(); |
duke@435 | 281 | |
duke@435 | 282 | // we jump here if osr happens with the interpreter |
duke@435 | 283 | // state set up to continue at the beginning of the |
duke@435 | 284 | // loop that triggered osr - in particular, we have |
duke@435 | 285 | // the following registers setup: |
duke@435 | 286 | // |
duke@435 | 287 | // rcx: osr buffer |
duke@435 | 288 | // |
duke@435 | 289 | |
duke@435 | 290 | // build frame |
duke@435 | 291 | ciMethod* m = compilation()->method(); |
duke@435 | 292 | __ build_frame(initial_frame_size_in_bytes()); |
duke@435 | 293 | |
duke@435 | 294 | // OSR buffer is |
duke@435 | 295 | // |
duke@435 | 296 | // locals[nlocals-1..0] |
duke@435 | 297 | // monitors[0..number_of_locks] |
duke@435 | 298 | // |
duke@435 | 299 | // locals is a direct copy of the interpreter frame so in the osr buffer |
duke@435 | 300 | // so first slot in the local array is the last local from the interpreter |
duke@435 | 301 | // and last slot is local[0] (receiver) from the interpreter |
duke@435 | 302 | // |
duke@435 | 303 | // Similarly with locks. The first lock slot in the osr buffer is the nth lock |
duke@435 | 304 | // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
duke@435 | 305 | // in the interpreter frame (the method lock if a sync method) |
duke@435 | 306 | |
duke@435 | 307 | // Initialize monitors in the compiled activation. |
duke@435 | 308 | // rcx: pointer to osr buffer |
duke@435 | 309 | // |
duke@435 | 310 | // All other registers are dead at this point and the locals will be |
duke@435 | 311 | // copied into place by code emitted in the IR. |
duke@435 | 312 | |
never@739 | 313 | Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
duke@435 | 314 | { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
duke@435 | 315 | int monitor_offset = BytesPerWord * method()->max_locals() + |
roland@1495 | 316 | (2 * BytesPerWord) * (number_of_locks - 1); |
roland@1495 | 317 | // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in |
roland@1495 | 318 | // the OSR buffer using 2 word entries: first the lock and then |
roland@1495 | 319 | // the oop. |
duke@435 | 320 | for (int i = 0; i < number_of_locks; i++) { |
roland@1495 | 321 | int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
duke@435 | 322 | #ifdef ASSERT |
duke@435 | 323 | // verify the interpreter's monitor has a non-null object |
duke@435 | 324 | { |
duke@435 | 325 | Label L; |
roland@1495 | 326 | __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
duke@435 | 327 | __ jcc(Assembler::notZero, L); |
duke@435 | 328 | __ stop("locked object is NULL"); |
duke@435 | 329 | __ bind(L); |
duke@435 | 330 | } |
duke@435 | 331 | #endif |
roland@1495 | 332 | __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
never@739 | 333 | __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
roland@1495 | 334 | __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
never@739 | 335 | __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
duke@435 | 336 | } |
duke@435 | 337 | } |
duke@435 | 338 | } |
duke@435 | 339 | |
duke@435 | 340 | |
duke@435 | 341 | // inline cache check; done before the frame is built. |
duke@435 | 342 | int LIR_Assembler::check_icache() { |
duke@435 | 343 | Register receiver = FrameMap::receiver_opr->as_register(); |
duke@435 | 344 | Register ic_klass = IC_Klass; |
never@739 | 345 | const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
iveresov@2344 | 346 | const bool do_post_padding = VerifyOops || UseCompressedOops; |
iveresov@2344 | 347 | if (!do_post_padding) { |
duke@435 | 348 | // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
never@739 | 349 | while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
duke@435 | 350 | __ nop(); |
duke@435 | 351 | } |
duke@435 | 352 | } |
duke@435 | 353 | int offset = __ offset(); |
duke@435 | 354 | __ inline_cache_check(receiver, IC_Klass); |
iveresov@2344 | 355 | assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
iveresov@2344 | 356 | if (do_post_padding) { |
duke@435 | 357 | // force alignment after the cache check. |
duke@435 | 358 | // It's been verified to be aligned if !VerifyOops |
duke@435 | 359 | __ align(CodeEntryAlignment); |
duke@435 | 360 | } |
duke@435 | 361 | return offset; |
duke@435 | 362 | } |
duke@435 | 363 | |
duke@435 | 364 | |
duke@435 | 365 | void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { |
duke@435 | 366 | jobject o = NULL; |
duke@435 | 367 | PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
duke@435 | 368 | __ movoop(reg, o); |
duke@435 | 369 | patching_epilog(patch, lir_patch_normal, reg, info); |
duke@435 | 370 | } |
duke@435 | 371 | |
duke@435 | 372 | |
duke@435 | 373 | void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { |
duke@435 | 374 | if (exception->is_valid()) { |
duke@435 | 375 | // preserve exception |
duke@435 | 376 | // note: the monitor_exit runtime call is a leaf routine |
duke@435 | 377 | // and cannot block => no GC can happen |
duke@435 | 378 | // The slow case (MonitorAccessStub) uses the first two stack slots |
duke@435 | 379 | // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] |
never@739 | 380 | __ movptr (Address(rsp, 2*wordSize), exception); |
duke@435 | 381 | } |
duke@435 | 382 | |
duke@435 | 383 | Register obj_reg = obj_opr->as_register(); |
duke@435 | 384 | Register lock_reg = lock_opr->as_register(); |
duke@435 | 385 | |
duke@435 | 386 | // setup registers (lock_reg must be rax, for lock_object) |
duke@435 | 387 | assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); |
duke@435 | 388 | Register hdr = lock_reg; |
duke@435 | 389 | assert(new_hdr == SYNC_header, "wrong register"); |
duke@435 | 390 | lock_reg = new_hdr; |
duke@435 | 391 | // compute pointer to BasicLock |
duke@435 | 392 | Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); |
never@739 | 393 | __ lea(lock_reg, lock_addr); |
duke@435 | 394 | // unlock object |
duke@435 | 395 | MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); |
duke@435 | 396 | // _slow_case_stubs->append(slow_case); |
duke@435 | 397 | // temporary fix: must be created after exceptionhandler, therefore as call stub |
duke@435 | 398 | _slow_case_stubs->append(slow_case); |
duke@435 | 399 | if (UseFastLocking) { |
duke@435 | 400 | // try inlined fast unlocking first, revert to slow locking if it fails |
duke@435 | 401 | // note: lock_reg points to the displaced header since the displaced header offset is 0! |
duke@435 | 402 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 403 | __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); |
duke@435 | 404 | } else { |
duke@435 | 405 | // always do slow unlocking |
duke@435 | 406 | // note: the slow unlocking code could be inlined here, however if we use |
duke@435 | 407 | // slow unlocking, speed doesn't matter anyway and this solution is |
duke@435 | 408 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 409 | // slow unlocking code is the same in either case which simplifies |
duke@435 | 410 | // debugging |
duke@435 | 411 | __ jmp(*slow_case->entry()); |
duke@435 | 412 | } |
duke@435 | 413 | // done |
duke@435 | 414 | __ bind(*slow_case->continuation()); |
duke@435 | 415 | |
duke@435 | 416 | if (exception->is_valid()) { |
duke@435 | 417 | // restore exception |
never@739 | 418 | __ movptr (exception, Address(rsp, 2 * wordSize)); |
duke@435 | 419 | } |
duke@435 | 420 | } |
duke@435 | 421 | |
duke@435 | 422 | // This specifies the rsp decrement needed to build the frame |
duke@435 | 423 | int LIR_Assembler::initial_frame_size_in_bytes() { |
duke@435 | 424 | // if rounding, must let FrameMap know! |
never@739 | 425 | |
never@739 | 426 | // The frame_map records size in slots (32bit word) |
never@739 | 427 | |
never@739 | 428 | // subtract two words to account for return address and link |
never@739 | 429 | return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; |
duke@435 | 430 | } |
duke@435 | 431 | |
duke@435 | 432 | |
twisti@1639 | 433 | int LIR_Assembler::emit_exception_handler() { |
duke@435 | 434 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 435 | // is coming at the end after block reordering) the return address |
duke@435 | 436 | // must still point into the code area in order to avoid assertion |
duke@435 | 437 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 438 | // (was bug 5/14/1999 - gri) |
duke@435 | 439 | __ nop(); |
duke@435 | 440 | |
duke@435 | 441 | // generate code for exception handler |
duke@435 | 442 | address handler_base = __ start_a_stub(exception_handler_size); |
duke@435 | 443 | if (handler_base == NULL) { |
duke@435 | 444 | // not enough space left for the handler |
duke@435 | 445 | bailout("exception handler overflow"); |
twisti@1639 | 446 | return -1; |
duke@435 | 447 | } |
twisti@1639 | 448 | |
duke@435 | 449 | int offset = code_offset(); |
duke@435 | 450 | |
twisti@1730 | 451 | // the exception oop and pc are in rax, and rdx |
duke@435 | 452 | // no other registers need to be preserved, so invalidate them |
twisti@1730 | 453 | __ invalidate_registers(false, true, true, false, true, true); |
duke@435 | 454 | |
duke@435 | 455 | // check that there is really an exception |
duke@435 | 456 | __ verify_not_null_oop(rax); |
duke@435 | 457 | |
twisti@1730 | 458 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
twisti@1730 | 459 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); |
twisti@1730 | 460 | |
twisti@1730 | 461 | __ stop("should not reach here"); |
twisti@1730 | 462 | |
duke@435 | 463 | assert(code_offset() - offset <= exception_handler_size, "overflow"); |
duke@435 | 464 | __ end_a_stub(); |
twisti@1639 | 465 | |
twisti@1639 | 466 | return offset; |
duke@435 | 467 | } |
duke@435 | 468 | |
twisti@1639 | 469 | |
never@1813 | 470 | // Emit the code to remove the frame from the stack in the exception |
never@1813 | 471 | // unwind path. |
never@1813 | 472 | int LIR_Assembler::emit_unwind_handler() { |
never@1813 | 473 | #ifndef PRODUCT |
never@1813 | 474 | if (CommentedAssembly) { |
never@1813 | 475 | _masm->block_comment("Unwind handler"); |
never@1813 | 476 | } |
never@1813 | 477 | #endif |
never@1813 | 478 | |
never@1813 | 479 | int offset = code_offset(); |
never@1813 | 480 | |
never@1813 | 481 | // Fetch the exception from TLS and clear out exception related thread state |
never@1813 | 482 | __ get_thread(rsi); |
never@1813 | 483 | __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
never@1813 | 484 | __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); |
never@1813 | 485 | __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); |
never@1813 | 486 | |
never@1813 | 487 | __ bind(_unwind_handler_entry); |
never@1813 | 488 | __ verify_not_null_oop(rax); |
never@1813 | 489 | if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
never@1813 | 490 | __ mov(rsi, rax); // Preserve the exception |
never@1813 | 491 | } |
never@1813 | 492 | |
never@1813 | 493 | // Preform needed unlocking |
never@1813 | 494 | MonitorExitStub* stub = NULL; |
never@1813 | 495 | if (method()->is_synchronized()) { |
never@1813 | 496 | monitor_address(0, FrameMap::rax_opr); |
never@1813 | 497 | stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
never@1813 | 498 | __ unlock_object(rdi, rbx, rax, *stub->entry()); |
never@1813 | 499 | __ bind(*stub->continuation()); |
never@1813 | 500 | } |
never@1813 | 501 | |
never@1813 | 502 | if (compilation()->env()->dtrace_method_probes()) { |
never@2185 | 503 | __ get_thread(rax); |
never@2185 | 504 | __ movptr(Address(rsp, 0), rax); |
never@2185 | 505 | __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
never@1813 | 506 | __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
never@1813 | 507 | } |
never@1813 | 508 | |
never@1813 | 509 | if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
never@1813 | 510 | __ mov(rax, rsi); // Restore the exception |
never@1813 | 511 | } |
never@1813 | 512 | |
never@1813 | 513 | // remove the activation and dispatch to the unwind handler |
never@1813 | 514 | __ remove_frame(initial_frame_size_in_bytes()); |
never@1813 | 515 | __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
never@1813 | 516 | |
never@1813 | 517 | // Emit the slow path assembly |
never@1813 | 518 | if (stub != NULL) { |
never@1813 | 519 | stub->emit_code(this); |
never@1813 | 520 | } |
never@1813 | 521 | |
never@1813 | 522 | return offset; |
never@1813 | 523 | } |
never@1813 | 524 | |
never@1813 | 525 | |
twisti@1639 | 526 | int LIR_Assembler::emit_deopt_handler() { |
duke@435 | 527 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 528 | // is coming at the end after block reordering) the return address |
duke@435 | 529 | // must still point into the code area in order to avoid assertion |
duke@435 | 530 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 531 | // (was bug 5/14/1999 - gri) |
duke@435 | 532 | __ nop(); |
duke@435 | 533 | |
duke@435 | 534 | // generate code for exception handler |
duke@435 | 535 | address handler_base = __ start_a_stub(deopt_handler_size); |
duke@435 | 536 | if (handler_base == NULL) { |
duke@435 | 537 | // not enough space left for the handler |
duke@435 | 538 | bailout("deopt handler overflow"); |
twisti@1639 | 539 | return -1; |
duke@435 | 540 | } |
twisti@1639 | 541 | |
duke@435 | 542 | int offset = code_offset(); |
duke@435 | 543 | InternalAddress here(__ pc()); |
twisti@1730 | 544 | |
duke@435 | 545 | __ pushptr(here.addr()); |
duke@435 | 546 | __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
twisti@1730 | 547 | |
duke@435 | 548 | assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
duke@435 | 549 | __ end_a_stub(); |
duke@435 | 550 | |
twisti@1639 | 551 | return offset; |
duke@435 | 552 | } |
duke@435 | 553 | |
duke@435 | 554 | |
duke@435 | 555 | // This is the fast version of java.lang.String.compare; it has not |
duke@435 | 556 | // OSR-entry and therefore, we generate a slow version for OSR's |
duke@435 | 557 | void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { |
never@739 | 558 | __ movptr (rbx, rcx); // receiver is in rcx |
never@739 | 559 | __ movptr (rax, arg1->as_register()); |
duke@435 | 560 | |
duke@435 | 561 | // Get addresses of first characters from both Strings |
iveresov@2344 | 562 | __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
iveresov@2344 | 563 | __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); |
iveresov@2344 | 564 | __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 565 | |
duke@435 | 566 | |
duke@435 | 567 | // rbx, may be NULL |
duke@435 | 568 | add_debug_info_for_null_check_here(info); |
iveresov@2344 | 569 | __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
iveresov@2344 | 570 | __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); |
iveresov@2344 | 571 | __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 572 | |
duke@435 | 573 | // compute minimum length (in rax) and difference of lengths (on top of stack) |
duke@435 | 574 | if (VM_Version::supports_cmov()) { |
never@739 | 575 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 576 | __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 577 | __ mov (rcx, rbx); |
never@739 | 578 | __ subptr (rbx, rax); // subtract lengths |
never@739 | 579 | __ push (rbx); // result |
never@739 | 580 | __ cmov (Assembler::lessEqual, rax, rcx); |
duke@435 | 581 | } else { |
duke@435 | 582 | Label L; |
never@739 | 583 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 584 | __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 585 | __ mov (rax, rbx); |
never@739 | 586 | __ subptr (rbx, rcx); |
never@739 | 587 | __ push (rbx); |
never@739 | 588 | __ jcc (Assembler::lessEqual, L); |
never@739 | 589 | __ mov (rax, rcx); |
duke@435 | 590 | __ bind (L); |
duke@435 | 591 | } |
duke@435 | 592 | // is minimum length 0? |
duke@435 | 593 | Label noLoop, haveResult; |
never@739 | 594 | __ testptr (rax, rax); |
duke@435 | 595 | __ jcc (Assembler::zero, noLoop); |
duke@435 | 596 | |
duke@435 | 597 | // compare first characters |
jrose@1057 | 598 | __ load_unsigned_short(rcx, Address(rdi, 0)); |
jrose@1057 | 599 | __ load_unsigned_short(rbx, Address(rsi, 0)); |
duke@435 | 600 | __ subl(rcx, rbx); |
duke@435 | 601 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 602 | // starting loop |
duke@435 | 603 | __ decrement(rax); // we already tested index: skip one |
duke@435 | 604 | __ jcc(Assembler::zero, noLoop); |
duke@435 | 605 | |
duke@435 | 606 | // set rsi.edi to the end of the arrays (arrays have same length) |
duke@435 | 607 | // negate the index |
duke@435 | 608 | |
never@739 | 609 | __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 610 | __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 611 | __ negptr(rax); |
duke@435 | 612 | |
duke@435 | 613 | // compare the strings in a loop |
duke@435 | 614 | |
duke@435 | 615 | Label loop; |
duke@435 | 616 | __ align(wordSize); |
duke@435 | 617 | __ bind(loop); |
jrose@1057 | 618 | __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
jrose@1057 | 619 | __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
duke@435 | 620 | __ subl(rcx, rbx); |
duke@435 | 621 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 622 | __ increment(rax); |
duke@435 | 623 | __ jcc(Assembler::notZero, loop); |
duke@435 | 624 | |
duke@435 | 625 | // strings are equal up to min length |
duke@435 | 626 | |
duke@435 | 627 | __ bind(noLoop); |
never@739 | 628 | __ pop(rax); |
duke@435 | 629 | return_op(LIR_OprFact::illegalOpr); |
duke@435 | 630 | |
duke@435 | 631 | __ bind(haveResult); |
duke@435 | 632 | // leave instruction is going to discard the TOS value |
never@739 | 633 | __ mov (rax, rcx); // result of call is in rax, |
duke@435 | 634 | } |
duke@435 | 635 | |
duke@435 | 636 | |
duke@435 | 637 | void LIR_Assembler::return_op(LIR_Opr result) { |
duke@435 | 638 | assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); |
duke@435 | 639 | if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { |
duke@435 | 640 | assert(result->fpu() == 0, "result must already be on TOS"); |
duke@435 | 641 | } |
duke@435 | 642 | |
duke@435 | 643 | // Pop the stack before the safepoint code |
twisti@1730 | 644 | __ remove_frame(initial_frame_size_in_bytes()); |
duke@435 | 645 | |
duke@435 | 646 | bool result_is_oop = result->is_valid() ? result->is_oop() : false; |
duke@435 | 647 | |
duke@435 | 648 | // Note: we do not need to round double result; float result has the right precision |
duke@435 | 649 | // the poll sets the condition code, but no data registers |
duke@435 | 650 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 651 | relocInfo::poll_return_type); |
never@739 | 652 | |
never@739 | 653 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 654 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 655 | // which breaks the signal handler code |
never@739 | 656 | |
duke@435 | 657 | __ test32(rax, polling_page); |
duke@435 | 658 | |
duke@435 | 659 | __ ret(0); |
duke@435 | 660 | } |
duke@435 | 661 | |
duke@435 | 662 | |
duke@435 | 663 | int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 664 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 665 | relocInfo::poll_type); |
duke@435 | 666 | |
duke@435 | 667 | if (info != NULL) { |
duke@435 | 668 | add_debug_info_for_branch(info); |
duke@435 | 669 | } else { |
duke@435 | 670 | ShouldNotReachHere(); |
duke@435 | 671 | } |
duke@435 | 672 | |
duke@435 | 673 | int offset = __ offset(); |
never@739 | 674 | |
never@739 | 675 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 676 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 677 | // which breaks the signal handler code |
never@739 | 678 | |
duke@435 | 679 | __ test32(rax, polling_page); |
duke@435 | 680 | return offset; |
duke@435 | 681 | } |
duke@435 | 682 | |
duke@435 | 683 | |
duke@435 | 684 | void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { |
never@739 | 685 | if (from_reg != to_reg) __ mov(to_reg, from_reg); |
duke@435 | 686 | } |
duke@435 | 687 | |
duke@435 | 688 | void LIR_Assembler::swap_reg(Register a, Register b) { |
never@739 | 689 | __ xchgptr(a, b); |
duke@435 | 690 | } |
duke@435 | 691 | |
duke@435 | 692 | |
duke@435 | 693 | void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
duke@435 | 694 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 695 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 696 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 697 | |
duke@435 | 698 | switch (c->type()) { |
iveresov@2344 | 699 | case T_INT: { |
iveresov@2344 | 700 | assert(patch_code == lir_patch_none, "no patching handled here"); |
iveresov@2344 | 701 | __ movl(dest->as_register(), c->as_jint()); |
iveresov@2344 | 702 | break; |
iveresov@2344 | 703 | } |
iveresov@2344 | 704 | |
roland@1732 | 705 | case T_ADDRESS: { |
duke@435 | 706 | assert(patch_code == lir_patch_none, "no patching handled here"); |
iveresov@2344 | 707 | __ movptr(dest->as_register(), c->as_jint()); |
duke@435 | 708 | break; |
duke@435 | 709 | } |
duke@435 | 710 | |
duke@435 | 711 | case T_LONG: { |
duke@435 | 712 | assert(patch_code == lir_patch_none, "no patching handled here"); |
never@739 | 713 | #ifdef _LP64 |
never@739 | 714 | __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); |
never@739 | 715 | #else |
never@739 | 716 | __ movptr(dest->as_register_lo(), c->as_jint_lo()); |
never@739 | 717 | __ movptr(dest->as_register_hi(), c->as_jint_hi()); |
never@739 | 718 | #endif // _LP64 |
duke@435 | 719 | break; |
duke@435 | 720 | } |
duke@435 | 721 | |
duke@435 | 722 | case T_OBJECT: { |
duke@435 | 723 | if (patch_code != lir_patch_none) { |
duke@435 | 724 | jobject2reg_with_patching(dest->as_register(), info); |
duke@435 | 725 | } else { |
duke@435 | 726 | __ movoop(dest->as_register(), c->as_jobject()); |
duke@435 | 727 | } |
duke@435 | 728 | break; |
duke@435 | 729 | } |
duke@435 | 730 | |
duke@435 | 731 | case T_FLOAT: { |
duke@435 | 732 | if (dest->is_single_xmm()) { |
duke@435 | 733 | if (c->is_zero_float()) { |
duke@435 | 734 | __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); |
duke@435 | 735 | } else { |
duke@435 | 736 | __ movflt(dest->as_xmm_float_reg(), |
duke@435 | 737 | InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 738 | } |
duke@435 | 739 | } else { |
duke@435 | 740 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 741 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 742 | if (c->is_zero_float()) { |
duke@435 | 743 | __ fldz(); |
duke@435 | 744 | } else if (c->is_one_float()) { |
duke@435 | 745 | __ fld1(); |
duke@435 | 746 | } else { |
duke@435 | 747 | __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 748 | } |
duke@435 | 749 | } |
duke@435 | 750 | break; |
duke@435 | 751 | } |
duke@435 | 752 | |
duke@435 | 753 | case T_DOUBLE: { |
duke@435 | 754 | if (dest->is_double_xmm()) { |
duke@435 | 755 | if (c->is_zero_double()) { |
duke@435 | 756 | __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); |
duke@435 | 757 | } else { |
duke@435 | 758 | __ movdbl(dest->as_xmm_double_reg(), |
duke@435 | 759 | InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 760 | } |
duke@435 | 761 | } else { |
duke@435 | 762 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 763 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 764 | if (c->is_zero_double()) { |
duke@435 | 765 | __ fldz(); |
duke@435 | 766 | } else if (c->is_one_double()) { |
duke@435 | 767 | __ fld1(); |
duke@435 | 768 | } else { |
duke@435 | 769 | __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 770 | } |
duke@435 | 771 | } |
duke@435 | 772 | break; |
duke@435 | 773 | } |
duke@435 | 774 | |
duke@435 | 775 | default: |
duke@435 | 776 | ShouldNotReachHere(); |
duke@435 | 777 | } |
duke@435 | 778 | } |
duke@435 | 779 | |
duke@435 | 780 | void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 781 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 782 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 783 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 784 | |
duke@435 | 785 | switch (c->type()) { |
duke@435 | 786 | case T_INT: // fall through |
duke@435 | 787 | case T_FLOAT: |
iveresov@2344 | 788 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
iveresov@2344 | 789 | break; |
iveresov@2344 | 790 | |
roland@1732 | 791 | case T_ADDRESS: |
iveresov@2344 | 792 | __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
duke@435 | 793 | break; |
duke@435 | 794 | |
duke@435 | 795 | case T_OBJECT: |
duke@435 | 796 | __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); |
duke@435 | 797 | break; |
duke@435 | 798 | |
duke@435 | 799 | case T_LONG: // fall through |
duke@435 | 800 | case T_DOUBLE: |
never@739 | 801 | #ifdef _LP64 |
never@739 | 802 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 803 | lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); |
never@739 | 804 | #else |
never@739 | 805 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 806 | lo_word_offset_in_bytes), c->as_jint_lo_bits()); |
never@739 | 807 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 808 | hi_word_offset_in_bytes), c->as_jint_hi_bits()); |
never@739 | 809 | #endif // _LP64 |
duke@435 | 810 | break; |
duke@435 | 811 | |
duke@435 | 812 | default: |
duke@435 | 813 | ShouldNotReachHere(); |
duke@435 | 814 | } |
duke@435 | 815 | } |
duke@435 | 816 | |
iveresov@2344 | 817 | void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
duke@435 | 818 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 819 | assert(dest->is_address(), "should not call otherwise"); |
duke@435 | 820 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 821 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 822 | |
never@739 | 823 | int null_check_here = code_offset(); |
duke@435 | 824 | switch (type) { |
duke@435 | 825 | case T_INT: // fall through |
duke@435 | 826 | case T_FLOAT: |
iveresov@2344 | 827 | __ movl(as_Address(addr), c->as_jint_bits()); |
iveresov@2344 | 828 | break; |
iveresov@2344 | 829 | |
roland@1732 | 830 | case T_ADDRESS: |
iveresov@2344 | 831 | __ movptr(as_Address(addr), c->as_jint_bits()); |
duke@435 | 832 | break; |
duke@435 | 833 | |
duke@435 | 834 | case T_OBJECT: // fall through |
duke@435 | 835 | case T_ARRAY: |
duke@435 | 836 | if (c->as_jobject() == NULL) { |
iveresov@2344 | 837 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 838 | __ movl(as_Address(addr), (int32_t)NULL_WORD); |
iveresov@2344 | 839 | } else { |
iveresov@2344 | 840 | __ movptr(as_Address(addr), NULL_WORD); |
iveresov@2344 | 841 | } |
duke@435 | 842 | } else { |
never@739 | 843 | if (is_literal_address(addr)) { |
never@739 | 844 | ShouldNotReachHere(); |
never@739 | 845 | __ movoop(as_Address(addr, noreg), c->as_jobject()); |
never@739 | 846 | } else { |
roland@1495 | 847 | #ifdef _LP64 |
roland@1495 | 848 | __ movoop(rscratch1, c->as_jobject()); |
iveresov@2344 | 849 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 850 | __ encode_heap_oop(rscratch1); |
iveresov@2344 | 851 | null_check_here = code_offset(); |
iveresov@2344 | 852 | __ movl(as_Address_lo(addr), rscratch1); |
iveresov@2344 | 853 | } else { |
iveresov@2344 | 854 | null_check_here = code_offset(); |
iveresov@2344 | 855 | __ movptr(as_Address_lo(addr), rscratch1); |
iveresov@2344 | 856 | } |
roland@1495 | 857 | #else |
never@739 | 858 | __ movoop(as_Address(addr), c->as_jobject()); |
roland@1495 | 859 | #endif |
never@739 | 860 | } |
duke@435 | 861 | } |
duke@435 | 862 | break; |
duke@435 | 863 | |
duke@435 | 864 | case T_LONG: // fall through |
duke@435 | 865 | case T_DOUBLE: |
never@739 | 866 | #ifdef _LP64 |
never@739 | 867 | if (is_literal_address(addr)) { |
never@739 | 868 | ShouldNotReachHere(); |
never@739 | 869 | __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); |
never@739 | 870 | } else { |
never@739 | 871 | __ movptr(r10, (intptr_t)c->as_jlong_bits()); |
never@739 | 872 | null_check_here = code_offset(); |
never@739 | 873 | __ movptr(as_Address_lo(addr), r10); |
never@739 | 874 | } |
never@739 | 875 | #else |
never@739 | 876 | // Always reachable in 32bit so this doesn't produce useless move literal |
never@739 | 877 | __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); |
never@739 | 878 | __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); |
never@739 | 879 | #endif // _LP64 |
duke@435 | 880 | break; |
duke@435 | 881 | |
duke@435 | 882 | case T_BOOLEAN: // fall through |
duke@435 | 883 | case T_BYTE: |
duke@435 | 884 | __ movb(as_Address(addr), c->as_jint() & 0xFF); |
duke@435 | 885 | break; |
duke@435 | 886 | |
duke@435 | 887 | case T_CHAR: // fall through |
duke@435 | 888 | case T_SHORT: |
duke@435 | 889 | __ movw(as_Address(addr), c->as_jint() & 0xFFFF); |
duke@435 | 890 | break; |
duke@435 | 891 | |
duke@435 | 892 | default: |
duke@435 | 893 | ShouldNotReachHere(); |
duke@435 | 894 | }; |
never@739 | 895 | |
never@739 | 896 | if (info != NULL) { |
never@739 | 897 | add_debug_info_for_null_check(null_check_here, info); |
never@739 | 898 | } |
duke@435 | 899 | } |
duke@435 | 900 | |
duke@435 | 901 | |
duke@435 | 902 | void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 903 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 904 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 905 | |
duke@435 | 906 | // move between cpu-registers |
duke@435 | 907 | if (dest->is_single_cpu()) { |
never@739 | 908 | #ifdef _LP64 |
never@739 | 909 | if (src->type() == T_LONG) { |
never@739 | 910 | // Can do LONG -> OBJECT |
never@739 | 911 | move_regs(src->as_register_lo(), dest->as_register()); |
never@739 | 912 | return; |
never@739 | 913 | } |
never@739 | 914 | #endif |
duke@435 | 915 | assert(src->is_single_cpu(), "must match"); |
duke@435 | 916 | if (src->type() == T_OBJECT) { |
duke@435 | 917 | __ verify_oop(src->as_register()); |
duke@435 | 918 | } |
duke@435 | 919 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 920 | |
duke@435 | 921 | } else if (dest->is_double_cpu()) { |
never@739 | 922 | #ifdef _LP64 |
never@739 | 923 | if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
never@739 | 924 | // Surprising to me but we can see move of a long to t_object |
never@739 | 925 | __ verify_oop(src->as_register()); |
never@739 | 926 | move_regs(src->as_register(), dest->as_register_lo()); |
never@739 | 927 | return; |
never@739 | 928 | } |
never@739 | 929 | #endif |
duke@435 | 930 | assert(src->is_double_cpu(), "must match"); |
duke@435 | 931 | Register f_lo = src->as_register_lo(); |
duke@435 | 932 | Register f_hi = src->as_register_hi(); |
duke@435 | 933 | Register t_lo = dest->as_register_lo(); |
duke@435 | 934 | Register t_hi = dest->as_register_hi(); |
never@739 | 935 | #ifdef _LP64 |
never@739 | 936 | assert(f_hi == f_lo, "must be same"); |
never@739 | 937 | assert(t_hi == t_lo, "must be same"); |
never@739 | 938 | move_regs(f_lo, t_lo); |
never@739 | 939 | #else |
duke@435 | 940 | assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
duke@435 | 941 | |
never@739 | 942 | |
duke@435 | 943 | if (f_lo == t_hi && f_hi == t_lo) { |
duke@435 | 944 | swap_reg(f_lo, f_hi); |
duke@435 | 945 | } else if (f_hi == t_lo) { |
duke@435 | 946 | assert(f_lo != t_hi, "overwriting register"); |
duke@435 | 947 | move_regs(f_hi, t_hi); |
duke@435 | 948 | move_regs(f_lo, t_lo); |
duke@435 | 949 | } else { |
duke@435 | 950 | assert(f_hi != t_lo, "overwriting register"); |
duke@435 | 951 | move_regs(f_lo, t_lo); |
duke@435 | 952 | move_regs(f_hi, t_hi); |
duke@435 | 953 | } |
never@739 | 954 | #endif // LP64 |
duke@435 | 955 | |
duke@435 | 956 | // special moves from fpu-register to xmm-register |
duke@435 | 957 | // necessary for method results |
duke@435 | 958 | } else if (src->is_single_xmm() && !dest->is_single_xmm()) { |
duke@435 | 959 | __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); |
duke@435 | 960 | __ fld_s(Address(rsp, 0)); |
duke@435 | 961 | } else if (src->is_double_xmm() && !dest->is_double_xmm()) { |
duke@435 | 962 | __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); |
duke@435 | 963 | __ fld_d(Address(rsp, 0)); |
duke@435 | 964 | } else if (dest->is_single_xmm() && !src->is_single_xmm()) { |
duke@435 | 965 | __ fstp_s(Address(rsp, 0)); |
duke@435 | 966 | __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); |
duke@435 | 967 | } else if (dest->is_double_xmm() && !src->is_double_xmm()) { |
duke@435 | 968 | __ fstp_d(Address(rsp, 0)); |
duke@435 | 969 | __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); |
duke@435 | 970 | |
duke@435 | 971 | // move between xmm-registers |
duke@435 | 972 | } else if (dest->is_single_xmm()) { |
duke@435 | 973 | assert(src->is_single_xmm(), "must match"); |
duke@435 | 974 | __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); |
duke@435 | 975 | } else if (dest->is_double_xmm()) { |
duke@435 | 976 | assert(src->is_double_xmm(), "must match"); |
duke@435 | 977 | __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); |
duke@435 | 978 | |
duke@435 | 979 | // move between fpu-registers (no instruction necessary because of fpu-stack) |
duke@435 | 980 | } else if (dest->is_single_fpu() || dest->is_double_fpu()) { |
duke@435 | 981 | assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); |
duke@435 | 982 | assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); |
duke@435 | 983 | } else { |
duke@435 | 984 | ShouldNotReachHere(); |
duke@435 | 985 | } |
duke@435 | 986 | } |
duke@435 | 987 | |
duke@435 | 988 | void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
duke@435 | 989 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 990 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 991 | |
duke@435 | 992 | if (src->is_single_cpu()) { |
duke@435 | 993 | Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 994 | if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 995 | __ verify_oop(src->as_register()); |
never@739 | 996 | __ movptr (dst, src->as_register()); |
never@739 | 997 | } else { |
never@739 | 998 | __ movl (dst, src->as_register()); |
duke@435 | 999 | } |
duke@435 | 1000 | |
duke@435 | 1001 | } else if (src->is_double_cpu()) { |
duke@435 | 1002 | Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 1003 | Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 1004 | __ movptr (dstLO, src->as_register_lo()); |
never@739 | 1005 | NOT_LP64(__ movptr (dstHI, src->as_register_hi())); |
duke@435 | 1006 | |
duke@435 | 1007 | } else if (src->is_single_xmm()) { |
duke@435 | 1008 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1009 | __ movflt(dst_addr, src->as_xmm_float_reg()); |
duke@435 | 1010 | |
duke@435 | 1011 | } else if (src->is_double_xmm()) { |
duke@435 | 1012 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 1013 | __ movdbl(dst_addr, src->as_xmm_double_reg()); |
duke@435 | 1014 | |
duke@435 | 1015 | } else if (src->is_single_fpu()) { |
duke@435 | 1016 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 1017 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1018 | if (pop_fpu_stack) __ fstp_s (dst_addr); |
duke@435 | 1019 | else __ fst_s (dst_addr); |
duke@435 | 1020 | |
duke@435 | 1021 | } else if (src->is_double_fpu()) { |
duke@435 | 1022 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 1023 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 1024 | if (pop_fpu_stack) __ fstp_d (dst_addr); |
duke@435 | 1025 | else __ fst_d (dst_addr); |
duke@435 | 1026 | |
duke@435 | 1027 | } else { |
duke@435 | 1028 | ShouldNotReachHere(); |
duke@435 | 1029 | } |
duke@435 | 1030 | } |
duke@435 | 1031 | |
duke@435 | 1032 | |
iveresov@2344 | 1033 | void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
duke@435 | 1034 | LIR_Address* to_addr = dest->as_address_ptr(); |
duke@435 | 1035 | PatchingStub* patch = NULL; |
iveresov@2344 | 1036 | Register compressed_src = rscratch1; |
duke@435 | 1037 | |
duke@435 | 1038 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 1039 | __ verify_oop(src->as_register()); |
iveresov@2344 | 1040 | #ifdef _LP64 |
iveresov@2344 | 1041 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1042 | __ movptr(compressed_src, src->as_register()); |
iveresov@2344 | 1043 | __ encode_heap_oop(compressed_src); |
iveresov@2344 | 1044 | } |
iveresov@2344 | 1045 | #endif |
duke@435 | 1046 | } |
iveresov@2344 | 1047 | |
duke@435 | 1048 | if (patch_code != lir_patch_none) { |
duke@435 | 1049 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 1050 | Address toa = as_Address(to_addr); |
never@739 | 1051 | assert(toa.disp() != 0, "must have"); |
duke@435 | 1052 | } |
iveresov@2344 | 1053 | |
iveresov@2344 | 1054 | int null_check_here = code_offset(); |
duke@435 | 1055 | switch (type) { |
duke@435 | 1056 | case T_FLOAT: { |
duke@435 | 1057 | if (src->is_single_xmm()) { |
duke@435 | 1058 | __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); |
duke@435 | 1059 | } else { |
duke@435 | 1060 | assert(src->is_single_fpu(), "must be"); |
duke@435 | 1061 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 1062 | if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); |
duke@435 | 1063 | else __ fst_s (as_Address(to_addr)); |
duke@435 | 1064 | } |
duke@435 | 1065 | break; |
duke@435 | 1066 | } |
duke@435 | 1067 | |
duke@435 | 1068 | case T_DOUBLE: { |
duke@435 | 1069 | if (src->is_double_xmm()) { |
duke@435 | 1070 | __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); |
duke@435 | 1071 | } else { |
duke@435 | 1072 | assert(src->is_double_fpu(), "must be"); |
duke@435 | 1073 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 1074 | if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); |
duke@435 | 1075 | else __ fst_d (as_Address(to_addr)); |
duke@435 | 1076 | } |
duke@435 | 1077 | break; |
duke@435 | 1078 | } |
duke@435 | 1079 | |
duke@435 | 1080 | case T_ARRAY: // fall through |
duke@435 | 1081 | case T_OBJECT: // fall through |
iveresov@2344 | 1082 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1083 | __ movl(as_Address(to_addr), compressed_src); |
iveresov@2344 | 1084 | } else { |
iveresov@2344 | 1085 | __ movptr(as_Address(to_addr), src->as_register()); |
iveresov@2344 | 1086 | } |
iveresov@2344 | 1087 | break; |
iveresov@2344 | 1088 | case T_ADDRESS: |
never@739 | 1089 | __ movptr(as_Address(to_addr), src->as_register()); |
never@739 | 1090 | break; |
duke@435 | 1091 | case T_INT: |
duke@435 | 1092 | __ movl(as_Address(to_addr), src->as_register()); |
duke@435 | 1093 | break; |
duke@435 | 1094 | |
duke@435 | 1095 | case T_LONG: { |
duke@435 | 1096 | Register from_lo = src->as_register_lo(); |
duke@435 | 1097 | Register from_hi = src->as_register_hi(); |
never@739 | 1098 | #ifdef _LP64 |
never@739 | 1099 | __ movptr(as_Address_lo(to_addr), from_lo); |
never@739 | 1100 | #else |
duke@435 | 1101 | Register base = to_addr->base()->as_register(); |
duke@435 | 1102 | Register index = noreg; |
duke@435 | 1103 | if (to_addr->index()->is_register()) { |
duke@435 | 1104 | index = to_addr->index()->as_register(); |
duke@435 | 1105 | } |
duke@435 | 1106 | if (base == from_lo || index == from_lo) { |
duke@435 | 1107 | assert(base != from_hi, "can't be"); |
duke@435 | 1108 | assert(index == noreg || (index != base && index != from_hi), "can't handle this"); |
duke@435 | 1109 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1110 | if (patch != NULL) { |
duke@435 | 1111 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1112 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1113 | patch_code = lir_patch_low; |
duke@435 | 1114 | } |
duke@435 | 1115 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1116 | } else { |
duke@435 | 1117 | assert(index == noreg || (index != base && index != from_lo), "can't handle this"); |
duke@435 | 1118 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1119 | if (patch != NULL) { |
duke@435 | 1120 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1121 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1122 | patch_code = lir_patch_high; |
duke@435 | 1123 | } |
duke@435 | 1124 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1125 | } |
never@739 | 1126 | #endif // _LP64 |
duke@435 | 1127 | break; |
duke@435 | 1128 | } |
duke@435 | 1129 | |
duke@435 | 1130 | case T_BYTE: // fall through |
duke@435 | 1131 | case T_BOOLEAN: { |
duke@435 | 1132 | Register src_reg = src->as_register(); |
duke@435 | 1133 | Address dst_addr = as_Address(to_addr); |
duke@435 | 1134 | assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1135 | __ movb(dst_addr, src_reg); |
duke@435 | 1136 | break; |
duke@435 | 1137 | } |
duke@435 | 1138 | |
duke@435 | 1139 | case T_CHAR: // fall through |
duke@435 | 1140 | case T_SHORT: |
duke@435 | 1141 | __ movw(as_Address(to_addr), src->as_register()); |
duke@435 | 1142 | break; |
duke@435 | 1143 | |
duke@435 | 1144 | default: |
duke@435 | 1145 | ShouldNotReachHere(); |
duke@435 | 1146 | } |
iveresov@2344 | 1147 | if (info != NULL) { |
iveresov@2344 | 1148 | add_debug_info_for_null_check(null_check_here, info); |
iveresov@2344 | 1149 | } |
duke@435 | 1150 | |
duke@435 | 1151 | if (patch_code != lir_patch_none) { |
duke@435 | 1152 | patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); |
duke@435 | 1153 | } |
duke@435 | 1154 | } |
duke@435 | 1155 | |
duke@435 | 1156 | |
duke@435 | 1157 | void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1158 | assert(src->is_stack(), "should not call otherwise"); |
duke@435 | 1159 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1160 | |
duke@435 | 1161 | if (dest->is_single_cpu()) { |
duke@435 | 1162 | if (type == T_ARRAY || type == T_OBJECT) { |
never@739 | 1163 | __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1164 | __ verify_oop(dest->as_register()); |
never@739 | 1165 | } else { |
never@739 | 1166 | __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1167 | } |
duke@435 | 1168 | |
duke@435 | 1169 | } else if (dest->is_double_cpu()) { |
duke@435 | 1170 | Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 1171 | Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 1172 | __ movptr(dest->as_register_lo(), src_addr_LO); |
never@739 | 1173 | NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); |
duke@435 | 1174 | |
duke@435 | 1175 | } else if (dest->is_single_xmm()) { |
duke@435 | 1176 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1177 | __ movflt(dest->as_xmm_float_reg(), src_addr); |
duke@435 | 1178 | |
duke@435 | 1179 | } else if (dest->is_double_xmm()) { |
duke@435 | 1180 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1181 | __ movdbl(dest->as_xmm_double_reg(), src_addr); |
duke@435 | 1182 | |
duke@435 | 1183 | } else if (dest->is_single_fpu()) { |
duke@435 | 1184 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1185 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1186 | __ fld_s(src_addr); |
duke@435 | 1187 | |
duke@435 | 1188 | } else if (dest->is_double_fpu()) { |
duke@435 | 1189 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1190 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1191 | __ fld_d(src_addr); |
duke@435 | 1192 | |
duke@435 | 1193 | } else { |
duke@435 | 1194 | ShouldNotReachHere(); |
duke@435 | 1195 | } |
duke@435 | 1196 | } |
duke@435 | 1197 | |
duke@435 | 1198 | |
duke@435 | 1199 | void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1200 | if (src->is_single_stack()) { |
never@739 | 1201 | if (type == T_OBJECT || type == T_ARRAY) { |
never@739 | 1202 | __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1203 | __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); |
never@739 | 1204 | } else { |
roland@1495 | 1205 | #ifndef _LP64 |
never@739 | 1206 | __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1207 | __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); |
roland@1495 | 1208 | #else |
roland@1495 | 1209 | //no pushl on 64bits |
roland@1495 | 1210 | __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); |
roland@1495 | 1211 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); |
roland@1495 | 1212 | #endif |
never@739 | 1213 | } |
duke@435 | 1214 | |
duke@435 | 1215 | } else if (src->is_double_stack()) { |
never@739 | 1216 | #ifdef _LP64 |
never@739 | 1217 | __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); |
never@739 | 1218 | __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); |
never@739 | 1219 | #else |
duke@435 | 1220 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
never@739 | 1221 | // push and pop the part at src + wordSize, adding wordSize for the previous push |
never@756 | 1222 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
never@756 | 1223 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
duke@435 | 1224 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
never@739 | 1225 | #endif // _LP64 |
duke@435 | 1226 | |
duke@435 | 1227 | } else { |
duke@435 | 1228 | ShouldNotReachHere(); |
duke@435 | 1229 | } |
duke@435 | 1230 | } |
duke@435 | 1231 | |
duke@435 | 1232 | |
iveresov@2344 | 1233 | void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
duke@435 | 1234 | assert(src->is_address(), "should not call otherwise"); |
duke@435 | 1235 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1236 | |
duke@435 | 1237 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1238 | Address from_addr = as_Address(addr); |
duke@435 | 1239 | |
duke@435 | 1240 | switch (type) { |
duke@435 | 1241 | case T_BOOLEAN: // fall through |
duke@435 | 1242 | case T_BYTE: // fall through |
duke@435 | 1243 | case T_CHAR: // fall through |
duke@435 | 1244 | case T_SHORT: |
duke@435 | 1245 | if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { |
duke@435 | 1246 | // on pre P6 processors we may get partial register stalls |
duke@435 | 1247 | // so blow away the value of to_rinfo before loading a |
duke@435 | 1248 | // partial word into it. Do it here so that it precedes |
duke@435 | 1249 | // the potential patch point below. |
never@739 | 1250 | __ xorptr(dest->as_register(), dest->as_register()); |
duke@435 | 1251 | } |
duke@435 | 1252 | break; |
duke@435 | 1253 | } |
duke@435 | 1254 | |
duke@435 | 1255 | PatchingStub* patch = NULL; |
duke@435 | 1256 | if (patch_code != lir_patch_none) { |
duke@435 | 1257 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 1258 | assert(from_addr.disp() != 0, "must have"); |
duke@435 | 1259 | } |
duke@435 | 1260 | if (info != NULL) { |
duke@435 | 1261 | add_debug_info_for_null_check_here(info); |
duke@435 | 1262 | } |
duke@435 | 1263 | |
duke@435 | 1264 | switch (type) { |
duke@435 | 1265 | case T_FLOAT: { |
duke@435 | 1266 | if (dest->is_single_xmm()) { |
duke@435 | 1267 | __ movflt(dest->as_xmm_float_reg(), from_addr); |
duke@435 | 1268 | } else { |
duke@435 | 1269 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 1270 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1271 | __ fld_s(from_addr); |
duke@435 | 1272 | } |
duke@435 | 1273 | break; |
duke@435 | 1274 | } |
duke@435 | 1275 | |
duke@435 | 1276 | case T_DOUBLE: { |
duke@435 | 1277 | if (dest->is_double_xmm()) { |
duke@435 | 1278 | __ movdbl(dest->as_xmm_double_reg(), from_addr); |
duke@435 | 1279 | } else { |
duke@435 | 1280 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 1281 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1282 | __ fld_d(from_addr); |
duke@435 | 1283 | } |
duke@435 | 1284 | break; |
duke@435 | 1285 | } |
duke@435 | 1286 | |
duke@435 | 1287 | case T_OBJECT: // fall through |
duke@435 | 1288 | case T_ARRAY: // fall through |
iveresov@2344 | 1289 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1290 | __ movl(dest->as_register(), from_addr); |
iveresov@2344 | 1291 | } else { |
iveresov@2344 | 1292 | __ movptr(dest->as_register(), from_addr); |
iveresov@2344 | 1293 | } |
iveresov@2344 | 1294 | break; |
iveresov@2344 | 1295 | |
iveresov@2344 | 1296 | case T_ADDRESS: |
never@739 | 1297 | __ movptr(dest->as_register(), from_addr); |
never@739 | 1298 | break; |
duke@435 | 1299 | case T_INT: |
iveresov@1833 | 1300 | __ movl(dest->as_register(), from_addr); |
duke@435 | 1301 | break; |
duke@435 | 1302 | |
duke@435 | 1303 | case T_LONG: { |
duke@435 | 1304 | Register to_lo = dest->as_register_lo(); |
duke@435 | 1305 | Register to_hi = dest->as_register_hi(); |
never@739 | 1306 | #ifdef _LP64 |
never@739 | 1307 | __ movptr(to_lo, as_Address_lo(addr)); |
never@739 | 1308 | #else |
duke@435 | 1309 | Register base = addr->base()->as_register(); |
duke@435 | 1310 | Register index = noreg; |
duke@435 | 1311 | if (addr->index()->is_register()) { |
duke@435 | 1312 | index = addr->index()->as_register(); |
duke@435 | 1313 | } |
duke@435 | 1314 | if ((base == to_lo && index == to_hi) || |
duke@435 | 1315 | (base == to_hi && index == to_lo)) { |
duke@435 | 1316 | // addresses with 2 registers are only formed as a result of |
duke@435 | 1317 | // array access so this code will never have to deal with |
duke@435 | 1318 | // patches or null checks. |
duke@435 | 1319 | assert(info == NULL && patch == NULL, "must be"); |
never@739 | 1320 | __ lea(to_hi, as_Address(addr)); |
duke@435 | 1321 | __ movl(to_lo, Address(to_hi, 0)); |
duke@435 | 1322 | __ movl(to_hi, Address(to_hi, BytesPerWord)); |
duke@435 | 1323 | } else if (base == to_lo || index == to_lo) { |
duke@435 | 1324 | assert(base != to_hi, "can't be"); |
duke@435 | 1325 | assert(index == noreg || (index != base && index != to_hi), "can't handle this"); |
duke@435 | 1326 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1327 | if (patch != NULL) { |
duke@435 | 1328 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1329 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1330 | patch_code = lir_patch_low; |
duke@435 | 1331 | } |
duke@435 | 1332 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1333 | } else { |
duke@435 | 1334 | assert(index == noreg || (index != base && index != to_lo), "can't handle this"); |
duke@435 | 1335 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1336 | if (patch != NULL) { |
duke@435 | 1337 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1338 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1339 | patch_code = lir_patch_high; |
duke@435 | 1340 | } |
duke@435 | 1341 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1342 | } |
never@739 | 1343 | #endif // _LP64 |
duke@435 | 1344 | break; |
duke@435 | 1345 | } |
duke@435 | 1346 | |
duke@435 | 1347 | case T_BOOLEAN: // fall through |
duke@435 | 1348 | case T_BYTE: { |
duke@435 | 1349 | Register dest_reg = dest->as_register(); |
duke@435 | 1350 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1351 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1352 | __ movsbl(dest_reg, from_addr); |
duke@435 | 1353 | } else { |
duke@435 | 1354 | __ movb(dest_reg, from_addr); |
duke@435 | 1355 | __ shll(dest_reg, 24); |
duke@435 | 1356 | __ sarl(dest_reg, 24); |
duke@435 | 1357 | } |
duke@435 | 1358 | break; |
duke@435 | 1359 | } |
duke@435 | 1360 | |
duke@435 | 1361 | case T_CHAR: { |
duke@435 | 1362 | Register dest_reg = dest->as_register(); |
duke@435 | 1363 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1364 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1365 | __ movzwl(dest_reg, from_addr); |
duke@435 | 1366 | } else { |
duke@435 | 1367 | __ movw(dest_reg, from_addr); |
duke@435 | 1368 | } |
duke@435 | 1369 | break; |
duke@435 | 1370 | } |
duke@435 | 1371 | |
duke@435 | 1372 | case T_SHORT: { |
duke@435 | 1373 | Register dest_reg = dest->as_register(); |
duke@435 | 1374 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1375 | __ movswl(dest_reg, from_addr); |
duke@435 | 1376 | } else { |
duke@435 | 1377 | __ movw(dest_reg, from_addr); |
duke@435 | 1378 | __ shll(dest_reg, 16); |
duke@435 | 1379 | __ sarl(dest_reg, 16); |
duke@435 | 1380 | } |
duke@435 | 1381 | break; |
duke@435 | 1382 | } |
duke@435 | 1383 | |
duke@435 | 1384 | default: |
duke@435 | 1385 | ShouldNotReachHere(); |
duke@435 | 1386 | } |
duke@435 | 1387 | |
duke@435 | 1388 | if (patch != NULL) { |
duke@435 | 1389 | patching_epilog(patch, patch_code, addr->base()->as_register(), info); |
duke@435 | 1390 | } |
duke@435 | 1391 | |
duke@435 | 1392 | if (type == T_ARRAY || type == T_OBJECT) { |
iveresov@2344 | 1393 | #ifdef _LP64 |
iveresov@2344 | 1394 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1395 | __ decode_heap_oop(dest->as_register()); |
iveresov@2344 | 1396 | } |
iveresov@2344 | 1397 | #endif |
duke@435 | 1398 | __ verify_oop(dest->as_register()); |
duke@435 | 1399 | } |
duke@435 | 1400 | } |
duke@435 | 1401 | |
duke@435 | 1402 | |
duke@435 | 1403 | void LIR_Assembler::prefetchr(LIR_Opr src) { |
duke@435 | 1404 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1405 | Address from_addr = as_Address(addr); |
duke@435 | 1406 | |
duke@435 | 1407 | if (VM_Version::supports_sse()) { |
duke@435 | 1408 | switch (ReadPrefetchInstr) { |
duke@435 | 1409 | case 0: |
duke@435 | 1410 | __ prefetchnta(from_addr); break; |
duke@435 | 1411 | case 1: |
duke@435 | 1412 | __ prefetcht0(from_addr); break; |
duke@435 | 1413 | case 2: |
duke@435 | 1414 | __ prefetcht2(from_addr); break; |
duke@435 | 1415 | default: |
duke@435 | 1416 | ShouldNotReachHere(); break; |
duke@435 | 1417 | } |
duke@435 | 1418 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1419 | __ prefetchr(from_addr); |
duke@435 | 1420 | } |
duke@435 | 1421 | } |
duke@435 | 1422 | |
duke@435 | 1423 | |
duke@435 | 1424 | void LIR_Assembler::prefetchw(LIR_Opr src) { |
duke@435 | 1425 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1426 | Address from_addr = as_Address(addr); |
duke@435 | 1427 | |
duke@435 | 1428 | if (VM_Version::supports_sse()) { |
duke@435 | 1429 | switch (AllocatePrefetchInstr) { |
duke@435 | 1430 | case 0: |
duke@435 | 1431 | __ prefetchnta(from_addr); break; |
duke@435 | 1432 | case 1: |
duke@435 | 1433 | __ prefetcht0(from_addr); break; |
duke@435 | 1434 | case 2: |
duke@435 | 1435 | __ prefetcht2(from_addr); break; |
duke@435 | 1436 | case 3: |
duke@435 | 1437 | __ prefetchw(from_addr); break; |
duke@435 | 1438 | default: |
duke@435 | 1439 | ShouldNotReachHere(); break; |
duke@435 | 1440 | } |
duke@435 | 1441 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1442 | __ prefetchw(from_addr); |
duke@435 | 1443 | } |
duke@435 | 1444 | } |
duke@435 | 1445 | |
duke@435 | 1446 | |
duke@435 | 1447 | NEEDS_CLEANUP; // This could be static? |
duke@435 | 1448 | Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { |
kvn@464 | 1449 | int elem_size = type2aelembytes(type); |
duke@435 | 1450 | switch (elem_size) { |
duke@435 | 1451 | case 1: return Address::times_1; |
duke@435 | 1452 | case 2: return Address::times_2; |
duke@435 | 1453 | case 4: return Address::times_4; |
duke@435 | 1454 | case 8: return Address::times_8; |
duke@435 | 1455 | } |
duke@435 | 1456 | ShouldNotReachHere(); |
duke@435 | 1457 | return Address::no_scale; |
duke@435 | 1458 | } |
duke@435 | 1459 | |
duke@435 | 1460 | |
duke@435 | 1461 | void LIR_Assembler::emit_op3(LIR_Op3* op) { |
duke@435 | 1462 | switch (op->code()) { |
duke@435 | 1463 | case lir_idiv: |
duke@435 | 1464 | case lir_irem: |
duke@435 | 1465 | arithmetic_idiv(op->code(), |
duke@435 | 1466 | op->in_opr1(), |
duke@435 | 1467 | op->in_opr2(), |
duke@435 | 1468 | op->in_opr3(), |
duke@435 | 1469 | op->result_opr(), |
duke@435 | 1470 | op->info()); |
duke@435 | 1471 | break; |
duke@435 | 1472 | default: ShouldNotReachHere(); break; |
duke@435 | 1473 | } |
duke@435 | 1474 | } |
duke@435 | 1475 | |
duke@435 | 1476 | void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
duke@435 | 1477 | #ifdef ASSERT |
duke@435 | 1478 | assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
duke@435 | 1479 | if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
duke@435 | 1480 | if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
duke@435 | 1481 | #endif |
duke@435 | 1482 | |
duke@435 | 1483 | if (op->cond() == lir_cond_always) { |
duke@435 | 1484 | if (op->info() != NULL) add_debug_info_for_branch(op->info()); |
duke@435 | 1485 | __ jmp (*(op->label())); |
duke@435 | 1486 | } else { |
duke@435 | 1487 | Assembler::Condition acond = Assembler::zero; |
duke@435 | 1488 | if (op->code() == lir_cond_float_branch) { |
duke@435 | 1489 | assert(op->ublock() != NULL, "must have unordered successor"); |
duke@435 | 1490 | __ jcc(Assembler::parity, *(op->ublock()->label())); |
duke@435 | 1491 | switch(op->cond()) { |
duke@435 | 1492 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1493 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1494 | case lir_cond_less: acond = Assembler::below; break; |
duke@435 | 1495 | case lir_cond_lessEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1496 | case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1497 | case lir_cond_greater: acond = Assembler::above; break; |
duke@435 | 1498 | default: ShouldNotReachHere(); |
duke@435 | 1499 | } |
duke@435 | 1500 | } else { |
duke@435 | 1501 | switch (op->cond()) { |
duke@435 | 1502 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1503 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1504 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 1505 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 1506 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; |
duke@435 | 1507 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 1508 | case lir_cond_belowEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1509 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1510 | default: ShouldNotReachHere(); |
duke@435 | 1511 | } |
duke@435 | 1512 | } |
duke@435 | 1513 | __ jcc(acond,*(op->label())); |
duke@435 | 1514 | } |
duke@435 | 1515 | } |
duke@435 | 1516 | |
duke@435 | 1517 | void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
duke@435 | 1518 | LIR_Opr src = op->in_opr(); |
duke@435 | 1519 | LIR_Opr dest = op->result_opr(); |
duke@435 | 1520 | |
duke@435 | 1521 | switch (op->bytecode()) { |
duke@435 | 1522 | case Bytecodes::_i2l: |
never@739 | 1523 | #ifdef _LP64 |
never@739 | 1524 | __ movl2ptr(dest->as_register_lo(), src->as_register()); |
never@739 | 1525 | #else |
duke@435 | 1526 | move_regs(src->as_register(), dest->as_register_lo()); |
duke@435 | 1527 | move_regs(src->as_register(), dest->as_register_hi()); |
duke@435 | 1528 | __ sarl(dest->as_register_hi(), 31); |
never@739 | 1529 | #endif // LP64 |
duke@435 | 1530 | break; |
duke@435 | 1531 | |
duke@435 | 1532 | case Bytecodes::_l2i: |
duke@435 | 1533 | move_regs(src->as_register_lo(), dest->as_register()); |
duke@435 | 1534 | break; |
duke@435 | 1535 | |
duke@435 | 1536 | case Bytecodes::_i2b: |
duke@435 | 1537 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1538 | __ sign_extend_byte(dest->as_register()); |
duke@435 | 1539 | break; |
duke@435 | 1540 | |
duke@435 | 1541 | case Bytecodes::_i2c: |
duke@435 | 1542 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1543 | __ andl(dest->as_register(), 0xFFFF); |
duke@435 | 1544 | break; |
duke@435 | 1545 | |
duke@435 | 1546 | case Bytecodes::_i2s: |
duke@435 | 1547 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1548 | __ sign_extend_short(dest->as_register()); |
duke@435 | 1549 | break; |
duke@435 | 1550 | |
duke@435 | 1551 | |
duke@435 | 1552 | case Bytecodes::_f2d: |
duke@435 | 1553 | case Bytecodes::_d2f: |
duke@435 | 1554 | if (dest->is_single_xmm()) { |
duke@435 | 1555 | __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); |
duke@435 | 1556 | } else if (dest->is_double_xmm()) { |
duke@435 | 1557 | __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); |
duke@435 | 1558 | } else { |
duke@435 | 1559 | assert(src->fpu() == dest->fpu(), "register must be equal"); |
duke@435 | 1560 | // do nothing (float result is rounded later through spilling) |
duke@435 | 1561 | } |
duke@435 | 1562 | break; |
duke@435 | 1563 | |
duke@435 | 1564 | case Bytecodes::_i2f: |
duke@435 | 1565 | case Bytecodes::_i2d: |
duke@435 | 1566 | if (dest->is_single_xmm()) { |
never@739 | 1567 | __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
duke@435 | 1568 | } else if (dest->is_double_xmm()) { |
never@739 | 1569 | __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
duke@435 | 1570 | } else { |
duke@435 | 1571 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1572 | __ movl(Address(rsp, 0), src->as_register()); |
duke@435 | 1573 | __ fild_s(Address(rsp, 0)); |
duke@435 | 1574 | } |
duke@435 | 1575 | break; |
duke@435 | 1576 | |
duke@435 | 1577 | case Bytecodes::_f2i: |
duke@435 | 1578 | case Bytecodes::_d2i: |
duke@435 | 1579 | if (src->is_single_xmm()) { |
never@739 | 1580 | __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
duke@435 | 1581 | } else if (src->is_double_xmm()) { |
never@739 | 1582 | __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
duke@435 | 1583 | } else { |
duke@435 | 1584 | assert(src->fpu() == 0, "input must be on TOS"); |
duke@435 | 1585 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); |
duke@435 | 1586 | __ fist_s(Address(rsp, 0)); |
duke@435 | 1587 | __ movl(dest->as_register(), Address(rsp, 0)); |
duke@435 | 1588 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 1589 | } |
duke@435 | 1590 | |
duke@435 | 1591 | // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub |
duke@435 | 1592 | assert(op->stub() != NULL, "stub required"); |
duke@435 | 1593 | __ cmpl(dest->as_register(), 0x80000000); |
duke@435 | 1594 | __ jcc(Assembler::equal, *op->stub()->entry()); |
duke@435 | 1595 | __ bind(*op->stub()->continuation()); |
duke@435 | 1596 | break; |
duke@435 | 1597 | |
duke@435 | 1598 | case Bytecodes::_l2f: |
duke@435 | 1599 | case Bytecodes::_l2d: |
duke@435 | 1600 | assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1601 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1602 | |
never@739 | 1603 | __ movptr(Address(rsp, 0), src->as_register_lo()); |
never@739 | 1604 | NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); |
duke@435 | 1605 | __ fild_d(Address(rsp, 0)); |
duke@435 | 1606 | // float result is rounded later through spilling |
duke@435 | 1607 | break; |
duke@435 | 1608 | |
duke@435 | 1609 | case Bytecodes::_f2l: |
duke@435 | 1610 | case Bytecodes::_d2l: |
duke@435 | 1611 | assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1612 | assert(src->fpu() == 0, "input must be on TOS"); |
never@739 | 1613 | assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
duke@435 | 1614 | |
duke@435 | 1615 | // instruction sequence too long to inline it here |
duke@435 | 1616 | { |
duke@435 | 1617 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); |
duke@435 | 1618 | } |
duke@435 | 1619 | break; |
duke@435 | 1620 | |
duke@435 | 1621 | default: ShouldNotReachHere(); |
duke@435 | 1622 | } |
duke@435 | 1623 | } |
duke@435 | 1624 | |
duke@435 | 1625 | void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
duke@435 | 1626 | if (op->init_check()) { |
duke@435 | 1627 | __ cmpl(Address(op->klass()->as_register(), |
duke@435 | 1628 | instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), |
duke@435 | 1629 | instanceKlass::fully_initialized); |
duke@435 | 1630 | add_debug_info_for_null_check_here(op->stub()->info()); |
duke@435 | 1631 | __ jcc(Assembler::notEqual, *op->stub()->entry()); |
duke@435 | 1632 | } |
duke@435 | 1633 | __ allocate_object(op->obj()->as_register(), |
duke@435 | 1634 | op->tmp1()->as_register(), |
duke@435 | 1635 | op->tmp2()->as_register(), |
duke@435 | 1636 | op->header_size(), |
duke@435 | 1637 | op->object_size(), |
duke@435 | 1638 | op->klass()->as_register(), |
duke@435 | 1639 | *op->stub()->entry()); |
duke@435 | 1640 | __ bind(*op->stub()->continuation()); |
duke@435 | 1641 | } |
duke@435 | 1642 | |
duke@435 | 1643 | void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
iveresov@2432 | 1644 | Register len = op->len()->as_register(); |
iveresov@2432 | 1645 | LP64_ONLY( __ movslq(len, len); ) |
iveresov@2432 | 1646 | |
duke@435 | 1647 | if (UseSlowPath || |
duke@435 | 1648 | (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
duke@435 | 1649 | (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
duke@435 | 1650 | __ jmp(*op->stub()->entry()); |
duke@435 | 1651 | } else { |
duke@435 | 1652 | Register tmp1 = op->tmp1()->as_register(); |
duke@435 | 1653 | Register tmp2 = op->tmp2()->as_register(); |
duke@435 | 1654 | Register tmp3 = op->tmp3()->as_register(); |
duke@435 | 1655 | if (len == tmp1) { |
duke@435 | 1656 | tmp1 = tmp3; |
duke@435 | 1657 | } else if (len == tmp2) { |
duke@435 | 1658 | tmp2 = tmp3; |
duke@435 | 1659 | } else if (len == tmp3) { |
duke@435 | 1660 | // everything is ok |
duke@435 | 1661 | } else { |
never@739 | 1662 | __ mov(tmp3, len); |
duke@435 | 1663 | } |
duke@435 | 1664 | __ allocate_array(op->obj()->as_register(), |
duke@435 | 1665 | len, |
duke@435 | 1666 | tmp1, |
duke@435 | 1667 | tmp2, |
duke@435 | 1668 | arrayOopDesc::header_size(op->type()), |
duke@435 | 1669 | array_element_size(op->type()), |
duke@435 | 1670 | op->klass()->as_register(), |
duke@435 | 1671 | *op->stub()->entry()); |
duke@435 | 1672 | } |
duke@435 | 1673 | __ bind(*op->stub()->continuation()); |
duke@435 | 1674 | } |
duke@435 | 1675 | |
iveresov@2138 | 1676 | void LIR_Assembler::type_profile_helper(Register mdo, |
iveresov@2138 | 1677 | ciMethodData *md, ciProfileData *data, |
iveresov@2138 | 1678 | Register recv, Label* update_done) { |
iveresov@2163 | 1679 | for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
iveresov@2138 | 1680 | Label next_test; |
iveresov@2138 | 1681 | // See if the receiver is receiver[n]. |
iveresov@2138 | 1682 | __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); |
iveresov@2138 | 1683 | __ jccb(Assembler::notEqual, next_test); |
iveresov@2138 | 1684 | Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); |
iveresov@2138 | 1685 | __ addptr(data_addr, DataLayout::counter_increment); |
iveresov@2146 | 1686 | __ jmp(*update_done); |
iveresov@2138 | 1687 | __ bind(next_test); |
iveresov@2138 | 1688 | } |
iveresov@2138 | 1689 | |
iveresov@2138 | 1690 | // Didn't find receiver; find next empty slot and fill it in |
iveresov@2163 | 1691 | for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
iveresov@2138 | 1692 | Label next_test; |
iveresov@2138 | 1693 | Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); |
iveresov@2138 | 1694 | __ cmpptr(recv_addr, (intptr_t)NULL_WORD); |
iveresov@2138 | 1695 | __ jccb(Assembler::notEqual, next_test); |
iveresov@2138 | 1696 | __ movptr(recv_addr, recv); |
iveresov@2138 | 1697 | __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); |
iveresov@2146 | 1698 | __ jmp(*update_done); |
iveresov@2138 | 1699 | __ bind(next_test); |
iveresov@2138 | 1700 | } |
iveresov@2138 | 1701 | } |
iveresov@2138 | 1702 | |
iveresov@2146 | 1703 | void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
iveresov@2138 | 1704 | // we always need a stub for the failure case. |
iveresov@2138 | 1705 | CodeStub* stub = op->stub(); |
iveresov@2138 | 1706 | Register obj = op->object()->as_register(); |
iveresov@2138 | 1707 | Register k_RInfo = op->tmp1()->as_register(); |
iveresov@2138 | 1708 | Register klass_RInfo = op->tmp2()->as_register(); |
iveresov@2138 | 1709 | Register dst = op->result_opr()->as_register(); |
iveresov@2138 | 1710 | ciKlass* k = op->klass(); |
iveresov@2138 | 1711 | Register Rtmp1 = noreg; |
iveresov@2138 | 1712 | |
iveresov@2138 | 1713 | // check if it needs to be profiled |
iveresov@2138 | 1714 | ciMethodData* md; |
iveresov@2138 | 1715 | ciProfileData* data; |
iveresov@2138 | 1716 | |
iveresov@2138 | 1717 | if (op->should_profile()) { |
iveresov@2138 | 1718 | ciMethod* method = op->profiled_method(); |
iveresov@2138 | 1719 | assert(method != NULL, "Should have method"); |
iveresov@2138 | 1720 | int bci = op->profiled_bci(); |
iveresov@2349 | 1721 | md = method->method_data_or_null(); |
iveresov@2349 | 1722 | assert(md != NULL, "Sanity"); |
iveresov@2138 | 1723 | data = md->bci_to_data(bci); |
iveresov@2146 | 1724 | assert(data != NULL, "need data for type check"); |
iveresov@2146 | 1725 | assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
iveresov@2138 | 1726 | } |
iveresov@2146 | 1727 | Label profile_cast_success, profile_cast_failure; |
iveresov@2146 | 1728 | Label *success_target = op->should_profile() ? &profile_cast_success : success; |
iveresov@2146 | 1729 | Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
iveresov@2138 | 1730 | |
iveresov@2138 | 1731 | if (obj == k_RInfo) { |
iveresov@2138 | 1732 | k_RInfo = dst; |
iveresov@2138 | 1733 | } else if (obj == klass_RInfo) { |
iveresov@2138 | 1734 | klass_RInfo = dst; |
iveresov@2138 | 1735 | } |
iveresov@2344 | 1736 | if (k->is_loaded() && !UseCompressedOops) { |
iveresov@2138 | 1737 | select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
iveresov@2138 | 1738 | } else { |
iveresov@2138 | 1739 | Rtmp1 = op->tmp3()->as_register(); |
iveresov@2138 | 1740 | select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); |
iveresov@2138 | 1741 | } |
iveresov@2138 | 1742 | |
iveresov@2138 | 1743 | assert_different_registers(obj, k_RInfo, klass_RInfo); |
iveresov@2138 | 1744 | if (!k->is_loaded()) { |
iveresov@2138 | 1745 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
iveresov@2138 | 1746 | } else { |
iveresov@2138 | 1747 | #ifdef _LP64 |
iveresov@2138 | 1748 | __ movoop(k_RInfo, k->constant_encoding()); |
iveresov@2138 | 1749 | #endif // _LP64 |
iveresov@2138 | 1750 | } |
iveresov@2138 | 1751 | assert(obj != k_RInfo, "must be different"); |
iveresov@2138 | 1752 | |
iveresov@2138 | 1753 | __ cmpptr(obj, (int32_t)NULL_WORD); |
iveresov@2138 | 1754 | if (op->should_profile()) { |
iveresov@2146 | 1755 | Label not_null; |
iveresov@2146 | 1756 | __ jccb(Assembler::notEqual, not_null); |
iveresov@2146 | 1757 | // Object is null; update MDO and exit |
iveresov@2138 | 1758 | Register mdo = klass_RInfo; |
iveresov@2138 | 1759 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2138 | 1760 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
iveresov@2138 | 1761 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
iveresov@2138 | 1762 | __ orl(data_addr, header_bits); |
iveresov@2146 | 1763 | __ jmp(*obj_is_null); |
iveresov@2146 | 1764 | __ bind(not_null); |
iveresov@2138 | 1765 | } else { |
iveresov@2146 | 1766 | __ jcc(Assembler::equal, *obj_is_null); |
iveresov@2138 | 1767 | } |
iveresov@2138 | 1768 | __ verify_oop(obj); |
iveresov@2138 | 1769 | |
iveresov@2138 | 1770 | if (op->fast_check()) { |
iveresov@2146 | 1771 | // get object class |
iveresov@2138 | 1772 | // not a safepoint as obj null check happens earlier |
iveresov@2138 | 1773 | #ifdef _LP64 |
iveresov@2344 | 1774 | if (UseCompressedOops) { |
iveresov@2344 | 1775 | __ load_klass(Rtmp1, obj); |
iveresov@2344 | 1776 | __ cmpptr(k_RInfo, Rtmp1); |
iveresov@2138 | 1777 | } else { |
iveresov@2138 | 1778 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
iveresov@2138 | 1779 | } |
iveresov@2344 | 1780 | #else |
iveresov@2344 | 1781 | if (k->is_loaded()) { |
iveresov@2344 | 1782 | __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
iveresov@2344 | 1783 | } else { |
iveresov@2344 | 1784 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
iveresov@2344 | 1785 | } |
iveresov@2344 | 1786 | #endif |
iveresov@2138 | 1787 | __ jcc(Assembler::notEqual, *failure_target); |
iveresov@2146 | 1788 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1789 | } else { |
iveresov@2138 | 1790 | // get object class |
iveresov@2138 | 1791 | // not a safepoint as obj null check happens earlier |
iveresov@2344 | 1792 | __ load_klass(klass_RInfo, obj); |
iveresov@2138 | 1793 | if (k->is_loaded()) { |
iveresov@2138 | 1794 | // See if we get an immediate positive hit |
iveresov@2138 | 1795 | #ifdef _LP64 |
iveresov@2138 | 1796 | __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); |
iveresov@2138 | 1797 | #else |
iveresov@2138 | 1798 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
iveresov@2138 | 1799 | #endif // _LP64 |
iveresov@2138 | 1800 | if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { |
iveresov@2138 | 1801 | __ jcc(Assembler::notEqual, *failure_target); |
iveresov@2146 | 1802 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1803 | } else { |
iveresov@2138 | 1804 | // See if we get an immediate positive hit |
iveresov@2146 | 1805 | __ jcc(Assembler::equal, *success_target); |
iveresov@2138 | 1806 | // check for self |
iveresov@2138 | 1807 | #ifdef _LP64 |
iveresov@2138 | 1808 | __ cmpptr(klass_RInfo, k_RInfo); |
iveresov@2138 | 1809 | #else |
iveresov@2138 | 1810 | __ cmpoop(klass_RInfo, k->constant_encoding()); |
iveresov@2138 | 1811 | #endif // _LP64 |
iveresov@2146 | 1812 | __ jcc(Assembler::equal, *success_target); |
iveresov@2138 | 1813 | |
iveresov@2138 | 1814 | __ push(klass_RInfo); |
iveresov@2138 | 1815 | #ifdef _LP64 |
iveresov@2138 | 1816 | __ push(k_RInfo); |
iveresov@2138 | 1817 | #else |
iveresov@2138 | 1818 | __ pushoop(k->constant_encoding()); |
iveresov@2138 | 1819 | #endif // _LP64 |
iveresov@2138 | 1820 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
iveresov@2138 | 1821 | __ pop(klass_RInfo); |
iveresov@2138 | 1822 | __ pop(klass_RInfo); |
iveresov@2138 | 1823 | // result is a boolean |
iveresov@2138 | 1824 | __ cmpl(klass_RInfo, 0); |
iveresov@2138 | 1825 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1826 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1827 | } |
iveresov@2138 | 1828 | } else { |
iveresov@2138 | 1829 | // perform the fast part of the checking logic |
iveresov@2146 | 1830 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
iveresov@2138 | 1831 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
iveresov@2138 | 1832 | __ push(klass_RInfo); |
iveresov@2138 | 1833 | __ push(k_RInfo); |
iveresov@2138 | 1834 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
iveresov@2138 | 1835 | __ pop(klass_RInfo); |
iveresov@2138 | 1836 | __ pop(k_RInfo); |
iveresov@2138 | 1837 | // result is a boolean |
iveresov@2138 | 1838 | __ cmpl(k_RInfo, 0); |
iveresov@2138 | 1839 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1840 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1841 | } |
iveresov@2138 | 1842 | } |
iveresov@2138 | 1843 | if (op->should_profile()) { |
iveresov@2138 | 1844 | Register mdo = klass_RInfo, recv = k_RInfo; |
iveresov@2146 | 1845 | __ bind(profile_cast_success); |
iveresov@2138 | 1846 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2344 | 1847 | __ load_klass(recv, obj); |
iveresov@2138 | 1848 | Label update_done; |
iveresov@2146 | 1849 | type_profile_helper(mdo, md, data, recv, success); |
iveresov@2146 | 1850 | __ jmp(*success); |
iveresov@2138 | 1851 | |
iveresov@2138 | 1852 | __ bind(profile_cast_failure); |
iveresov@2138 | 1853 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2138 | 1854 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
iveresov@2138 | 1855 | __ subptr(counter_addr, DataLayout::counter_increment); |
iveresov@2146 | 1856 | __ jmp(*failure); |
iveresov@2138 | 1857 | } |
iveresov@2146 | 1858 | __ jmp(*success); |
iveresov@2138 | 1859 | } |
duke@435 | 1860 | |
iveresov@2146 | 1861 | |
duke@435 | 1862 | void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
duke@435 | 1863 | LIR_Code code = op->code(); |
duke@435 | 1864 | if (code == lir_store_check) { |
duke@435 | 1865 | Register value = op->object()->as_register(); |
duke@435 | 1866 | Register array = op->array()->as_register(); |
duke@435 | 1867 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1868 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1869 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1870 | |
duke@435 | 1871 | CodeStub* stub = op->stub(); |
iveresov@2146 | 1872 | |
iveresov@2146 | 1873 | // check if it needs to be profiled |
iveresov@2146 | 1874 | ciMethodData* md; |
iveresov@2146 | 1875 | ciProfileData* data; |
iveresov@2146 | 1876 | |
iveresov@2146 | 1877 | if (op->should_profile()) { |
iveresov@2146 | 1878 | ciMethod* method = op->profiled_method(); |
iveresov@2146 | 1879 | assert(method != NULL, "Should have method"); |
iveresov@2146 | 1880 | int bci = op->profiled_bci(); |
iveresov@2349 | 1881 | md = method->method_data_or_null(); |
iveresov@2349 | 1882 | assert(md != NULL, "Sanity"); |
iveresov@2146 | 1883 | data = md->bci_to_data(bci); |
iveresov@2146 | 1884 | assert(data != NULL, "need data for type check"); |
iveresov@2146 | 1885 | assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
iveresov@2146 | 1886 | } |
iveresov@2146 | 1887 | Label profile_cast_success, profile_cast_failure, done; |
iveresov@2146 | 1888 | Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
iveresov@2146 | 1889 | Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
iveresov@2146 | 1890 | |
never@739 | 1891 | __ cmpptr(value, (int32_t)NULL_WORD); |
iveresov@2146 | 1892 | if (op->should_profile()) { |
iveresov@2146 | 1893 | Label not_null; |
iveresov@2146 | 1894 | __ jccb(Assembler::notEqual, not_null); |
iveresov@2146 | 1895 | // Object is null; update MDO and exit |
iveresov@2146 | 1896 | Register mdo = klass_RInfo; |
iveresov@2146 | 1897 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2146 | 1898 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
iveresov@2146 | 1899 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
iveresov@2146 | 1900 | __ orl(data_addr, header_bits); |
iveresov@2146 | 1901 | __ jmp(done); |
iveresov@2146 | 1902 | __ bind(not_null); |
iveresov@2146 | 1903 | } else { |
iveresov@2146 | 1904 | __ jcc(Assembler::equal, done); |
iveresov@2146 | 1905 | } |
iveresov@2146 | 1906 | |
duke@435 | 1907 | add_debug_info_for_null_check_here(op->info_for_exception()); |
iveresov@2344 | 1908 | __ load_klass(k_RInfo, array); |
iveresov@2344 | 1909 | __ load_klass(klass_RInfo, value); |
iveresov@2344 | 1910 | |
iveresov@2344 | 1911 | // get instance klass (it's already uncompressed) |
never@739 | 1912 | __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
jrose@1079 | 1913 | // perform the fast part of the checking logic |
iveresov@2146 | 1914 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
jrose@1079 | 1915 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
never@739 | 1916 | __ push(klass_RInfo); |
never@739 | 1917 | __ push(k_RInfo); |
duke@435 | 1918 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1919 | __ pop(klass_RInfo); |
never@739 | 1920 | __ pop(k_RInfo); |
never@739 | 1921 | // result is a boolean |
duke@435 | 1922 | __ cmpl(k_RInfo, 0); |
iveresov@2146 | 1923 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1924 | // fall through to the success case |
iveresov@2146 | 1925 | |
iveresov@2146 | 1926 | if (op->should_profile()) { |
iveresov@2146 | 1927 | Register mdo = klass_RInfo, recv = k_RInfo; |
iveresov@2146 | 1928 | __ bind(profile_cast_success); |
iveresov@2146 | 1929 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2344 | 1930 | __ load_klass(recv, value); |
iveresov@2146 | 1931 | Label update_done; |
iveresov@2146 | 1932 | type_profile_helper(mdo, md, data, recv, &done); |
iveresov@2146 | 1933 | __ jmpb(done); |
iveresov@2146 | 1934 | |
iveresov@2146 | 1935 | __ bind(profile_cast_failure); |
iveresov@2146 | 1936 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2146 | 1937 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
iveresov@2146 | 1938 | __ subptr(counter_addr, DataLayout::counter_increment); |
iveresov@2146 | 1939 | __ jmp(*stub->entry()); |
iveresov@2146 | 1940 | } |
iveresov@2146 | 1941 | |
duke@435 | 1942 | __ bind(done); |
iveresov@2146 | 1943 | } else |
iveresov@2146 | 1944 | if (code == lir_checkcast) { |
iveresov@2146 | 1945 | Register obj = op->object()->as_register(); |
iveresov@2146 | 1946 | Register dst = op->result_opr()->as_register(); |
iveresov@2146 | 1947 | Label success; |
iveresov@2146 | 1948 | emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
iveresov@2146 | 1949 | __ bind(success); |
iveresov@2146 | 1950 | if (dst != obj) { |
iveresov@2146 | 1951 | __ mov(dst, obj); |
iveresov@2146 | 1952 | } |
iveresov@2146 | 1953 | } else |
iveresov@2146 | 1954 | if (code == lir_instanceof) { |
iveresov@2146 | 1955 | Register obj = op->object()->as_register(); |
iveresov@2146 | 1956 | Register dst = op->result_opr()->as_register(); |
iveresov@2146 | 1957 | Label success, failure, done; |
iveresov@2146 | 1958 | emit_typecheck_helper(op, &success, &failure, &failure); |
iveresov@2146 | 1959 | __ bind(failure); |
iveresov@2146 | 1960 | __ xorptr(dst, dst); |
iveresov@2146 | 1961 | __ jmpb(done); |
iveresov@2146 | 1962 | __ bind(success); |
iveresov@2146 | 1963 | __ movptr(dst, 1); |
iveresov@2146 | 1964 | __ bind(done); |
duke@435 | 1965 | } else { |
iveresov@2146 | 1966 | ShouldNotReachHere(); |
duke@435 | 1967 | } |
duke@435 | 1968 | |
duke@435 | 1969 | } |
duke@435 | 1970 | |
duke@435 | 1971 | |
duke@435 | 1972 | void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
never@739 | 1973 | if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
duke@435 | 1974 | assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
duke@435 | 1975 | assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); |
duke@435 | 1976 | assert(op->new_value()->as_register_lo() == rbx, "wrong register"); |
duke@435 | 1977 | assert(op->new_value()->as_register_hi() == rcx, "wrong register"); |
duke@435 | 1978 | Register addr = op->addr()->as_register(); |
duke@435 | 1979 | if (os::is_MP()) { |
duke@435 | 1980 | __ lock(); |
duke@435 | 1981 | } |
never@739 | 1982 | NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
never@739 | 1983 | |
never@739 | 1984 | } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { |
never@739 | 1985 | NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) |
never@739 | 1986 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
duke@435 | 1987 | Register newval = op->new_value()->as_register(); |
duke@435 | 1988 | Register cmpval = op->cmp_value()->as_register(); |
duke@435 | 1989 | assert(cmpval == rax, "wrong register"); |
duke@435 | 1990 | assert(newval != NULL, "new val must be register"); |
duke@435 | 1991 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
duke@435 | 1992 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
duke@435 | 1993 | assert(newval != addr, "new value and addr must be in different registers"); |
iveresov@2344 | 1994 | |
never@739 | 1995 | if ( op->code() == lir_cas_obj) { |
iveresov@2344 | 1996 | #ifdef _LP64 |
iveresov@2344 | 1997 | if (UseCompressedOops) { |
iveresov@2344 | 1998 | __ encode_heap_oop(cmpval); |
iveresov@2355 | 1999 | __ mov(rscratch1, newval); |
iveresov@2355 | 2000 | __ encode_heap_oop(rscratch1); |
iveresov@2344 | 2001 | if (os::is_MP()) { |
iveresov@2344 | 2002 | __ lock(); |
iveresov@2344 | 2003 | } |
iveresov@2355 | 2004 | // cmpval (rax) is implicitly used by this instruction |
iveresov@2355 | 2005 | __ cmpxchgl(rscratch1, Address(addr, 0)); |
iveresov@2344 | 2006 | } else |
iveresov@2344 | 2007 | #endif |
iveresov@2344 | 2008 | { |
iveresov@2344 | 2009 | if (os::is_MP()) { |
iveresov@2344 | 2010 | __ lock(); |
iveresov@2344 | 2011 | } |
iveresov@2344 | 2012 | __ cmpxchgptr(newval, Address(addr, 0)); |
iveresov@2344 | 2013 | } |
iveresov@2344 | 2014 | } else { |
iveresov@2344 | 2015 | assert(op->code() == lir_cas_int, "lir_cas_int expected"); |
iveresov@2344 | 2016 | if (os::is_MP()) { |
iveresov@2344 | 2017 | __ lock(); |
iveresov@2344 | 2018 | } |
never@739 | 2019 | __ cmpxchgl(newval, Address(addr, 0)); |
never@739 | 2020 | } |
never@739 | 2021 | #ifdef _LP64 |
never@739 | 2022 | } else if (op->code() == lir_cas_long) { |
never@739 | 2023 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
never@739 | 2024 | Register newval = op->new_value()->as_register_lo(); |
never@739 | 2025 | Register cmpval = op->cmp_value()->as_register_lo(); |
never@739 | 2026 | assert(cmpval == rax, "wrong register"); |
never@739 | 2027 | assert(newval != NULL, "new val must be register"); |
never@739 | 2028 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
never@739 | 2029 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
never@739 | 2030 | assert(newval != addr, "new value and addr must be in different registers"); |
never@739 | 2031 | if (os::is_MP()) { |
never@739 | 2032 | __ lock(); |
never@739 | 2033 | } |
never@739 | 2034 | __ cmpxchgq(newval, Address(addr, 0)); |
never@739 | 2035 | #endif // _LP64 |
duke@435 | 2036 | } else { |
duke@435 | 2037 | Unimplemented(); |
duke@435 | 2038 | } |
duke@435 | 2039 | } |
duke@435 | 2040 | |
iveresov@2412 | 2041 | void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
duke@435 | 2042 | Assembler::Condition acond, ncond; |
duke@435 | 2043 | switch (condition) { |
duke@435 | 2044 | case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; |
duke@435 | 2045 | case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; |
duke@435 | 2046 | case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; |
duke@435 | 2047 | case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; |
duke@435 | 2048 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; |
duke@435 | 2049 | case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; |
duke@435 | 2050 | case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; |
duke@435 | 2051 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; |
duke@435 | 2052 | default: ShouldNotReachHere(); |
duke@435 | 2053 | } |
duke@435 | 2054 | |
duke@435 | 2055 | if (opr1->is_cpu_register()) { |
duke@435 | 2056 | reg2reg(opr1, result); |
duke@435 | 2057 | } else if (opr1->is_stack()) { |
duke@435 | 2058 | stack2reg(opr1, result, result->type()); |
duke@435 | 2059 | } else if (opr1->is_constant()) { |
duke@435 | 2060 | const2reg(opr1, result, lir_patch_none, NULL); |
duke@435 | 2061 | } else { |
duke@435 | 2062 | ShouldNotReachHere(); |
duke@435 | 2063 | } |
duke@435 | 2064 | |
duke@435 | 2065 | if (VM_Version::supports_cmov() && !opr2->is_constant()) { |
duke@435 | 2066 | // optimized version that does not require a branch |
duke@435 | 2067 | if (opr2->is_single_cpu()) { |
duke@435 | 2068 | assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); |
never@739 | 2069 | __ cmov(ncond, result->as_register(), opr2->as_register()); |
duke@435 | 2070 | } else if (opr2->is_double_cpu()) { |
duke@435 | 2071 | assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
duke@435 | 2072 | assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
never@739 | 2073 | __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
never@739 | 2074 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) |
duke@435 | 2075 | } else if (opr2->is_single_stack()) { |
duke@435 | 2076 | __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2077 | } else if (opr2->is_double_stack()) { |
never@739 | 2078 | __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
never@739 | 2079 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) |
duke@435 | 2080 | } else { |
duke@435 | 2081 | ShouldNotReachHere(); |
duke@435 | 2082 | } |
duke@435 | 2083 | |
duke@435 | 2084 | } else { |
duke@435 | 2085 | Label skip; |
duke@435 | 2086 | __ jcc (acond, skip); |
duke@435 | 2087 | if (opr2->is_cpu_register()) { |
duke@435 | 2088 | reg2reg(opr2, result); |
duke@435 | 2089 | } else if (opr2->is_stack()) { |
duke@435 | 2090 | stack2reg(opr2, result, result->type()); |
duke@435 | 2091 | } else if (opr2->is_constant()) { |
duke@435 | 2092 | const2reg(opr2, result, lir_patch_none, NULL); |
duke@435 | 2093 | } else { |
duke@435 | 2094 | ShouldNotReachHere(); |
duke@435 | 2095 | } |
duke@435 | 2096 | __ bind(skip); |
duke@435 | 2097 | } |
duke@435 | 2098 | } |
duke@435 | 2099 | |
duke@435 | 2100 | |
duke@435 | 2101 | void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
duke@435 | 2102 | assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); |
duke@435 | 2103 | |
duke@435 | 2104 | if (left->is_single_cpu()) { |
duke@435 | 2105 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2106 | Register lreg = left->as_register(); |
duke@435 | 2107 | |
duke@435 | 2108 | if (right->is_single_cpu()) { |
duke@435 | 2109 | // cpu register - cpu register |
duke@435 | 2110 | Register rreg = right->as_register(); |
duke@435 | 2111 | switch (code) { |
duke@435 | 2112 | case lir_add: __ addl (lreg, rreg); break; |
duke@435 | 2113 | case lir_sub: __ subl (lreg, rreg); break; |
duke@435 | 2114 | case lir_mul: __ imull(lreg, rreg); break; |
duke@435 | 2115 | default: ShouldNotReachHere(); |
duke@435 | 2116 | } |
duke@435 | 2117 | |
duke@435 | 2118 | } else if (right->is_stack()) { |
duke@435 | 2119 | // cpu register - stack |
duke@435 | 2120 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2121 | switch (code) { |
duke@435 | 2122 | case lir_add: __ addl(lreg, raddr); break; |
duke@435 | 2123 | case lir_sub: __ subl(lreg, raddr); break; |
duke@435 | 2124 | default: ShouldNotReachHere(); |
duke@435 | 2125 | } |
duke@435 | 2126 | |
duke@435 | 2127 | } else if (right->is_constant()) { |
duke@435 | 2128 | // cpu register - constant |
duke@435 | 2129 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2130 | switch (code) { |
duke@435 | 2131 | case lir_add: { |
iveresov@2145 | 2132 | __ incrementl(lreg, c); |
duke@435 | 2133 | break; |
duke@435 | 2134 | } |
duke@435 | 2135 | case lir_sub: { |
iveresov@2145 | 2136 | __ decrementl(lreg, c); |
duke@435 | 2137 | break; |
duke@435 | 2138 | } |
duke@435 | 2139 | default: ShouldNotReachHere(); |
duke@435 | 2140 | } |
duke@435 | 2141 | |
duke@435 | 2142 | } else { |
duke@435 | 2143 | ShouldNotReachHere(); |
duke@435 | 2144 | } |
duke@435 | 2145 | |
duke@435 | 2146 | } else if (left->is_double_cpu()) { |
duke@435 | 2147 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2148 | Register lreg_lo = left->as_register_lo(); |
duke@435 | 2149 | Register lreg_hi = left->as_register_hi(); |
duke@435 | 2150 | |
duke@435 | 2151 | if (right->is_double_cpu()) { |
duke@435 | 2152 | // cpu register - cpu register |
duke@435 | 2153 | Register rreg_lo = right->as_register_lo(); |
duke@435 | 2154 | Register rreg_hi = right->as_register_hi(); |
never@739 | 2155 | NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
never@739 | 2156 | LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); |
duke@435 | 2157 | switch (code) { |
duke@435 | 2158 | case lir_add: |
never@739 | 2159 | __ addptr(lreg_lo, rreg_lo); |
never@739 | 2160 | NOT_LP64(__ adcl(lreg_hi, rreg_hi)); |
duke@435 | 2161 | break; |
duke@435 | 2162 | case lir_sub: |
never@739 | 2163 | __ subptr(lreg_lo, rreg_lo); |
never@739 | 2164 | NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); |
duke@435 | 2165 | break; |
duke@435 | 2166 | case lir_mul: |
never@739 | 2167 | #ifdef _LP64 |
never@739 | 2168 | __ imulq(lreg_lo, rreg_lo); |
never@739 | 2169 | #else |
duke@435 | 2170 | assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
duke@435 | 2171 | __ imull(lreg_hi, rreg_lo); |
duke@435 | 2172 | __ imull(rreg_hi, lreg_lo); |
duke@435 | 2173 | __ addl (rreg_hi, lreg_hi); |
duke@435 | 2174 | __ mull (rreg_lo); |
duke@435 | 2175 | __ addl (lreg_hi, rreg_hi); |
never@739 | 2176 | #endif // _LP64 |
duke@435 | 2177 | break; |
duke@435 | 2178 | default: |
duke@435 | 2179 | ShouldNotReachHere(); |
duke@435 | 2180 | } |
duke@435 | 2181 | |
duke@435 | 2182 | } else if (right->is_constant()) { |
duke@435 | 2183 | // cpu register - constant |
never@739 | 2184 | #ifdef _LP64 |
never@739 | 2185 | jlong c = right->as_constant_ptr()->as_jlong_bits(); |
never@739 | 2186 | __ movptr(r10, (intptr_t) c); |
never@739 | 2187 | switch (code) { |
never@739 | 2188 | case lir_add: |
never@739 | 2189 | __ addptr(lreg_lo, r10); |
never@739 | 2190 | break; |
never@739 | 2191 | case lir_sub: |
never@739 | 2192 | __ subptr(lreg_lo, r10); |
never@739 | 2193 | break; |
never@739 | 2194 | default: |
never@739 | 2195 | ShouldNotReachHere(); |
never@739 | 2196 | } |
never@739 | 2197 | #else |
duke@435 | 2198 | jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2199 | jint c_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2200 | switch (code) { |
duke@435 | 2201 | case lir_add: |
never@739 | 2202 | __ addptr(lreg_lo, c_lo); |
duke@435 | 2203 | __ adcl(lreg_hi, c_hi); |
duke@435 | 2204 | break; |
duke@435 | 2205 | case lir_sub: |
never@739 | 2206 | __ subptr(lreg_lo, c_lo); |
duke@435 | 2207 | __ sbbl(lreg_hi, c_hi); |
duke@435 | 2208 | break; |
duke@435 | 2209 | default: |
duke@435 | 2210 | ShouldNotReachHere(); |
duke@435 | 2211 | } |
never@739 | 2212 | #endif // _LP64 |
duke@435 | 2213 | |
duke@435 | 2214 | } else { |
duke@435 | 2215 | ShouldNotReachHere(); |
duke@435 | 2216 | } |
duke@435 | 2217 | |
duke@435 | 2218 | } else if (left->is_single_xmm()) { |
duke@435 | 2219 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2220 | XMMRegister lreg = left->as_xmm_float_reg(); |
duke@435 | 2221 | |
duke@435 | 2222 | if (right->is_single_xmm()) { |
duke@435 | 2223 | XMMRegister rreg = right->as_xmm_float_reg(); |
duke@435 | 2224 | switch (code) { |
duke@435 | 2225 | case lir_add: __ addss(lreg, rreg); break; |
duke@435 | 2226 | case lir_sub: __ subss(lreg, rreg); break; |
duke@435 | 2227 | case lir_mul_strictfp: // fall through |
duke@435 | 2228 | case lir_mul: __ mulss(lreg, rreg); break; |
duke@435 | 2229 | case lir_div_strictfp: // fall through |
duke@435 | 2230 | case lir_div: __ divss(lreg, rreg); break; |
duke@435 | 2231 | default: ShouldNotReachHere(); |
duke@435 | 2232 | } |
duke@435 | 2233 | } else { |
duke@435 | 2234 | Address raddr; |
duke@435 | 2235 | if (right->is_single_stack()) { |
duke@435 | 2236 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2237 | } else if (right->is_constant()) { |
duke@435 | 2238 | // hack for now |
duke@435 | 2239 | raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); |
duke@435 | 2240 | } else { |
duke@435 | 2241 | ShouldNotReachHere(); |
duke@435 | 2242 | } |
duke@435 | 2243 | switch (code) { |
duke@435 | 2244 | case lir_add: __ addss(lreg, raddr); break; |
duke@435 | 2245 | case lir_sub: __ subss(lreg, raddr); break; |
duke@435 | 2246 | case lir_mul_strictfp: // fall through |
duke@435 | 2247 | case lir_mul: __ mulss(lreg, raddr); break; |
duke@435 | 2248 | case lir_div_strictfp: // fall through |
duke@435 | 2249 | case lir_div: __ divss(lreg, raddr); break; |
duke@435 | 2250 | default: ShouldNotReachHere(); |
duke@435 | 2251 | } |
duke@435 | 2252 | } |
duke@435 | 2253 | |
duke@435 | 2254 | } else if (left->is_double_xmm()) { |
duke@435 | 2255 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2256 | |
duke@435 | 2257 | XMMRegister lreg = left->as_xmm_double_reg(); |
duke@435 | 2258 | if (right->is_double_xmm()) { |
duke@435 | 2259 | XMMRegister rreg = right->as_xmm_double_reg(); |
duke@435 | 2260 | switch (code) { |
duke@435 | 2261 | case lir_add: __ addsd(lreg, rreg); break; |
duke@435 | 2262 | case lir_sub: __ subsd(lreg, rreg); break; |
duke@435 | 2263 | case lir_mul_strictfp: // fall through |
duke@435 | 2264 | case lir_mul: __ mulsd(lreg, rreg); break; |
duke@435 | 2265 | case lir_div_strictfp: // fall through |
duke@435 | 2266 | case lir_div: __ divsd(lreg, rreg); break; |
duke@435 | 2267 | default: ShouldNotReachHere(); |
duke@435 | 2268 | } |
duke@435 | 2269 | } else { |
duke@435 | 2270 | Address raddr; |
duke@435 | 2271 | if (right->is_double_stack()) { |
duke@435 | 2272 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2273 | } else if (right->is_constant()) { |
duke@435 | 2274 | // hack for now |
duke@435 | 2275 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2276 | } else { |
duke@435 | 2277 | ShouldNotReachHere(); |
duke@435 | 2278 | } |
duke@435 | 2279 | switch (code) { |
duke@435 | 2280 | case lir_add: __ addsd(lreg, raddr); break; |
duke@435 | 2281 | case lir_sub: __ subsd(lreg, raddr); break; |
duke@435 | 2282 | case lir_mul_strictfp: // fall through |
duke@435 | 2283 | case lir_mul: __ mulsd(lreg, raddr); break; |
duke@435 | 2284 | case lir_div_strictfp: // fall through |
duke@435 | 2285 | case lir_div: __ divsd(lreg, raddr); break; |
duke@435 | 2286 | default: ShouldNotReachHere(); |
duke@435 | 2287 | } |
duke@435 | 2288 | } |
duke@435 | 2289 | |
duke@435 | 2290 | } else if (left->is_single_fpu()) { |
duke@435 | 2291 | assert(dest->is_single_fpu(), "fpu stack allocation required"); |
duke@435 | 2292 | |
duke@435 | 2293 | if (right->is_single_fpu()) { |
duke@435 | 2294 | arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); |
duke@435 | 2295 | |
duke@435 | 2296 | } else { |
duke@435 | 2297 | assert(left->fpu_regnr() == 0, "left must be on TOS"); |
duke@435 | 2298 | assert(dest->fpu_regnr() == 0, "dest must be on TOS"); |
duke@435 | 2299 | |
duke@435 | 2300 | Address raddr; |
duke@435 | 2301 | if (right->is_single_stack()) { |
duke@435 | 2302 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2303 | } else if (right->is_constant()) { |
duke@435 | 2304 | address const_addr = float_constant(right->as_jfloat()); |
duke@435 | 2305 | assert(const_addr != NULL, "incorrect float/double constant maintainance"); |
duke@435 | 2306 | // hack for now |
duke@435 | 2307 | raddr = __ as_Address(InternalAddress(const_addr)); |
duke@435 | 2308 | } else { |
duke@435 | 2309 | ShouldNotReachHere(); |
duke@435 | 2310 | } |
duke@435 | 2311 | |
duke@435 | 2312 | switch (code) { |
duke@435 | 2313 | case lir_add: __ fadd_s(raddr); break; |
duke@435 | 2314 | case lir_sub: __ fsub_s(raddr); break; |
duke@435 | 2315 | case lir_mul_strictfp: // fall through |
duke@435 | 2316 | case lir_mul: __ fmul_s(raddr); break; |
duke@435 | 2317 | case lir_div_strictfp: // fall through |
duke@435 | 2318 | case lir_div: __ fdiv_s(raddr); break; |
duke@435 | 2319 | default: ShouldNotReachHere(); |
duke@435 | 2320 | } |
duke@435 | 2321 | } |
duke@435 | 2322 | |
duke@435 | 2323 | } else if (left->is_double_fpu()) { |
duke@435 | 2324 | assert(dest->is_double_fpu(), "fpu stack allocation required"); |
duke@435 | 2325 | |
duke@435 | 2326 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2327 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2328 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); |
duke@435 | 2329 | __ fmulp(left->fpu_regnrLo() + 1); |
duke@435 | 2330 | } |
duke@435 | 2331 | |
duke@435 | 2332 | if (right->is_double_fpu()) { |
duke@435 | 2333 | arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); |
duke@435 | 2334 | |
duke@435 | 2335 | } else { |
duke@435 | 2336 | assert(left->fpu_regnrLo() == 0, "left must be on TOS"); |
duke@435 | 2337 | assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); |
duke@435 | 2338 | |
duke@435 | 2339 | Address raddr; |
duke@435 | 2340 | if (right->is_double_stack()) { |
duke@435 | 2341 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2342 | } else if (right->is_constant()) { |
duke@435 | 2343 | // hack for now |
duke@435 | 2344 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2345 | } else { |
duke@435 | 2346 | ShouldNotReachHere(); |
duke@435 | 2347 | } |
duke@435 | 2348 | |
duke@435 | 2349 | switch (code) { |
duke@435 | 2350 | case lir_add: __ fadd_d(raddr); break; |
duke@435 | 2351 | case lir_sub: __ fsub_d(raddr); break; |
duke@435 | 2352 | case lir_mul_strictfp: // fall through |
duke@435 | 2353 | case lir_mul: __ fmul_d(raddr); break; |
duke@435 | 2354 | case lir_div_strictfp: // fall through |
duke@435 | 2355 | case lir_div: __ fdiv_d(raddr); break; |
duke@435 | 2356 | default: ShouldNotReachHere(); |
duke@435 | 2357 | } |
duke@435 | 2358 | } |
duke@435 | 2359 | |
duke@435 | 2360 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2361 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2362 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); |
duke@435 | 2363 | __ fmulp(dest->fpu_regnrLo() + 1); |
duke@435 | 2364 | } |
duke@435 | 2365 | |
duke@435 | 2366 | } else if (left->is_single_stack() || left->is_address()) { |
duke@435 | 2367 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2368 | |
duke@435 | 2369 | Address laddr; |
duke@435 | 2370 | if (left->is_single_stack()) { |
duke@435 | 2371 | laddr = frame_map()->address_for_slot(left->single_stack_ix()); |
duke@435 | 2372 | } else if (left->is_address()) { |
duke@435 | 2373 | laddr = as_Address(left->as_address_ptr()); |
duke@435 | 2374 | } else { |
duke@435 | 2375 | ShouldNotReachHere(); |
duke@435 | 2376 | } |
duke@435 | 2377 | |
duke@435 | 2378 | if (right->is_single_cpu()) { |
duke@435 | 2379 | Register rreg = right->as_register(); |
duke@435 | 2380 | switch (code) { |
duke@435 | 2381 | case lir_add: __ addl(laddr, rreg); break; |
duke@435 | 2382 | case lir_sub: __ subl(laddr, rreg); break; |
duke@435 | 2383 | default: ShouldNotReachHere(); |
duke@435 | 2384 | } |
duke@435 | 2385 | } else if (right->is_constant()) { |
duke@435 | 2386 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2387 | switch (code) { |
duke@435 | 2388 | case lir_add: { |
never@739 | 2389 | __ incrementl(laddr, c); |
duke@435 | 2390 | break; |
duke@435 | 2391 | } |
duke@435 | 2392 | case lir_sub: { |
never@739 | 2393 | __ decrementl(laddr, c); |
duke@435 | 2394 | break; |
duke@435 | 2395 | } |
duke@435 | 2396 | default: ShouldNotReachHere(); |
duke@435 | 2397 | } |
duke@435 | 2398 | } else { |
duke@435 | 2399 | ShouldNotReachHere(); |
duke@435 | 2400 | } |
duke@435 | 2401 | |
duke@435 | 2402 | } else { |
duke@435 | 2403 | ShouldNotReachHere(); |
duke@435 | 2404 | } |
duke@435 | 2405 | } |
duke@435 | 2406 | |
duke@435 | 2407 | void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { |
duke@435 | 2408 | assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); |
duke@435 | 2409 | assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); |
duke@435 | 2410 | assert(left_index == 0 || right_index == 0, "either must be on top of stack"); |
duke@435 | 2411 | |
duke@435 | 2412 | bool left_is_tos = (left_index == 0); |
duke@435 | 2413 | bool dest_is_tos = (dest_index == 0); |
duke@435 | 2414 | int non_tos_index = (left_is_tos ? right_index : left_index); |
duke@435 | 2415 | |
duke@435 | 2416 | switch (code) { |
duke@435 | 2417 | case lir_add: |
duke@435 | 2418 | if (pop_fpu_stack) __ faddp(non_tos_index); |
duke@435 | 2419 | else if (dest_is_tos) __ fadd (non_tos_index); |
duke@435 | 2420 | else __ fadda(non_tos_index); |
duke@435 | 2421 | break; |
duke@435 | 2422 | |
duke@435 | 2423 | case lir_sub: |
duke@435 | 2424 | if (left_is_tos) { |
duke@435 | 2425 | if (pop_fpu_stack) __ fsubrp(non_tos_index); |
duke@435 | 2426 | else if (dest_is_tos) __ fsub (non_tos_index); |
duke@435 | 2427 | else __ fsubra(non_tos_index); |
duke@435 | 2428 | } else { |
duke@435 | 2429 | if (pop_fpu_stack) __ fsubp (non_tos_index); |
duke@435 | 2430 | else if (dest_is_tos) __ fsubr (non_tos_index); |
duke@435 | 2431 | else __ fsuba (non_tos_index); |
duke@435 | 2432 | } |
duke@435 | 2433 | break; |
duke@435 | 2434 | |
duke@435 | 2435 | case lir_mul_strictfp: // fall through |
duke@435 | 2436 | case lir_mul: |
duke@435 | 2437 | if (pop_fpu_stack) __ fmulp(non_tos_index); |
duke@435 | 2438 | else if (dest_is_tos) __ fmul (non_tos_index); |
duke@435 | 2439 | else __ fmula(non_tos_index); |
duke@435 | 2440 | break; |
duke@435 | 2441 | |
duke@435 | 2442 | case lir_div_strictfp: // fall through |
duke@435 | 2443 | case lir_div: |
duke@435 | 2444 | if (left_is_tos) { |
duke@435 | 2445 | if (pop_fpu_stack) __ fdivrp(non_tos_index); |
duke@435 | 2446 | else if (dest_is_tos) __ fdiv (non_tos_index); |
duke@435 | 2447 | else __ fdivra(non_tos_index); |
duke@435 | 2448 | } else { |
duke@435 | 2449 | if (pop_fpu_stack) __ fdivp (non_tos_index); |
duke@435 | 2450 | else if (dest_is_tos) __ fdivr (non_tos_index); |
duke@435 | 2451 | else __ fdiva (non_tos_index); |
duke@435 | 2452 | } |
duke@435 | 2453 | break; |
duke@435 | 2454 | |
duke@435 | 2455 | case lir_rem: |
duke@435 | 2456 | assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); |
duke@435 | 2457 | __ fremr(noreg); |
duke@435 | 2458 | break; |
duke@435 | 2459 | |
duke@435 | 2460 | default: |
duke@435 | 2461 | ShouldNotReachHere(); |
duke@435 | 2462 | } |
duke@435 | 2463 | } |
duke@435 | 2464 | |
duke@435 | 2465 | |
duke@435 | 2466 | void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { |
duke@435 | 2467 | if (value->is_double_xmm()) { |
duke@435 | 2468 | switch(code) { |
duke@435 | 2469 | case lir_abs : |
duke@435 | 2470 | { |
duke@435 | 2471 | if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { |
duke@435 | 2472 | __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); |
duke@435 | 2473 | } |
duke@435 | 2474 | __ andpd(dest->as_xmm_double_reg(), |
duke@435 | 2475 | ExternalAddress((address)double_signmask_pool)); |
duke@435 | 2476 | } |
duke@435 | 2477 | break; |
duke@435 | 2478 | |
duke@435 | 2479 | case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; |
duke@435 | 2480 | // all other intrinsics are not available in the SSE instruction set, so FPU is used |
duke@435 | 2481 | default : ShouldNotReachHere(); |
duke@435 | 2482 | } |
duke@435 | 2483 | |
duke@435 | 2484 | } else if (value->is_double_fpu()) { |
duke@435 | 2485 | assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); |
duke@435 | 2486 | switch(code) { |
duke@435 | 2487 | case lir_log : __ flog() ; break; |
duke@435 | 2488 | case lir_log10 : __ flog10() ; break; |
duke@435 | 2489 | case lir_abs : __ fabs() ; break; |
duke@435 | 2490 | case lir_sqrt : __ fsqrt(); break; |
duke@435 | 2491 | case lir_sin : |
duke@435 | 2492 | // Should consider not saving rbx, if not necessary |
duke@435 | 2493 | __ trigfunc('s', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2494 | break; |
duke@435 | 2495 | case lir_cos : |
duke@435 | 2496 | // Should consider not saving rbx, if not necessary |
duke@435 | 2497 | assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); |
duke@435 | 2498 | __ trigfunc('c', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2499 | break; |
duke@435 | 2500 | case lir_tan : |
duke@435 | 2501 | // Should consider not saving rbx, if not necessary |
duke@435 | 2502 | __ trigfunc('t', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2503 | break; |
duke@435 | 2504 | default : ShouldNotReachHere(); |
duke@435 | 2505 | } |
duke@435 | 2506 | } else { |
duke@435 | 2507 | Unimplemented(); |
duke@435 | 2508 | } |
duke@435 | 2509 | } |
duke@435 | 2510 | |
duke@435 | 2511 | void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
duke@435 | 2512 | // assert(left->destroys_register(), "check"); |
duke@435 | 2513 | if (left->is_single_cpu()) { |
duke@435 | 2514 | Register reg = left->as_register(); |
duke@435 | 2515 | if (right->is_constant()) { |
duke@435 | 2516 | int val = right->as_constant_ptr()->as_jint(); |
duke@435 | 2517 | switch (code) { |
duke@435 | 2518 | case lir_logic_and: __ andl (reg, val); break; |
duke@435 | 2519 | case lir_logic_or: __ orl (reg, val); break; |
duke@435 | 2520 | case lir_logic_xor: __ xorl (reg, val); break; |
duke@435 | 2521 | default: ShouldNotReachHere(); |
duke@435 | 2522 | } |
duke@435 | 2523 | } else if (right->is_stack()) { |
duke@435 | 2524 | // added support for stack operands |
duke@435 | 2525 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2526 | switch (code) { |
duke@435 | 2527 | case lir_logic_and: __ andl (reg, raddr); break; |
duke@435 | 2528 | case lir_logic_or: __ orl (reg, raddr); break; |
duke@435 | 2529 | case lir_logic_xor: __ xorl (reg, raddr); break; |
duke@435 | 2530 | default: ShouldNotReachHere(); |
duke@435 | 2531 | } |
duke@435 | 2532 | } else { |
duke@435 | 2533 | Register rright = right->as_register(); |
duke@435 | 2534 | switch (code) { |
never@739 | 2535 | case lir_logic_and: __ andptr (reg, rright); break; |
never@739 | 2536 | case lir_logic_or : __ orptr (reg, rright); break; |
never@739 | 2537 | case lir_logic_xor: __ xorptr (reg, rright); break; |
duke@435 | 2538 | default: ShouldNotReachHere(); |
duke@435 | 2539 | } |
duke@435 | 2540 | } |
duke@435 | 2541 | move_regs(reg, dst->as_register()); |
duke@435 | 2542 | } else { |
duke@435 | 2543 | Register l_lo = left->as_register_lo(); |
duke@435 | 2544 | Register l_hi = left->as_register_hi(); |
duke@435 | 2545 | if (right->is_constant()) { |
never@739 | 2546 | #ifdef _LP64 |
never@739 | 2547 | __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); |
never@739 | 2548 | switch (code) { |
never@739 | 2549 | case lir_logic_and: |
never@739 | 2550 | __ andq(l_lo, rscratch1); |
never@739 | 2551 | break; |
never@739 | 2552 | case lir_logic_or: |
never@739 | 2553 | __ orq(l_lo, rscratch1); |
never@739 | 2554 | break; |
never@739 | 2555 | case lir_logic_xor: |
never@739 | 2556 | __ xorq(l_lo, rscratch1); |
never@739 | 2557 | break; |
never@739 | 2558 | default: ShouldNotReachHere(); |
never@739 | 2559 | } |
never@739 | 2560 | #else |
duke@435 | 2561 | int r_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2562 | int r_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2563 | switch (code) { |
duke@435 | 2564 | case lir_logic_and: |
duke@435 | 2565 | __ andl(l_lo, r_lo); |
duke@435 | 2566 | __ andl(l_hi, r_hi); |
duke@435 | 2567 | break; |
duke@435 | 2568 | case lir_logic_or: |
duke@435 | 2569 | __ orl(l_lo, r_lo); |
duke@435 | 2570 | __ orl(l_hi, r_hi); |
duke@435 | 2571 | break; |
duke@435 | 2572 | case lir_logic_xor: |
duke@435 | 2573 | __ xorl(l_lo, r_lo); |
duke@435 | 2574 | __ xorl(l_hi, r_hi); |
duke@435 | 2575 | break; |
duke@435 | 2576 | default: ShouldNotReachHere(); |
duke@435 | 2577 | } |
never@739 | 2578 | #endif // _LP64 |
duke@435 | 2579 | } else { |
iveresov@1927 | 2580 | #ifdef _LP64 |
iveresov@1927 | 2581 | Register r_lo; |
iveresov@1927 | 2582 | if (right->type() == T_OBJECT || right->type() == T_ARRAY) { |
iveresov@1927 | 2583 | r_lo = right->as_register(); |
iveresov@1927 | 2584 | } else { |
iveresov@1927 | 2585 | r_lo = right->as_register_lo(); |
iveresov@1927 | 2586 | } |
iveresov@1927 | 2587 | #else |
duke@435 | 2588 | Register r_lo = right->as_register_lo(); |
duke@435 | 2589 | Register r_hi = right->as_register_hi(); |
duke@435 | 2590 | assert(l_lo != r_hi, "overwriting registers"); |
iveresov@1927 | 2591 | #endif |
duke@435 | 2592 | switch (code) { |
duke@435 | 2593 | case lir_logic_and: |
never@739 | 2594 | __ andptr(l_lo, r_lo); |
never@739 | 2595 | NOT_LP64(__ andptr(l_hi, r_hi);) |
duke@435 | 2596 | break; |
duke@435 | 2597 | case lir_logic_or: |
never@739 | 2598 | __ orptr(l_lo, r_lo); |
never@739 | 2599 | NOT_LP64(__ orptr(l_hi, r_hi);) |
duke@435 | 2600 | break; |
duke@435 | 2601 | case lir_logic_xor: |
never@739 | 2602 | __ xorptr(l_lo, r_lo); |
never@739 | 2603 | NOT_LP64(__ xorptr(l_hi, r_hi);) |
duke@435 | 2604 | break; |
duke@435 | 2605 | default: ShouldNotReachHere(); |
duke@435 | 2606 | } |
duke@435 | 2607 | } |
duke@435 | 2608 | |
duke@435 | 2609 | Register dst_lo = dst->as_register_lo(); |
duke@435 | 2610 | Register dst_hi = dst->as_register_hi(); |
duke@435 | 2611 | |
never@739 | 2612 | #ifdef _LP64 |
never@739 | 2613 | move_regs(l_lo, dst_lo); |
never@739 | 2614 | #else |
duke@435 | 2615 | if (dst_lo == l_hi) { |
duke@435 | 2616 | assert(dst_hi != l_lo, "overwriting registers"); |
duke@435 | 2617 | move_regs(l_hi, dst_hi); |
duke@435 | 2618 | move_regs(l_lo, dst_lo); |
duke@435 | 2619 | } else { |
duke@435 | 2620 | assert(dst_lo != l_hi, "overwriting registers"); |
duke@435 | 2621 | move_regs(l_lo, dst_lo); |
duke@435 | 2622 | move_regs(l_hi, dst_hi); |
duke@435 | 2623 | } |
never@739 | 2624 | #endif // _LP64 |
duke@435 | 2625 | } |
duke@435 | 2626 | } |
duke@435 | 2627 | |
duke@435 | 2628 | |
duke@435 | 2629 | // we assume that rax, and rdx can be overwritten |
duke@435 | 2630 | void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { |
duke@435 | 2631 | |
duke@435 | 2632 | assert(left->is_single_cpu(), "left must be register"); |
duke@435 | 2633 | assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); |
duke@435 | 2634 | assert(result->is_single_cpu(), "result must be register"); |
duke@435 | 2635 | |
duke@435 | 2636 | // assert(left->destroys_register(), "check"); |
duke@435 | 2637 | // assert(right->destroys_register(), "check"); |
duke@435 | 2638 | |
duke@435 | 2639 | Register lreg = left->as_register(); |
duke@435 | 2640 | Register dreg = result->as_register(); |
duke@435 | 2641 | |
duke@435 | 2642 | if (right->is_constant()) { |
duke@435 | 2643 | int divisor = right->as_constant_ptr()->as_jint(); |
duke@435 | 2644 | assert(divisor > 0 && is_power_of_2(divisor), "must be"); |
duke@435 | 2645 | if (code == lir_idiv) { |
duke@435 | 2646 | assert(lreg == rax, "must be rax,"); |
duke@435 | 2647 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2648 | __ cdql(); // sign extend into rdx:rax |
duke@435 | 2649 | if (divisor == 2) { |
duke@435 | 2650 | __ subl(lreg, rdx); |
duke@435 | 2651 | } else { |
duke@435 | 2652 | __ andl(rdx, divisor - 1); |
duke@435 | 2653 | __ addl(lreg, rdx); |
duke@435 | 2654 | } |
duke@435 | 2655 | __ sarl(lreg, log2_intptr(divisor)); |
duke@435 | 2656 | move_regs(lreg, dreg); |
duke@435 | 2657 | } else if (code == lir_irem) { |
duke@435 | 2658 | Label done; |
never@739 | 2659 | __ mov(dreg, lreg); |
duke@435 | 2660 | __ andl(dreg, 0x80000000 | (divisor - 1)); |
duke@435 | 2661 | __ jcc(Assembler::positive, done); |
duke@435 | 2662 | __ decrement(dreg); |
duke@435 | 2663 | __ orl(dreg, ~(divisor - 1)); |
duke@435 | 2664 | __ increment(dreg); |
duke@435 | 2665 | __ bind(done); |
duke@435 | 2666 | } else { |
duke@435 | 2667 | ShouldNotReachHere(); |
duke@435 | 2668 | } |
duke@435 | 2669 | } else { |
duke@435 | 2670 | Register rreg = right->as_register(); |
duke@435 | 2671 | assert(lreg == rax, "left register must be rax,"); |
duke@435 | 2672 | assert(rreg != rdx, "right register must not be rdx"); |
duke@435 | 2673 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2674 | |
duke@435 | 2675 | move_regs(lreg, rax); |
duke@435 | 2676 | |
duke@435 | 2677 | int idivl_offset = __ corrected_idivl(rreg); |
duke@435 | 2678 | add_debug_info_for_div0(idivl_offset, info); |
duke@435 | 2679 | if (code == lir_irem) { |
duke@435 | 2680 | move_regs(rdx, dreg); // result is in rdx |
duke@435 | 2681 | } else { |
duke@435 | 2682 | move_regs(rax, dreg); |
duke@435 | 2683 | } |
duke@435 | 2684 | } |
duke@435 | 2685 | } |
duke@435 | 2686 | |
duke@435 | 2687 | |
duke@435 | 2688 | void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
duke@435 | 2689 | if (opr1->is_single_cpu()) { |
duke@435 | 2690 | Register reg1 = opr1->as_register(); |
duke@435 | 2691 | if (opr2->is_single_cpu()) { |
duke@435 | 2692 | // cpu register - cpu register |
never@739 | 2693 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2694 | __ cmpptr(reg1, opr2->as_register()); |
never@739 | 2695 | } else { |
never@739 | 2696 | assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
never@739 | 2697 | __ cmpl(reg1, opr2->as_register()); |
never@739 | 2698 | } |
duke@435 | 2699 | } else if (opr2->is_stack()) { |
duke@435 | 2700 | // cpu register - stack |
never@739 | 2701 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2702 | __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2703 | } else { |
never@739 | 2704 | __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2705 | } |
duke@435 | 2706 | } else if (opr2->is_constant()) { |
duke@435 | 2707 | // cpu register - constant |
duke@435 | 2708 | LIR_Const* c = opr2->as_constant_ptr(); |
duke@435 | 2709 | if (c->type() == T_INT) { |
duke@435 | 2710 | __ cmpl(reg1, c->as_jint()); |
never@739 | 2711 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2712 | // In 64bit oops are single register |
duke@435 | 2713 | jobject o = c->as_jobject(); |
duke@435 | 2714 | if (o == NULL) { |
never@739 | 2715 | __ cmpptr(reg1, (int32_t)NULL_WORD); |
duke@435 | 2716 | } else { |
never@739 | 2717 | #ifdef _LP64 |
never@739 | 2718 | __ movoop(rscratch1, o); |
never@739 | 2719 | __ cmpptr(reg1, rscratch1); |
never@739 | 2720 | #else |
duke@435 | 2721 | __ cmpoop(reg1, c->as_jobject()); |
never@739 | 2722 | #endif // _LP64 |
duke@435 | 2723 | } |
duke@435 | 2724 | } else { |
duke@435 | 2725 | ShouldNotReachHere(); |
duke@435 | 2726 | } |
duke@435 | 2727 | // cpu register - address |
duke@435 | 2728 | } else if (opr2->is_address()) { |
duke@435 | 2729 | if (op->info() != NULL) { |
duke@435 | 2730 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2731 | } |
duke@435 | 2732 | __ cmpl(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2733 | } else { |
duke@435 | 2734 | ShouldNotReachHere(); |
duke@435 | 2735 | } |
duke@435 | 2736 | |
duke@435 | 2737 | } else if(opr1->is_double_cpu()) { |
duke@435 | 2738 | Register xlo = opr1->as_register_lo(); |
duke@435 | 2739 | Register xhi = opr1->as_register_hi(); |
duke@435 | 2740 | if (opr2->is_double_cpu()) { |
never@739 | 2741 | #ifdef _LP64 |
never@739 | 2742 | __ cmpptr(xlo, opr2->as_register_lo()); |
never@739 | 2743 | #else |
duke@435 | 2744 | // cpu register - cpu register |
duke@435 | 2745 | Register ylo = opr2->as_register_lo(); |
duke@435 | 2746 | Register yhi = opr2->as_register_hi(); |
duke@435 | 2747 | __ subl(xlo, ylo); |
duke@435 | 2748 | __ sbbl(xhi, yhi); |
duke@435 | 2749 | if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
duke@435 | 2750 | __ orl(xhi, xlo); |
duke@435 | 2751 | } |
never@739 | 2752 | #endif // _LP64 |
duke@435 | 2753 | } else if (opr2->is_constant()) { |
duke@435 | 2754 | // cpu register - constant 0 |
duke@435 | 2755 | assert(opr2->as_jlong() == (jlong)0, "only handles zero"); |
never@739 | 2756 | #ifdef _LP64 |
never@739 | 2757 | __ cmpptr(xlo, (int32_t)opr2->as_jlong()); |
never@739 | 2758 | #else |
duke@435 | 2759 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
duke@435 | 2760 | __ orl(xhi, xlo); |
never@739 | 2761 | #endif // _LP64 |
duke@435 | 2762 | } else { |
duke@435 | 2763 | ShouldNotReachHere(); |
duke@435 | 2764 | } |
duke@435 | 2765 | |
duke@435 | 2766 | } else if (opr1->is_single_xmm()) { |
duke@435 | 2767 | XMMRegister reg1 = opr1->as_xmm_float_reg(); |
duke@435 | 2768 | if (opr2->is_single_xmm()) { |
duke@435 | 2769 | // xmm register - xmm register |
duke@435 | 2770 | __ ucomiss(reg1, opr2->as_xmm_float_reg()); |
duke@435 | 2771 | } else if (opr2->is_stack()) { |
duke@435 | 2772 | // xmm register - stack |
duke@435 | 2773 | __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2774 | } else if (opr2->is_constant()) { |
duke@435 | 2775 | // xmm register - constant |
duke@435 | 2776 | __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); |
duke@435 | 2777 | } else if (opr2->is_address()) { |
duke@435 | 2778 | // xmm register - address |
duke@435 | 2779 | if (op->info() != NULL) { |
duke@435 | 2780 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2781 | } |
duke@435 | 2782 | __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2783 | } else { |
duke@435 | 2784 | ShouldNotReachHere(); |
duke@435 | 2785 | } |
duke@435 | 2786 | |
duke@435 | 2787 | } else if (opr1->is_double_xmm()) { |
duke@435 | 2788 | XMMRegister reg1 = opr1->as_xmm_double_reg(); |
duke@435 | 2789 | if (opr2->is_double_xmm()) { |
duke@435 | 2790 | // xmm register - xmm register |
duke@435 | 2791 | __ ucomisd(reg1, opr2->as_xmm_double_reg()); |
duke@435 | 2792 | } else if (opr2->is_stack()) { |
duke@435 | 2793 | // xmm register - stack |
duke@435 | 2794 | __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); |
duke@435 | 2795 | } else if (opr2->is_constant()) { |
duke@435 | 2796 | // xmm register - constant |
duke@435 | 2797 | __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); |
duke@435 | 2798 | } else if (opr2->is_address()) { |
duke@435 | 2799 | // xmm register - address |
duke@435 | 2800 | if (op->info() != NULL) { |
duke@435 | 2801 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2802 | } |
duke@435 | 2803 | __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); |
duke@435 | 2804 | } else { |
duke@435 | 2805 | ShouldNotReachHere(); |
duke@435 | 2806 | } |
duke@435 | 2807 | |
duke@435 | 2808 | } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { |
duke@435 | 2809 | assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); |
duke@435 | 2810 | assert(opr2->is_fpu_register(), "both must be registers"); |
duke@435 | 2811 | __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2812 | |
duke@435 | 2813 | } else if (opr1->is_address() && opr2->is_constant()) { |
never@739 | 2814 | LIR_Const* c = opr2->as_constant_ptr(); |
never@739 | 2815 | #ifdef _LP64 |
never@739 | 2816 | if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2817 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); |
never@739 | 2818 | __ movoop(rscratch1, c->as_jobject()); |
never@739 | 2819 | } |
never@739 | 2820 | #endif // LP64 |
duke@435 | 2821 | if (op->info() != NULL) { |
duke@435 | 2822 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2823 | } |
duke@435 | 2824 | // special case: address - constant |
duke@435 | 2825 | LIR_Address* addr = opr1->as_address_ptr(); |
duke@435 | 2826 | if (c->type() == T_INT) { |
duke@435 | 2827 | __ cmpl(as_Address(addr), c->as_jint()); |
never@739 | 2828 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2829 | #ifdef _LP64 |
never@739 | 2830 | // %%% Make this explode if addr isn't reachable until we figure out a |
never@739 | 2831 | // better strategy by giving noreg as the temp for as_Address |
never@739 | 2832 | __ cmpptr(rscratch1, as_Address(addr, noreg)); |
never@739 | 2833 | #else |
duke@435 | 2834 | __ cmpoop(as_Address(addr), c->as_jobject()); |
never@739 | 2835 | #endif // _LP64 |
duke@435 | 2836 | } else { |
duke@435 | 2837 | ShouldNotReachHere(); |
duke@435 | 2838 | } |
duke@435 | 2839 | |
duke@435 | 2840 | } else { |
duke@435 | 2841 | ShouldNotReachHere(); |
duke@435 | 2842 | } |
duke@435 | 2843 | } |
duke@435 | 2844 | |
duke@435 | 2845 | void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { |
duke@435 | 2846 | if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
duke@435 | 2847 | if (left->is_single_xmm()) { |
duke@435 | 2848 | assert(right->is_single_xmm(), "must match"); |
duke@435 | 2849 | __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2850 | } else if (left->is_double_xmm()) { |
duke@435 | 2851 | assert(right->is_double_xmm(), "must match"); |
duke@435 | 2852 | __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2853 | |
duke@435 | 2854 | } else { |
duke@435 | 2855 | assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); |
duke@435 | 2856 | assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); |
duke@435 | 2857 | |
duke@435 | 2858 | assert(left->fpu() == 0, "left must be on TOS"); |
duke@435 | 2859 | __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), |
duke@435 | 2860 | op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2861 | } |
duke@435 | 2862 | } else { |
duke@435 | 2863 | assert(code == lir_cmp_l2i, "check"); |
never@739 | 2864 | #ifdef _LP64 |
iveresov@1804 | 2865 | Label done; |
iveresov@1804 | 2866 | Register dest = dst->as_register(); |
iveresov@1804 | 2867 | __ cmpptr(left->as_register_lo(), right->as_register_lo()); |
iveresov@1804 | 2868 | __ movl(dest, -1); |
iveresov@1804 | 2869 | __ jccb(Assembler::less, done); |
iveresov@1804 | 2870 | __ set_byte_if_not_zero(dest); |
iveresov@1804 | 2871 | __ movzbl(dest, dest); |
iveresov@1804 | 2872 | __ bind(done); |
never@739 | 2873 | #else |
duke@435 | 2874 | __ lcmp2int(left->as_register_hi(), |
duke@435 | 2875 | left->as_register_lo(), |
duke@435 | 2876 | right->as_register_hi(), |
duke@435 | 2877 | right->as_register_lo()); |
duke@435 | 2878 | move_regs(left->as_register_hi(), dst->as_register()); |
never@739 | 2879 | #endif // _LP64 |
duke@435 | 2880 | } |
duke@435 | 2881 | } |
duke@435 | 2882 | |
duke@435 | 2883 | |
duke@435 | 2884 | void LIR_Assembler::align_call(LIR_Code code) { |
duke@435 | 2885 | if (os::is_MP()) { |
duke@435 | 2886 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2887 | int offset = __ offset(); |
duke@435 | 2888 | switch (code) { |
duke@435 | 2889 | case lir_static_call: |
duke@435 | 2890 | case lir_optvirtual_call: |
twisti@1730 | 2891 | case lir_dynamic_call: |
duke@435 | 2892 | offset += NativeCall::displacement_offset; |
duke@435 | 2893 | break; |
duke@435 | 2894 | case lir_icvirtual_call: |
duke@435 | 2895 | offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; |
duke@435 | 2896 | break; |
duke@435 | 2897 | case lir_virtual_call: // currently, sparc-specific for niagara |
duke@435 | 2898 | default: ShouldNotReachHere(); |
duke@435 | 2899 | } |
duke@435 | 2900 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2901 | __ nop(); |
duke@435 | 2902 | } |
duke@435 | 2903 | } |
duke@435 | 2904 | } |
duke@435 | 2905 | |
duke@435 | 2906 | |
twisti@1730 | 2907 | void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
duke@435 | 2908 | assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2909 | "must be aligned"); |
twisti@1730 | 2910 | __ call(AddressLiteral(op->addr(), rtype)); |
twisti@1919 | 2911 | add_call_info(code_offset(), op->info()); |
duke@435 | 2912 | } |
duke@435 | 2913 | |
duke@435 | 2914 | |
twisti@1730 | 2915 | void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
duke@435 | 2916 | RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
duke@435 | 2917 | __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); |
duke@435 | 2918 | assert(!os::is_MP() || |
duke@435 | 2919 | (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2920 | "must be aligned"); |
twisti@1730 | 2921 | __ call(AddressLiteral(op->addr(), rh)); |
twisti@1919 | 2922 | add_call_info(code_offset(), op->info()); |
duke@435 | 2923 | } |
duke@435 | 2924 | |
duke@435 | 2925 | |
duke@435 | 2926 | /* Currently, vtable-dispatch is only enabled for sparc platforms */ |
twisti@1730 | 2927 | void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
duke@435 | 2928 | ShouldNotReachHere(); |
duke@435 | 2929 | } |
duke@435 | 2930 | |
twisti@1730 | 2931 | |
duke@435 | 2932 | void LIR_Assembler::emit_static_call_stub() { |
duke@435 | 2933 | address call_pc = __ pc(); |
duke@435 | 2934 | address stub = __ start_a_stub(call_stub_size); |
duke@435 | 2935 | if (stub == NULL) { |
duke@435 | 2936 | bailout("static call stub overflow"); |
duke@435 | 2937 | return; |
duke@435 | 2938 | } |
duke@435 | 2939 | |
duke@435 | 2940 | int start = __ offset(); |
duke@435 | 2941 | if (os::is_MP()) { |
duke@435 | 2942 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2943 | int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; |
duke@435 | 2944 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2945 | __ nop(); |
duke@435 | 2946 | } |
duke@435 | 2947 | } |
duke@435 | 2948 | __ relocate(static_stub_Relocation::spec(call_pc)); |
duke@435 | 2949 | __ movoop(rbx, (jobject)NULL); |
duke@435 | 2950 | // must be set to -1 at code generation time |
duke@435 | 2951 | assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); |
never@739 | 2952 | // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
never@739 | 2953 | __ jump(RuntimeAddress(__ pc())); |
duke@435 | 2954 | |
jcoomes@1844 | 2955 | assert(__ offset() - start <= call_stub_size, "stub too big"); |
duke@435 | 2956 | __ end_a_stub(); |
duke@435 | 2957 | } |
duke@435 | 2958 | |
duke@435 | 2959 | |
never@1813 | 2960 | void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
duke@435 | 2961 | assert(exceptionOop->as_register() == rax, "must match"); |
never@1813 | 2962 | assert(exceptionPC->as_register() == rdx, "must match"); |
duke@435 | 2963 | |
duke@435 | 2964 | // exception object is not added to oop map by LinearScan |
duke@435 | 2965 | // (LinearScan assumes that no oops are in fixed registers) |
duke@435 | 2966 | info->add_register_oop(exceptionOop); |
duke@435 | 2967 | Runtime1::StubID unwind_id; |
duke@435 | 2968 | |
never@1813 | 2969 | // get current pc information |
never@1813 | 2970 | // pc is only needed if the method has an exception handler, the unwind code does not need it. |
never@1813 | 2971 | int pc_for_athrow_offset = __ offset(); |
never@1813 | 2972 | InternalAddress pc_for_athrow(__ pc()); |
never@1813 | 2973 | __ lea(exceptionPC->as_register(), pc_for_athrow); |
never@1813 | 2974 | add_call_info(pc_for_athrow_offset, info); // for exception handler |
never@1813 | 2975 | |
never@1813 | 2976 | __ verify_not_null_oop(rax); |
never@1813 | 2977 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
never@1813 | 2978 | if (compilation()->has_fpu_code()) { |
never@1813 | 2979 | unwind_id = Runtime1::handle_exception_id; |
duke@435 | 2980 | } else { |
never@1813 | 2981 | unwind_id = Runtime1::handle_exception_nofpu_id; |
duke@435 | 2982 | } |
never@1813 | 2983 | __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
duke@435 | 2984 | |
duke@435 | 2985 | // enough room for two byte trap |
duke@435 | 2986 | __ nop(); |
duke@435 | 2987 | } |
duke@435 | 2988 | |
duke@435 | 2989 | |
never@1813 | 2990 | void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
never@1813 | 2991 | assert(exceptionOop->as_register() == rax, "must match"); |
never@1813 | 2992 | |
never@1813 | 2993 | __ jmp(_unwind_handler_entry); |
never@1813 | 2994 | } |
never@1813 | 2995 | |
never@1813 | 2996 | |
duke@435 | 2997 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
duke@435 | 2998 | |
duke@435 | 2999 | // optimized version for linear scan: |
duke@435 | 3000 | // * count must be already in ECX (guaranteed by LinearScan) |
duke@435 | 3001 | // * left and dest must be equal |
duke@435 | 3002 | // * tmp must be unused |
duke@435 | 3003 | assert(count->as_register() == SHIFT_count, "count must be in ECX"); |
duke@435 | 3004 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 3005 | assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); |
duke@435 | 3006 | |
duke@435 | 3007 | if (left->is_single_cpu()) { |
duke@435 | 3008 | Register value = left->as_register(); |
duke@435 | 3009 | assert(value != SHIFT_count, "left cannot be ECX"); |
duke@435 | 3010 | |
duke@435 | 3011 | switch (code) { |
duke@435 | 3012 | case lir_shl: __ shll(value); break; |
duke@435 | 3013 | case lir_shr: __ sarl(value); break; |
duke@435 | 3014 | case lir_ushr: __ shrl(value); break; |
duke@435 | 3015 | default: ShouldNotReachHere(); |
duke@435 | 3016 | } |
duke@435 | 3017 | } else if (left->is_double_cpu()) { |
duke@435 | 3018 | Register lo = left->as_register_lo(); |
duke@435 | 3019 | Register hi = left->as_register_hi(); |
duke@435 | 3020 | assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); |
never@739 | 3021 | #ifdef _LP64 |
never@739 | 3022 | switch (code) { |
never@739 | 3023 | case lir_shl: __ shlptr(lo); break; |
never@739 | 3024 | case lir_shr: __ sarptr(lo); break; |
never@739 | 3025 | case lir_ushr: __ shrptr(lo); break; |
never@739 | 3026 | default: ShouldNotReachHere(); |
never@739 | 3027 | } |
never@739 | 3028 | #else |
duke@435 | 3029 | |
duke@435 | 3030 | switch (code) { |
duke@435 | 3031 | case lir_shl: __ lshl(hi, lo); break; |
duke@435 | 3032 | case lir_shr: __ lshr(hi, lo, true); break; |
duke@435 | 3033 | case lir_ushr: __ lshr(hi, lo, false); break; |
duke@435 | 3034 | default: ShouldNotReachHere(); |
duke@435 | 3035 | } |
never@739 | 3036 | #endif // LP64 |
duke@435 | 3037 | } else { |
duke@435 | 3038 | ShouldNotReachHere(); |
duke@435 | 3039 | } |
duke@435 | 3040 | } |
duke@435 | 3041 | |
duke@435 | 3042 | |
duke@435 | 3043 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
duke@435 | 3044 | if (dest->is_single_cpu()) { |
duke@435 | 3045 | // first move left into dest so that left is not destroyed by the shift |
duke@435 | 3046 | Register value = dest->as_register(); |
duke@435 | 3047 | count = count & 0x1F; // Java spec |
duke@435 | 3048 | |
duke@435 | 3049 | move_regs(left->as_register(), value); |
duke@435 | 3050 | switch (code) { |
duke@435 | 3051 | case lir_shl: __ shll(value, count); break; |
duke@435 | 3052 | case lir_shr: __ sarl(value, count); break; |
duke@435 | 3053 | case lir_ushr: __ shrl(value, count); break; |
duke@435 | 3054 | default: ShouldNotReachHere(); |
duke@435 | 3055 | } |
duke@435 | 3056 | } else if (dest->is_double_cpu()) { |
never@739 | 3057 | #ifndef _LP64 |
duke@435 | 3058 | Unimplemented(); |
never@739 | 3059 | #else |
never@739 | 3060 | // first move left into dest so that left is not destroyed by the shift |
never@739 | 3061 | Register value = dest->as_register_lo(); |
never@739 | 3062 | count = count & 0x1F; // Java spec |
never@739 | 3063 | |
never@739 | 3064 | move_regs(left->as_register_lo(), value); |
never@739 | 3065 | switch (code) { |
never@739 | 3066 | case lir_shl: __ shlptr(value, count); break; |
never@739 | 3067 | case lir_shr: __ sarptr(value, count); break; |
never@739 | 3068 | case lir_ushr: __ shrptr(value, count); break; |
never@739 | 3069 | default: ShouldNotReachHere(); |
never@739 | 3070 | } |
never@739 | 3071 | #endif // _LP64 |
duke@435 | 3072 | } else { |
duke@435 | 3073 | ShouldNotReachHere(); |
duke@435 | 3074 | } |
duke@435 | 3075 | } |
duke@435 | 3076 | |
duke@435 | 3077 | |
duke@435 | 3078 | void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { |
duke@435 | 3079 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3080 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3081 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 3082 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
duke@435 | 3083 | } |
duke@435 | 3084 | |
duke@435 | 3085 | |
duke@435 | 3086 | void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { |
duke@435 | 3087 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3088 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3089 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 3090 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
duke@435 | 3091 | } |
duke@435 | 3092 | |
duke@435 | 3093 | |
duke@435 | 3094 | void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { |
duke@435 | 3095 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3096 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3097 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
duke@435 | 3098 | __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); |
duke@435 | 3099 | } |
duke@435 | 3100 | |
duke@435 | 3101 | |
duke@435 | 3102 | // This code replaces a call to arraycopy; no exception may |
duke@435 | 3103 | // be thrown in this code, they must be thrown in the System.arraycopy |
duke@435 | 3104 | // activation frame; we could save some checks if this would not be the case |
duke@435 | 3105 | void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
duke@435 | 3106 | ciArrayKlass* default_type = op->expected_type(); |
duke@435 | 3107 | Register src = op->src()->as_register(); |
duke@435 | 3108 | Register dst = op->dst()->as_register(); |
duke@435 | 3109 | Register src_pos = op->src_pos()->as_register(); |
duke@435 | 3110 | Register dst_pos = op->dst_pos()->as_register(); |
duke@435 | 3111 | Register length = op->length()->as_register(); |
duke@435 | 3112 | Register tmp = op->tmp()->as_register(); |
duke@435 | 3113 | |
duke@435 | 3114 | CodeStub* stub = op->stub(); |
duke@435 | 3115 | int flags = op->flags(); |
duke@435 | 3116 | BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
duke@435 | 3117 | if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
duke@435 | 3118 | |
duke@435 | 3119 | // if we don't know anything or it's an object array, just go through the generic arraycopy |
duke@435 | 3120 | if (default_type == NULL) { |
duke@435 | 3121 | Label done; |
duke@435 | 3122 | // save outgoing arguments on stack in case call to System.arraycopy is needed |
duke@435 | 3123 | // HACK ALERT. This code used to push the parameters in a hardwired fashion |
duke@435 | 3124 | // for interpreter calling conventions. Now we have to do it in new style conventions. |
duke@435 | 3125 | // For the moment until C1 gets the new register allocator I just force all the |
duke@435 | 3126 | // args to the right place (except the register args) and then on the back side |
duke@435 | 3127 | // reload the register args properly if we go slow path. Yuck |
duke@435 | 3128 | |
duke@435 | 3129 | // These are proper for the calling convention |
duke@435 | 3130 | |
duke@435 | 3131 | store_parameter(length, 2); |
duke@435 | 3132 | store_parameter(dst_pos, 1); |
duke@435 | 3133 | store_parameter(dst, 0); |
duke@435 | 3134 | |
duke@435 | 3135 | // these are just temporary placements until we need to reload |
duke@435 | 3136 | store_parameter(src_pos, 3); |
duke@435 | 3137 | store_parameter(src, 4); |
never@739 | 3138 | NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
never@739 | 3139 | |
never@739 | 3140 | address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
duke@435 | 3141 | |
duke@435 | 3142 | // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint |
never@739 | 3143 | #ifdef _LP64 |
never@739 | 3144 | // The arguments are in java calling convention so we can trivially shift them to C |
never@739 | 3145 | // convention |
never@739 | 3146 | assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3147 | __ mov(c_rarg0, j_rarg0); |
never@739 | 3148 | assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3149 | __ mov(c_rarg1, j_rarg1); |
never@739 | 3150 | assert_different_registers(c_rarg2, j_rarg3, j_rarg4); |
never@739 | 3151 | __ mov(c_rarg2, j_rarg2); |
never@739 | 3152 | assert_different_registers(c_rarg3, j_rarg4); |
never@739 | 3153 | __ mov(c_rarg3, j_rarg3); |
never@739 | 3154 | #ifdef _WIN64 |
never@739 | 3155 | // Allocate abi space for args but be sure to keep stack aligned |
never@739 | 3156 | __ subptr(rsp, 6*wordSize); |
never@739 | 3157 | store_parameter(j_rarg4, 4); |
never@739 | 3158 | __ call(RuntimeAddress(entry)); |
never@739 | 3159 | __ addptr(rsp, 6*wordSize); |
never@739 | 3160 | #else |
never@739 | 3161 | __ mov(c_rarg4, j_rarg4); |
never@739 | 3162 | __ call(RuntimeAddress(entry)); |
never@739 | 3163 | #endif // _WIN64 |
never@739 | 3164 | #else |
never@739 | 3165 | __ push(length); |
never@739 | 3166 | __ push(dst_pos); |
never@739 | 3167 | __ push(dst); |
never@739 | 3168 | __ push(src_pos); |
never@739 | 3169 | __ push(src); |
duke@435 | 3170 | __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
duke@435 | 3171 | |
never@739 | 3172 | #endif // _LP64 |
never@739 | 3173 | |
duke@435 | 3174 | __ cmpl(rax, 0); |
duke@435 | 3175 | __ jcc(Assembler::equal, *stub->continuation()); |
duke@435 | 3176 | |
duke@435 | 3177 | // Reload values from the stack so they are where the stub |
duke@435 | 3178 | // expects them. |
never@739 | 3179 | __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
never@739 | 3180 | __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
never@739 | 3181 | __ movptr (length, Address(rsp, 2*BytesPerWord)); |
never@739 | 3182 | __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
never@739 | 3183 | __ movptr (src, Address(rsp, 4*BytesPerWord)); |
duke@435 | 3184 | __ jmp(*stub->entry()); |
duke@435 | 3185 | |
duke@435 | 3186 | __ bind(*stub->continuation()); |
duke@435 | 3187 | return; |
duke@435 | 3188 | } |
duke@435 | 3189 | |
duke@435 | 3190 | assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); |
duke@435 | 3191 | |
kvn@464 | 3192 | int elem_size = type2aelembytes(basic_type); |
duke@435 | 3193 | int shift_amount; |
duke@435 | 3194 | Address::ScaleFactor scale; |
duke@435 | 3195 | |
duke@435 | 3196 | switch (elem_size) { |
duke@435 | 3197 | case 1 : |
duke@435 | 3198 | shift_amount = 0; |
duke@435 | 3199 | scale = Address::times_1; |
duke@435 | 3200 | break; |
duke@435 | 3201 | case 2 : |
duke@435 | 3202 | shift_amount = 1; |
duke@435 | 3203 | scale = Address::times_2; |
duke@435 | 3204 | break; |
duke@435 | 3205 | case 4 : |
duke@435 | 3206 | shift_amount = 2; |
duke@435 | 3207 | scale = Address::times_4; |
duke@435 | 3208 | break; |
duke@435 | 3209 | case 8 : |
duke@435 | 3210 | shift_amount = 3; |
duke@435 | 3211 | scale = Address::times_8; |
duke@435 | 3212 | break; |
duke@435 | 3213 | default: |
duke@435 | 3214 | ShouldNotReachHere(); |
duke@435 | 3215 | } |
duke@435 | 3216 | |
duke@435 | 3217 | Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3218 | Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3219 | Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3220 | Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3221 | |
never@739 | 3222 | // length and pos's are all sign extended at this point on 64bit |
never@739 | 3223 | |
duke@435 | 3224 | // test for NULL |
duke@435 | 3225 | if (flags & LIR_OpArrayCopy::src_null_check) { |
never@739 | 3226 | __ testptr(src, src); |
duke@435 | 3227 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3228 | } |
duke@435 | 3229 | if (flags & LIR_OpArrayCopy::dst_null_check) { |
never@739 | 3230 | __ testptr(dst, dst); |
duke@435 | 3231 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3232 | } |
duke@435 | 3233 | |
duke@435 | 3234 | // check if negative |
duke@435 | 3235 | if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
duke@435 | 3236 | __ testl(src_pos, src_pos); |
duke@435 | 3237 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3238 | } |
duke@435 | 3239 | if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
duke@435 | 3240 | __ testl(dst_pos, dst_pos); |
duke@435 | 3241 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3242 | } |
duke@435 | 3243 | if (flags & LIR_OpArrayCopy::length_positive_check) { |
duke@435 | 3244 | __ testl(length, length); |
duke@435 | 3245 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3246 | } |
duke@435 | 3247 | |
duke@435 | 3248 | if (flags & LIR_OpArrayCopy::src_range_check) { |
never@739 | 3249 | __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
duke@435 | 3250 | __ cmpl(tmp, src_length_addr); |
duke@435 | 3251 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3252 | } |
duke@435 | 3253 | if (flags & LIR_OpArrayCopy::dst_range_check) { |
never@739 | 3254 | __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
duke@435 | 3255 | __ cmpl(tmp, dst_length_addr); |
duke@435 | 3256 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3257 | } |
duke@435 | 3258 | |
duke@435 | 3259 | if (flags & LIR_OpArrayCopy::type_check) { |
iveresov@2344 | 3260 | if (UseCompressedOops) { |
iveresov@2344 | 3261 | __ movl(tmp, src_klass_addr); |
iveresov@2344 | 3262 | __ cmpl(tmp, dst_klass_addr); |
iveresov@2344 | 3263 | } else { |
iveresov@2344 | 3264 | __ movptr(tmp, src_klass_addr); |
iveresov@2344 | 3265 | __ cmpptr(tmp, dst_klass_addr); |
iveresov@2344 | 3266 | } |
duke@435 | 3267 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 3268 | } |
duke@435 | 3269 | |
duke@435 | 3270 | #ifdef ASSERT |
duke@435 | 3271 | if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
duke@435 | 3272 | // Sanity check the known type with the incoming class. For the |
duke@435 | 3273 | // primitive case the types must match exactly with src.klass and |
duke@435 | 3274 | // dst.klass each exactly matching the default type. For the |
duke@435 | 3275 | // object array case, if no type check is needed then either the |
duke@435 | 3276 | // dst type is exactly the expected type and the src type is a |
duke@435 | 3277 | // subtype which we can't check or src is the same array as dst |
duke@435 | 3278 | // but not necessarily exactly of type default_type. |
duke@435 | 3279 | Label known_ok, halt; |
jrose@1424 | 3280 | __ movoop(tmp, default_type->constant_encoding()); |
iveresov@2344 | 3281 | #ifdef _LP64 |
iveresov@2344 | 3282 | if (UseCompressedOops) { |
iveresov@2344 | 3283 | __ encode_heap_oop(tmp); |
iveresov@2344 | 3284 | } |
iveresov@2344 | 3285 | #endif |
iveresov@2344 | 3286 | |
duke@435 | 3287 | if (basic_type != T_OBJECT) { |
iveresov@2344 | 3288 | |
iveresov@2344 | 3289 | if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
iveresov@2344 | 3290 | else __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3291 | __ jcc(Assembler::notEqual, halt); |
iveresov@2344 | 3292 | if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); |
iveresov@2344 | 3293 | else __ cmpptr(tmp, src_klass_addr); |
duke@435 | 3294 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3295 | } else { |
iveresov@2344 | 3296 | if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
iveresov@2344 | 3297 | else __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3298 | __ jcc(Assembler::equal, known_ok); |
never@739 | 3299 | __ cmpptr(src, dst); |
duke@435 | 3300 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3301 | } |
duke@435 | 3302 | __ bind(halt); |
duke@435 | 3303 | __ stop("incorrect type information in arraycopy"); |
duke@435 | 3304 | __ bind(known_ok); |
duke@435 | 3305 | } |
duke@435 | 3306 | #endif |
duke@435 | 3307 | |
never@739 | 3308 | if (shift_amount > 0 && basic_type != T_OBJECT) { |
never@739 | 3309 | __ shlptr(length, shift_amount); |
never@739 | 3310 | } |
never@739 | 3311 | |
never@739 | 3312 | #ifdef _LP64 |
never@739 | 3313 | assert_different_registers(c_rarg0, dst, dst_pos, length); |
roland@1495 | 3314 | __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
never@739 | 3315 | __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3316 | assert_different_registers(c_rarg1, length); |
roland@1495 | 3317 | __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
never@739 | 3318 | __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3319 | __ mov(c_rarg2, length); |
never@739 | 3320 | |
never@739 | 3321 | #else |
never@739 | 3322 | __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3323 | store_parameter(tmp, 0); |
never@739 | 3324 | __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3325 | store_parameter(tmp, 1); |
duke@435 | 3326 | store_parameter(length, 2); |
never@739 | 3327 | #endif // _LP64 |
duke@435 | 3328 | if (basic_type == T_OBJECT) { |
duke@435 | 3329 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); |
duke@435 | 3330 | } else { |
duke@435 | 3331 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); |
duke@435 | 3332 | } |
duke@435 | 3333 | |
duke@435 | 3334 | __ bind(*stub->continuation()); |
duke@435 | 3335 | } |
duke@435 | 3336 | |
duke@435 | 3337 | |
duke@435 | 3338 | void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
duke@435 | 3339 | Register obj = op->obj_opr()->as_register(); // may not be an oop |
duke@435 | 3340 | Register hdr = op->hdr_opr()->as_register(); |
duke@435 | 3341 | Register lock = op->lock_opr()->as_register(); |
duke@435 | 3342 | if (!UseFastLocking) { |
duke@435 | 3343 | __ jmp(*op->stub()->entry()); |
duke@435 | 3344 | } else if (op->code() == lir_lock) { |
duke@435 | 3345 | Register scratch = noreg; |
duke@435 | 3346 | if (UseBiasedLocking) { |
duke@435 | 3347 | scratch = op->scratch_opr()->as_register(); |
duke@435 | 3348 | } |
duke@435 | 3349 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3350 | // add debug info for NullPointerException only if one is possible |
duke@435 | 3351 | int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); |
duke@435 | 3352 | if (op->info() != NULL) { |
duke@435 | 3353 | add_debug_info_for_null_check(null_check_offset, op->info()); |
duke@435 | 3354 | } |
duke@435 | 3355 | // done |
duke@435 | 3356 | } else if (op->code() == lir_unlock) { |
duke@435 | 3357 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3358 | __ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
duke@435 | 3359 | } else { |
duke@435 | 3360 | Unimplemented(); |
duke@435 | 3361 | } |
duke@435 | 3362 | __ bind(*op->stub()->continuation()); |
duke@435 | 3363 | } |
duke@435 | 3364 | |
duke@435 | 3365 | |
duke@435 | 3366 | void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
duke@435 | 3367 | ciMethod* method = op->profiled_method(); |
duke@435 | 3368 | int bci = op->profiled_bci(); |
duke@435 | 3369 | |
duke@435 | 3370 | // Update counter for all call types |
iveresov@2349 | 3371 | ciMethodData* md = method->method_data_or_null(); |
iveresov@2349 | 3372 | assert(md != NULL, "Sanity"); |
duke@435 | 3373 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 3374 | assert(data->is_CounterData(), "need CounterData for calls"); |
duke@435 | 3375 | assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
duke@435 | 3376 | Register mdo = op->mdo()->as_register(); |
jrose@1424 | 3377 | __ movoop(mdo, md->constant_encoding()); |
duke@435 | 3378 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
duke@435 | 3379 | Bytecodes::Code bc = method->java_code_at_bci(bci); |
duke@435 | 3380 | // Perform additional virtual call profiling for invokevirtual and |
duke@435 | 3381 | // invokeinterface bytecodes |
duke@435 | 3382 | if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
iveresov@2138 | 3383 | C1ProfileVirtualCalls) { |
duke@435 | 3384 | assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
duke@435 | 3385 | Register recv = op->recv()->as_register(); |
duke@435 | 3386 | assert_different_registers(mdo, recv); |
duke@435 | 3387 | assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
duke@435 | 3388 | ciKlass* known_klass = op->known_holder(); |
iveresov@2138 | 3389 | if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
duke@435 | 3390 | // We know the type that will be seen at this call site; we can |
duke@435 | 3391 | // statically update the methodDataOop rather than needing to do |
duke@435 | 3392 | // dynamic tests on the receiver type |
duke@435 | 3393 | |
duke@435 | 3394 | // NOTE: we should probably put a lock around this search to |
duke@435 | 3395 | // avoid collisions by concurrent compilations |
duke@435 | 3396 | ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
duke@435 | 3397 | uint i; |
duke@435 | 3398 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3399 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3400 | if (known_klass->equals(receiver)) { |
duke@435 | 3401 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
iveresov@2138 | 3402 | __ addptr(data_addr, DataLayout::counter_increment); |
duke@435 | 3403 | return; |
duke@435 | 3404 | } |
duke@435 | 3405 | } |
duke@435 | 3406 | |
duke@435 | 3407 | // Receiver type not found in profile data; select an empty slot |
duke@435 | 3408 | |
duke@435 | 3409 | // Note that this is less efficient than it should be because it |
duke@435 | 3410 | // always does a write to the receiver part of the |
duke@435 | 3411 | // VirtualCallData rather than just the first time |
duke@435 | 3412 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3413 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3414 | if (receiver == NULL) { |
duke@435 | 3415 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
jrose@1424 | 3416 | __ movoop(recv_addr, known_klass->constant_encoding()); |
duke@435 | 3417 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
iveresov@2138 | 3418 | __ addptr(data_addr, DataLayout::counter_increment); |
duke@435 | 3419 | return; |
duke@435 | 3420 | } |
duke@435 | 3421 | } |
duke@435 | 3422 | } else { |
iveresov@2344 | 3423 | __ load_klass(recv, recv); |
duke@435 | 3424 | Label update_done; |
iveresov@2138 | 3425 | type_profile_helper(mdo, md, data, recv, &update_done); |
kvn@1641 | 3426 | // Receiver did not match any saved receiver and there is no empty row for it. |
kvn@1686 | 3427 | // Increment total counter to indicate polymorphic case. |
iveresov@2138 | 3428 | __ addptr(counter_addr, DataLayout::counter_increment); |
duke@435 | 3429 | |
duke@435 | 3430 | __ bind(update_done); |
duke@435 | 3431 | } |
kvn@1641 | 3432 | } else { |
kvn@1641 | 3433 | // Static call |
iveresov@2138 | 3434 | __ addptr(counter_addr, DataLayout::counter_increment); |
duke@435 | 3435 | } |
duke@435 | 3436 | } |
duke@435 | 3437 | |
duke@435 | 3438 | void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
duke@435 | 3439 | Unimplemented(); |
duke@435 | 3440 | } |
duke@435 | 3441 | |
duke@435 | 3442 | |
duke@435 | 3443 | void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { |
never@739 | 3444 | __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
duke@435 | 3445 | } |
duke@435 | 3446 | |
duke@435 | 3447 | |
duke@435 | 3448 | void LIR_Assembler::align_backward_branch_target() { |
duke@435 | 3449 | __ align(BytesPerWord); |
duke@435 | 3450 | } |
duke@435 | 3451 | |
duke@435 | 3452 | |
duke@435 | 3453 | void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
duke@435 | 3454 | if (left->is_single_cpu()) { |
duke@435 | 3455 | __ negl(left->as_register()); |
duke@435 | 3456 | move_regs(left->as_register(), dest->as_register()); |
duke@435 | 3457 | |
duke@435 | 3458 | } else if (left->is_double_cpu()) { |
duke@435 | 3459 | Register lo = left->as_register_lo(); |
never@739 | 3460 | #ifdef _LP64 |
never@739 | 3461 | Register dst = dest->as_register_lo(); |
never@739 | 3462 | __ movptr(dst, lo); |
never@739 | 3463 | __ negptr(dst); |
never@739 | 3464 | #else |
duke@435 | 3465 | Register hi = left->as_register_hi(); |
duke@435 | 3466 | __ lneg(hi, lo); |
duke@435 | 3467 | if (dest->as_register_lo() == hi) { |
duke@435 | 3468 | assert(dest->as_register_hi() != lo, "destroying register"); |
duke@435 | 3469 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3470 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3471 | } else { |
duke@435 | 3472 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3473 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3474 | } |
never@739 | 3475 | #endif // _LP64 |
duke@435 | 3476 | |
duke@435 | 3477 | } else if (dest->is_single_xmm()) { |
duke@435 | 3478 | if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { |
duke@435 | 3479 | __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); |
duke@435 | 3480 | } |
duke@435 | 3481 | __ xorps(dest->as_xmm_float_reg(), |
duke@435 | 3482 | ExternalAddress((address)float_signflip_pool)); |
duke@435 | 3483 | |
duke@435 | 3484 | } else if (dest->is_double_xmm()) { |
duke@435 | 3485 | if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { |
duke@435 | 3486 | __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); |
duke@435 | 3487 | } |
duke@435 | 3488 | __ xorpd(dest->as_xmm_double_reg(), |
duke@435 | 3489 | ExternalAddress((address)double_signflip_pool)); |
duke@435 | 3490 | |
duke@435 | 3491 | } else if (left->is_single_fpu() || left->is_double_fpu()) { |
duke@435 | 3492 | assert(left->fpu() == 0, "arg must be on TOS"); |
duke@435 | 3493 | assert(dest->fpu() == 0, "dest must be TOS"); |
duke@435 | 3494 | __ fchs(); |
duke@435 | 3495 | |
duke@435 | 3496 | } else { |
duke@435 | 3497 | ShouldNotReachHere(); |
duke@435 | 3498 | } |
duke@435 | 3499 | } |
duke@435 | 3500 | |
duke@435 | 3501 | |
duke@435 | 3502 | void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { |
duke@435 | 3503 | assert(addr->is_address() && dest->is_register(), "check"); |
never@739 | 3504 | Register reg; |
never@739 | 3505 | reg = dest->as_pointer_register(); |
never@739 | 3506 | __ lea(reg, as_Address(addr->as_address_ptr())); |
duke@435 | 3507 | } |
duke@435 | 3508 | |
duke@435 | 3509 | |
duke@435 | 3510 | |
duke@435 | 3511 | void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 3512 | assert(!tmp->is_valid(), "don't need temporary"); |
duke@435 | 3513 | __ call(RuntimeAddress(dest)); |
duke@435 | 3514 | if (info != NULL) { |
duke@435 | 3515 | add_call_info_here(info); |
duke@435 | 3516 | } |
duke@435 | 3517 | } |
duke@435 | 3518 | |
duke@435 | 3519 | |
duke@435 | 3520 | void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
duke@435 | 3521 | assert(type == T_LONG, "only for volatile long fields"); |
duke@435 | 3522 | |
duke@435 | 3523 | if (info != NULL) { |
duke@435 | 3524 | add_debug_info_for_null_check_here(info); |
duke@435 | 3525 | } |
duke@435 | 3526 | |
duke@435 | 3527 | if (src->is_double_xmm()) { |
duke@435 | 3528 | if (dest->is_double_cpu()) { |
never@739 | 3529 | #ifdef _LP64 |
never@739 | 3530 | __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); |
never@739 | 3531 | #else |
never@739 | 3532 | __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); |
duke@435 | 3533 | __ psrlq(src->as_xmm_double_reg(), 32); |
never@739 | 3534 | __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
never@739 | 3535 | #endif // _LP64 |
duke@435 | 3536 | } else if (dest->is_double_stack()) { |
duke@435 | 3537 | __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); |
duke@435 | 3538 | } else if (dest->is_address()) { |
duke@435 | 3539 | __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); |
duke@435 | 3540 | } else { |
duke@435 | 3541 | ShouldNotReachHere(); |
duke@435 | 3542 | } |
duke@435 | 3543 | |
duke@435 | 3544 | } else if (dest->is_double_xmm()) { |
duke@435 | 3545 | if (src->is_double_stack()) { |
duke@435 | 3546 | __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3547 | } else if (src->is_address()) { |
duke@435 | 3548 | __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); |
duke@435 | 3549 | } else { |
duke@435 | 3550 | ShouldNotReachHere(); |
duke@435 | 3551 | } |
duke@435 | 3552 | |
duke@435 | 3553 | } else if (src->is_double_fpu()) { |
duke@435 | 3554 | assert(src->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3555 | if (dest->is_double_stack()) { |
duke@435 | 3556 | __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); |
duke@435 | 3557 | } else if (dest->is_address()) { |
duke@435 | 3558 | __ fistp_d(as_Address(dest->as_address_ptr())); |
duke@435 | 3559 | } else { |
duke@435 | 3560 | ShouldNotReachHere(); |
duke@435 | 3561 | } |
duke@435 | 3562 | |
duke@435 | 3563 | } else if (dest->is_double_fpu()) { |
duke@435 | 3564 | assert(dest->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3565 | if (src->is_double_stack()) { |
duke@435 | 3566 | __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3567 | } else if (src->is_address()) { |
duke@435 | 3568 | __ fild_d(as_Address(src->as_address_ptr())); |
duke@435 | 3569 | } else { |
duke@435 | 3570 | ShouldNotReachHere(); |
duke@435 | 3571 | } |
duke@435 | 3572 | } else { |
duke@435 | 3573 | ShouldNotReachHere(); |
duke@435 | 3574 | } |
duke@435 | 3575 | } |
duke@435 | 3576 | |
duke@435 | 3577 | |
duke@435 | 3578 | void LIR_Assembler::membar() { |
never@739 | 3579 | // QQQ sparc TSO uses this, |
never@739 | 3580 | __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
duke@435 | 3581 | } |
duke@435 | 3582 | |
duke@435 | 3583 | void LIR_Assembler::membar_acquire() { |
duke@435 | 3584 | // No x86 machines currently require load fences |
duke@435 | 3585 | // __ load_fence(); |
duke@435 | 3586 | } |
duke@435 | 3587 | |
duke@435 | 3588 | void LIR_Assembler::membar_release() { |
duke@435 | 3589 | // No x86 machines currently require store fences |
duke@435 | 3590 | // __ store_fence(); |
duke@435 | 3591 | } |
duke@435 | 3592 | |
duke@435 | 3593 | void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
duke@435 | 3594 | assert(result_reg->is_register(), "check"); |
never@739 | 3595 | #ifdef _LP64 |
never@739 | 3596 | // __ get_thread(result_reg->as_register_lo()); |
never@739 | 3597 | __ mov(result_reg->as_register(), r15_thread); |
never@739 | 3598 | #else |
duke@435 | 3599 | __ get_thread(result_reg->as_register()); |
never@739 | 3600 | #endif // _LP64 |
duke@435 | 3601 | } |
duke@435 | 3602 | |
duke@435 | 3603 | |
duke@435 | 3604 | void LIR_Assembler::peephole(LIR_List*) { |
duke@435 | 3605 | // do nothing for now |
duke@435 | 3606 | } |
duke@435 | 3607 | |
duke@435 | 3608 | |
duke@435 | 3609 | #undef __ |