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src/cpu/sparc/vm/assembler_sparc.hpp@03214612e77e (annotated)

src/cpu/sparc/vm/assembler_sparc.hpp

Wed, 30 Apr 2014 14:14:01 -0700

author

kvn

date

Wed, 30 Apr 2014 14:14:01 -0700

changeset 6653

03214612e77e

parent 6620

17b2fbdb6637

child 6876

710a3c8b516e

child 7027

b20a35eae442

permissions

-rw-r--r--

8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
Summary: Fix the arbitrary alignment issue in SPARC AES crypto stub routines.
Reviewed-by: kvn, iveresov
Contributed-by: shrinivas.joshi@oracle.com

duke@435	1	/*
kvn@6653	2	* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	26	#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	27
twisti@4323	28	#include "asm/register.hpp"
duke@435	29
duke@435	30	// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
duke@435	31	// level; i.e., what you write
duke@435	32	// is what you get. The Assembler is generating code into a CodeBuffer.
duke@435	33
duke@435	34	class Assembler : public AbstractAssembler {
duke@435	35	friend class AbstractAssembler;
twisti@1162	36	friend class AddressLiteral;
duke@435	37
duke@435	38	// code patchers need various routines like inv_wdisp()
duke@435	39	friend class NativeInstruction;
duke@435	40	friend class NativeGeneralJump;
duke@435	41	friend class Relocation;
duke@435	42	friend class Label;
duke@435	43
duke@435	44	public:
duke@435	45	// op carries format info; see page 62 & 267
duke@435	46
duke@435	47	enum ops {
duke@435	48	call_op = 1, // fmt 1
duke@435	49	branch_op = 0, // also sethi (fmt2)
duke@435	50	arith_op = 2, // fmt 3, arith & misc
duke@435	51	ldst_op = 3 // fmt 3, load/store
duke@435	52	};
duke@435	53
duke@435	54	enum op2s {
duke@435	55	bpr_op2 = 3,
duke@435	56	fb_op2 = 6,
duke@435	57	fbp_op2 = 5,
duke@435	58	br_op2 = 2,
duke@435	59	bp_op2 = 1,
duke@435	60	sethi_op2 = 4
duke@435	61	};
duke@435	62
duke@435	63	enum op3s {
duke@435	64	// selected op3s
duke@435	65	add_op3 = 0x00,
duke@435	66	and_op3 = 0x01,
duke@435	67	or_op3 = 0x02,
duke@435	68	xor_op3 = 0x03,
duke@435	69	sub_op3 = 0x04,
duke@435	70	andn_op3 = 0x05,
duke@435	71	orn_op3 = 0x06,
duke@435	72	xnor_op3 = 0x07,
duke@435	73	addc_op3 = 0x08,
duke@435	74	mulx_op3 = 0x09,
duke@435	75	umul_op3 = 0x0a,
duke@435	76	smul_op3 = 0x0b,
duke@435	77	subc_op3 = 0x0c,
duke@435	78	udivx_op3 = 0x0d,
duke@435	79	udiv_op3 = 0x0e,
duke@435	80	sdiv_op3 = 0x0f,
duke@435	81
duke@435	82	addcc_op3 = 0x10,
duke@435	83	andcc_op3 = 0x11,
duke@435	84	orcc_op3 = 0x12,
duke@435	85	xorcc_op3 = 0x13,
duke@435	86	subcc_op3 = 0x14,
duke@435	87	andncc_op3 = 0x15,
duke@435	88	orncc_op3 = 0x16,
duke@435	89	xnorcc_op3 = 0x17,
duke@435	90	addccc_op3 = 0x18,
kvn@6312	91	aes4_op3 = 0x19,
duke@435	92	umulcc_op3 = 0x1a,
duke@435	93	smulcc_op3 = 0x1b,
duke@435	94	subccc_op3 = 0x1c,
duke@435	95	udivcc_op3 = 0x1e,
duke@435	96	sdivcc_op3 = 0x1f,
duke@435	97
duke@435	98	taddcc_op3 = 0x20,
duke@435	99	tsubcc_op3 = 0x21,
duke@435	100	taddcctv_op3 = 0x22,
duke@435	101	tsubcctv_op3 = 0x23,
duke@435	102	mulscc_op3 = 0x24,
duke@435	103	sll_op3 = 0x25,
duke@435	104	sllx_op3 = 0x25,
duke@435	105	srl_op3 = 0x26,
duke@435	106	srlx_op3 = 0x26,
duke@435	107	sra_op3 = 0x27,
duke@435	108	srax_op3 = 0x27,
duke@435	109	rdreg_op3 = 0x28,
duke@435	110	membar_op3 = 0x28,
duke@435	111
duke@435	112	flushw_op3 = 0x2b,
duke@435	113	movcc_op3 = 0x2c,
duke@435	114	sdivx_op3 = 0x2d,
duke@435	115	popc_op3 = 0x2e,
duke@435	116	movr_op3 = 0x2f,
duke@435	117
duke@435	118	sir_op3 = 0x30,
duke@435	119	wrreg_op3 = 0x30,
duke@435	120	saved_op3 = 0x31,
duke@435	121
duke@435	122	fpop1_op3 = 0x34,
duke@435	123	fpop2_op3 = 0x35,
duke@435	124	impdep1_op3 = 0x36,
kvn@6312	125	aes3_op3 = 0x36,
kvn@6653	126	alignaddr_op3 = 0x36,
kvn@6653	127	faligndata_op3 = 0x36,
kvn@6312	128	flog3_op3 = 0x36,
kvn@6653	129	edge_op3 = 0x36,
kvn@6653	130	fsrc_op3 = 0x36,
duke@435	131	impdep2_op3 = 0x37,
kvn@6653	132	stpartialf_op3 = 0x37,
duke@435	133	jmpl_op3 = 0x38,
duke@435	134	rett_op3 = 0x39,
duke@435	135	trap_op3 = 0x3a,
duke@435	136	flush_op3 = 0x3b,
duke@435	137	save_op3 = 0x3c,
duke@435	138	restore_op3 = 0x3d,
duke@435	139	done_op3 = 0x3e,
duke@435	140	retry_op3 = 0x3e,
duke@435	141
duke@435	142	lduw_op3 = 0x00,
duke@435	143	ldub_op3 = 0x01,
duke@435	144	lduh_op3 = 0x02,
duke@435	145	ldd_op3 = 0x03,
duke@435	146	stw_op3 = 0x04,
duke@435	147	stb_op3 = 0x05,
duke@435	148	sth_op3 = 0x06,
duke@435	149	std_op3 = 0x07,
duke@435	150	ldsw_op3 = 0x08,
duke@435	151	ldsb_op3 = 0x09,
duke@435	152	ldsh_op3 = 0x0a,
duke@435	153	ldx_op3 = 0x0b,
duke@435	154
duke@435	155	stx_op3 = 0x0e,
duke@435	156	swap_op3 = 0x0f,
duke@435	157
duke@435	158	stwa_op3 = 0x14,
duke@435	159	stxa_op3 = 0x1e,
duke@435	160
duke@435	161	ldf_op3 = 0x20,
duke@435	162	ldfsr_op3 = 0x21,
duke@435	163	ldqf_op3 = 0x22,
duke@435	164	lddf_op3 = 0x23,
duke@435	165	stf_op3 = 0x24,
duke@435	166	stfsr_op3 = 0x25,
duke@435	167	stqf_op3 = 0x26,
duke@435	168	stdf_op3 = 0x27,
duke@435	169
duke@435	170	prefetch_op3 = 0x2d,
duke@435	171
duke@435	172	casa_op3 = 0x3c,
duke@435	173	casxa_op3 = 0x3e,
duke@435	174
kvn@3001	175	mftoi_op3 = 0x36,
kvn@3001	176
duke@435	177	alt_bit_op3 = 0x10,
duke@435	178	cc_bit_op3 = 0x10
duke@435	179	};
duke@435	180
duke@435	181	enum opfs {
duke@435	182	// selected opfs
kvn@6653	183	edge8n_opf = 0x01,
kvn@6653	184
kvn@6312	185	fmovs_opf = 0x01,
kvn@6312	186	fmovd_opf = 0x02,
duke@435	187
kvn@6312	188	fnegs_opf = 0x05,
kvn@6312	189	fnegd_opf = 0x06,
duke@435	190
kvn@6653	191	alignaddr_opf = 0x18,
kvn@6653	192
kvn@6312	193	fadds_opf = 0x41,
kvn@6312	194	faddd_opf = 0x42,
kvn@6312	195	fsubs_opf = 0x45,
kvn@6312	196	fsubd_opf = 0x46,
duke@435	197
kvn@6653	198	faligndata_opf = 0x48,
kvn@6653	199
kvn@6312	200	fmuls_opf = 0x49,
kvn@6312	201	fmuld_opf = 0x4a,
kvn@6312	202	fdivs_opf = 0x4d,
kvn@6312	203	fdivd_opf = 0x4e,
duke@435	204
kvn@6312	205	fcmps_opf = 0x51,
kvn@6312	206	fcmpd_opf = 0x52,
duke@435	207
kvn@6312	208	fstox_opf = 0x81,
kvn@6312	209	fdtox_opf = 0x82,
kvn@6312	210	fxtos_opf = 0x84,
kvn@6312	211	fxtod_opf = 0x88,
kvn@6312	212	fitos_opf = 0xc4,
kvn@6312	213	fdtos_opf = 0xc6,
kvn@6312	214	fitod_opf = 0xc8,
kvn@6312	215	fstod_opf = 0xc9,
kvn@6312	216	fstoi_opf = 0xd1,
kvn@6312	217	fdtoi_opf = 0xd2,
kvn@3001	218
kvn@6312	219	mdtox_opf = 0x110,
kvn@6312	220	mstouw_opf = 0x111,
kvn@6312	221	mstosw_opf = 0x113,
kvn@6312	222	mxtod_opf = 0x118,
kvn@6312	223	mwtos_opf = 0x119,
kvn@6312	224
kvn@6312	225	aes_kexpand0_opf = 0x130,
kvn@6312	226	aes_kexpand2_opf = 0x131
kvn@6312	227	};
kvn@6312	228
kvn@6312	229	enum op5s {
kvn@6312	230	aes_eround01_op5 = 0x00,
kvn@6312	231	aes_eround23_op5 = 0x01,
kvn@6312	232	aes_dround01_op5 = 0x02,
kvn@6312	233	aes_dround23_op5 = 0x03,
kvn@6312	234	aes_eround01_l_op5 = 0x04,
kvn@6312	235	aes_eround23_l_op5 = 0x05,
kvn@6312	236	aes_dround01_l_op5 = 0x06,
kvn@6312	237	aes_dround23_l_op5 = 0x07,
kvn@6312	238	aes_kexpand1_op5 = 0x08
duke@435	239	};
duke@435	240
kvn@3037	241	enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
duke@435	242
duke@435	243	enum Condition {
duke@435	244	// for FBfcc & FBPfcc instruction
duke@435	245	f_never = 0,
duke@435	246	f_notEqual = 1,
duke@435	247	f_notZero = 1,
duke@435	248	f_lessOrGreater = 2,
duke@435	249	f_unorderedOrLess = 3,
duke@435	250	f_less = 4,
duke@435	251	f_unorderedOrGreater = 5,
duke@435	252	f_greater = 6,
duke@435	253	f_unordered = 7,
duke@435	254	f_always = 8,
duke@435	255	f_equal = 9,
duke@435	256	f_zero = 9,
duke@435	257	f_unorderedOrEqual = 10,
duke@435	258	f_greaterOrEqual = 11,
duke@435	259	f_unorderedOrGreaterOrEqual = 12,
duke@435	260	f_lessOrEqual = 13,
duke@435	261	f_unorderedOrLessOrEqual = 14,
duke@435	262	f_ordered = 15,
duke@435	263
duke@435	264	// V8 coproc, pp 123 v8 manual
duke@435	265
duke@435	266	cp_always = 8,
duke@435	267	cp_never = 0,
duke@435	268	cp_3 = 7,
duke@435	269	cp_2 = 6,
duke@435	270	cp_2or3 = 5,
duke@435	271	cp_1 = 4,
duke@435	272	cp_1or3 = 3,
duke@435	273	cp_1or2 = 2,
duke@435	274	cp_1or2or3 = 1,
duke@435	275	cp_0 = 9,
duke@435	276	cp_0or3 = 10,
duke@435	277	cp_0or2 = 11,
duke@435	278	cp_0or2or3 = 12,
duke@435	279	cp_0or1 = 13,
duke@435	280	cp_0or1or3 = 14,
duke@435	281	cp_0or1or2 = 15,
duke@435	282
duke@435	283
duke@435	284	// for integers
duke@435	285
duke@435	286	never = 0,
duke@435	287	equal = 1,
duke@435	288	zero = 1,
duke@435	289	lessEqual = 2,
duke@435	290	less = 3,
duke@435	291	lessEqualUnsigned = 4,
duke@435	292	lessUnsigned = 5,
duke@435	293	carrySet = 5,
duke@435	294	negative = 6,
duke@435	295	overflowSet = 7,
duke@435	296	always = 8,
duke@435	297	notEqual = 9,
duke@435	298	notZero = 9,
duke@435	299	greater = 10,
duke@435	300	greaterEqual = 11,
duke@435	301	greaterUnsigned = 12,
duke@435	302	greaterEqualUnsigned = 13,
duke@435	303	carryClear = 13,
duke@435	304	positive = 14,
duke@435	305	overflowClear = 15
duke@435	306	};
duke@435	307
duke@435	308	enum CC {
duke@435	309	icc = 0, xcc = 2,
duke@435	310	// ptr_cc is the correct condition code for a pointer or intptr_t:
duke@435	311	ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
duke@435	312	fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
duke@435	313	};
duke@435	314
duke@435	315	enum PrefetchFcn {
duke@435	316	severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
duke@435	317	};
duke@435	318
duke@435	319	public:
duke@435	320	// Helper functions for groups of instructions
duke@435	321
duke@435	322	enum Predict { pt = 1, pn = 0 }; // pt = predict taken
duke@435	323
duke@435	324	enum Membar_mask_bits { // page 184, v9
duke@435	325	StoreStore = 1 << 3,
duke@435	326	LoadStore = 1 << 2,
duke@435	327	StoreLoad = 1 << 1,
duke@435	328	LoadLoad = 1 << 0,
duke@435	329
duke@435	330	Sync = 1 << 6,
duke@435	331	MemIssue = 1 << 5,
duke@435	332	Lookaside = 1 << 4
duke@435	333	};
duke@435	334
iveresov@2441	335	static bool is_in_wdisp_range(address a, address b, int nbits) {
iveresov@2441	336	intptr_t d = intptr_t(b) - intptr_t(a);
iveresov@2441	337	return is_simm(d, nbits + 2);
iveresov@2441	338	}
duke@435	339
kvn@3037	340	address target_distance(Label& L) {
kvn@3037	341	// Assembler::target(L) should be called only when
kvn@3037	342	// a branch instruction is emitted since non-bound
kvn@3037	343	// labels record current pc() as a branch address.
kvn@3037	344	if (L.is_bound()) return target(L);
kvn@3037	345	// Return current address for non-bound labels.
kvn@3037	346	return pc();
kvn@3037	347	}
kvn@3037	348
iveresov@2203	349	// test if label is in simm16 range in words (wdisp16).
iveresov@2203	350	bool is_in_wdisp16_range(Label& L) {
kvn@3037	351	return is_in_wdisp_range(target_distance(L), pc(), 16);
iveresov@2441	352	}
iveresov@2441	353	// test if the distance between two addresses fits in simm30 range in words
iveresov@2441	354	static bool is_in_wdisp30_range(address a, address b) {
iveresov@2441	355	return is_in_wdisp_range(a, b, 30);
iveresov@2203	356	}
iveresov@2203	357
duke@435	358	enum ASIs { // page 72, v9
kvn@3092	359	ASI_PRIMARY = 0x80,
kvn@3092	360	ASI_PRIMARY_NOFAULT = 0x82,
kvn@3092	361	ASI_PRIMARY_LITTLE = 0x88,
kvn@6653	362	// 8x8-bit partial store
kvn@6653	363	ASI_PST8_PRIMARY = 0xC0,
kvn@3052	364	// Block initializing store
kvn@3052	365	ASI_ST_BLKINIT_PRIMARY = 0xE2,
kvn@3052	366	// Most-Recently-Used (MRU) BIS variant
kvn@3052	367	ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
duke@435	368	// add more from book as needed
duke@435	369	};
duke@435	370
duke@435	371	protected:
duke@435	372	// helpers
duke@435	373
duke@435	374	// x is supposed to fit in a field "nbits" wide
duke@435	375	// and be sign-extended. Check the range.
duke@435	376
duke@435	377	static void assert_signed_range(intptr_t x, int nbits) {
never@2950	378	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
never@2950	379	err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
duke@435	380	}
duke@435	381
duke@435	382	static void assert_signed_word_disp_range(intptr_t x, int nbits) {
duke@435	383	assert( (x & 3) == 0, "not word aligned");
duke@435	384	assert_signed_range(x, nbits + 2);
duke@435	385	}
duke@435	386
duke@435	387	static void assert_unsigned_const(int x, int nbits) {
duke@435	388	assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
duke@435	389	}
duke@435	390
duke@435	391	// fields: note bits numbered from LSB = 0,
duke@435	392	// fields known by inclusive bit range
duke@435	393
duke@435	394	static int fmask(juint hi_bit, juint lo_bit) {
duke@435	395	assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
duke@435	396	return (1 << ( hi_bit-lo_bit + 1 )) - 1;
duke@435	397	}
duke@435	398
duke@435	399	// inverse of u_field
duke@435	400
duke@435	401	static int inv_u_field(int x, int hi_bit, int lo_bit) {
duke@435	402	juint r = juint(x) >> lo_bit;
duke@435	403	r &= fmask( hi_bit, lo_bit);
duke@435	404	return int(r);
duke@435	405	}
duke@435	406
duke@435	407
duke@435	408	// signed version: extract from field and sign-extend
duke@435	409
duke@435	410	static int inv_s_field(int x, int hi_bit, int lo_bit) {
duke@435	411	int sign_shift = 31 - hi_bit;
duke@435	412	return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
duke@435	413	}
duke@435	414
duke@435	415	// given a field that ranges from hi_bit to lo_bit (inclusive,
duke@435	416	// LSB = 0), and an unsigned value for the field,
duke@435	417	// shift it into the field
duke@435	418
duke@435	419	#ifdef ASSERT
duke@435	420	static int u_field(int x, int hi_bit, int lo_bit) {
duke@435	421	assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
duke@435	422	"value out of range");
duke@435	423	int r = x << lo_bit;
duke@435	424	assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
duke@435	425	return r;
duke@435	426	}
duke@435	427	#else
duke@435	428	// make sure this is inlined as it will reduce code size significantly
duke@435	429	#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
duke@435	430	#endif
duke@435	431
duke@435	432	static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
duke@435	433	static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
duke@435	434	static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
duke@435	435	static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
duke@435	436
duke@435	437	static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
duke@435	438
duke@435	439	static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
duke@435	440	static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
duke@435	441	static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
duke@435	442
duke@435	443	static int op( int x) { return u_field(x, 31, 30); }
duke@435	444	static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
duke@435	445	static int fcn( int x) { return u_field(x, 29, 25); }
duke@435	446	static int op3( int x) { return u_field(x, 24, 19); }
duke@435	447	static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
duke@435	448	static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
duke@435	449	static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
duke@435	450	static int cond( int x) { return u_field(x, 28, 25); }
duke@435	451	static int cond_mov( int x) { return u_field(x, 17, 14); }
duke@435	452	static int rcond( RCondition x) { return u_field(x, 12, 10); }
duke@435	453	static int op2( int x) { return u_field(x, 24, 22); }
duke@435	454	static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
duke@435	455	static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
duke@435	456	static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
duke@435	457	static int imm_asi( int x) { return u_field(x, 12, 5); }
duke@435	458	static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
duke@435	459	static int opf_low6( int w) { return u_field(w, 10, 5); }
duke@435	460	static int opf_low5( int w) { return u_field(w, 9, 5); }
kvn@6312	461	static int op5( int x) { return u_field(x, 8, 5); }
duke@435	462	static int trapcc( CC cc) { return u_field(cc, 12, 11); }
duke@435	463	static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
duke@435	464	static int opf( int x) { return u_field(x, 13, 5); }
duke@435	465
kvn@3037	466	static bool is_cbcond( int x ) {
kvn@3037	467	return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
kvn@3037	468	inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
kvn@3037	469	}
kvn@3037	470	static bool is_cxb( int x ) {
kvn@3037	471	assert(is_cbcond(x), "wrong instruction");
kvn@3037	472	return (x & (1<<21)) != 0;
kvn@3037	473	}
kvn@3037	474	static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
kvn@3037	475	static int inv_cond_cbcond(int x) {
kvn@3037	476	assert(is_cbcond(x), "wrong instruction");
kvn@3037	477	return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
kvn@3037	478	}
kvn@3037	479
duke@435	480	static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
duke@435	481	static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
duke@435	482
duke@435	483	static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
duke@435	484	static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
duke@435	485	static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
kvn@6312	486	static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
duke@435	487
duke@435	488	// some float instructions use this encoding on the op3 field
duke@435	489	static int alt_op3(int op, FloatRegisterImpl::Width w) {
duke@435	490	int r;
duke@435	491	switch(w) {
duke@435	492	case FloatRegisterImpl::S: r = op + 0; break;
duke@435	493	case FloatRegisterImpl::D: r = op + 3; break;
duke@435	494	case FloatRegisterImpl::Q: r = op + 2; break;
duke@435	495	default: ShouldNotReachHere(); break;
duke@435	496	}
duke@435	497	return op3(r);
duke@435	498	}
duke@435	499
duke@435	500
duke@435	501	// compute inverse of simm
duke@435	502	static int inv_simm(int x, int nbits) {
duke@435	503	return (int)(x << (32 - nbits)) >> (32 - nbits);
duke@435	504	}
duke@435	505
duke@435	506	static int inv_simm13( int x ) { return inv_simm(x, 13); }
duke@435	507
duke@435	508	// signed immediate, in low bits, nbits long
duke@435	509	static int simm(int x, int nbits) {
duke@435	510	assert_signed_range(x, nbits);
duke@435	511	return x & (( 1 << nbits ) - 1);
duke@435	512	}
duke@435	513
duke@435	514	// compute inverse of wdisp16
duke@435	515	static intptr_t inv_wdisp16(int x, intptr_t pos) {
duke@435	516	int lo = x & (( 1 << 14 ) - 1);
duke@435	517	int hi = (x >> 20) & 3;
duke@435	518	if (hi >= 2) hi |= ~1;
duke@435	519	return (((hi << 14) | lo) << 2) + pos;
duke@435	520	}
duke@435	521
duke@435	522	// word offset, 14 bits at LSend, 2 bits at B21, B20
duke@435	523	static int wdisp16(intptr_t x, intptr_t off) {
duke@435	524	intptr_t xx = x - off;
duke@435	525	assert_signed_word_disp_range(xx, 16);
duke@435	526	int r = (xx >> 2) & ((1 << 14) - 1)
duke@435	527	| ( ( (xx>>(2+14)) & 3 ) << 20 );
duke@435	528	assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
duke@435	529	return r;
duke@435	530	}
duke@435	531
kvn@3037	532	// compute inverse of wdisp10
kvn@3037	533	static intptr_t inv_wdisp10(int x, intptr_t pos) {
kvn@3037	534	assert(is_cbcond(x), "wrong instruction");
kvn@3037	535	int lo = inv_u_field(x, 12, 5);
kvn@3037	536	int hi = (x >> 19) & 3;
kvn@3037	537	if (hi >= 2) hi |= ~1;
kvn@3037	538	return (((hi << 8) | lo) << 2) + pos;
kvn@3037	539	}
kvn@3037	540
kvn@3037	541	// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
kvn@3037	542	static int wdisp10(intptr_t x, intptr_t off) {
kvn@3037	543	assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
kvn@3037	544	intptr_t xx = x - off;
kvn@3037	545	assert_signed_word_disp_range(xx, 10);
kvn@3037	546	int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
kvn@3037	547	| ( ( (xx >> (2+8)) & 3 ) << 19 );
kvn@3037	548	// Have to fake cbcond instruction to pass assert in inv_wdisp10()
kvn@3037	549	assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
kvn@3037	550	return r;
kvn@3037	551	}
duke@435	552
duke@435	553	// word displacement in low-order nbits bits
duke@435	554
duke@435	555	static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
duke@435	556	int pre_sign_extend = x & (( 1 << nbits ) - 1);
duke@435	557	int r = pre_sign_extend >= ( 1 << (nbits-1) )
duke@435	558	? pre_sign_extend | ~(( 1 << nbits ) - 1)
duke@435	559	: pre_sign_extend;
duke@435	560	return (r << 2) + pos;
duke@435	561	}
duke@435	562
duke@435	563	static int wdisp( intptr_t x, intptr_t off, int nbits ) {
duke@435	564	intptr_t xx = x - off;
duke@435	565	assert_signed_word_disp_range(xx, nbits);
duke@435	566	int r = (xx >> 2) & (( 1 << nbits ) - 1);
duke@435	567	assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
duke@435	568	return r;
duke@435	569	}
duke@435	570
duke@435	571
duke@435	572	// Extract the top 32 bits in a 64 bit word
duke@435	573	static int32_t hi32( int64_t x ) {
duke@435	574	int32_t r = int32_t( (uint64_t)x >> 32 );
duke@435	575	return r;
duke@435	576	}
duke@435	577
duke@435	578	// given a sethi instruction, extract the constant, left-justified
duke@435	579	static int inv_hi22( int x ) {
duke@435	580	return x << 10;
duke@435	581	}
duke@435	582
duke@435	583	// create an imm22 field, given a 32-bit left-justified constant
duke@435	584	static int hi22( int x ) {
duke@435	585	int r = int( juint(x) >> 10 );
duke@435	586	assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
duke@435	587	return r;
duke@435	588	}
duke@435	589
duke@435	590	// create a low10 __value__ (not a field) for a given a 32-bit constant
duke@435	591	static int low10( int x ) {
duke@435	592	return x & ((1 << 10) - 1);
duke@435	593	}
duke@435	594
kvn@6312	595	// AES crypto instructions supported only on certain processors
kvn@6312	596	static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
kvn@6312	597
kvn@6312	598	// instruction only in VIS1
kvn@6312	599	static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
kvn@6312	600
kvn@6653	601	// instruction only in VIS2
kvn@6653	602	static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
kvn@6653	603
kvn@3001	604	// instruction only in VIS3
kvn@3001	605	static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
kvn@3001	606
duke@435	607	// instruction only in v9
morris@5283	608	static void v9_only() { } // do nothing
duke@435	609
duke@435	610	// instruction deprecated in v9
duke@435	611	static void v9_dep() { } // do nothing for now
duke@435	612
duke@435	613	// v8 has no CC field
duke@435	614	static void v8_no_cc(CC cc) { if (cc) v9_only(); }
duke@435	615
duke@435	616	protected:
duke@435	617	// Simple delay-slot scheme:
duke@435	618	// In order to check the programmer, the assembler keeps track of deley slots.
duke@435	619	// It forbids CTIs in delay slots (conservative, but should be OK).
duke@435	620	// Also, when putting an instruction into a delay slot, you must say
duke@435	621	// asm->delayed()->add(...), in order to check that you don't omit
duke@435	622	// delay-slot instructions.
duke@435	623	// To implement this, we use a simple FSA
duke@435	624
duke@435	625	#ifdef ASSERT
duke@435	626	#define CHECK_DELAY
duke@435	627	#endif
duke@435	628	#ifdef CHECK_DELAY
duke@435	629	enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
duke@435	630	#endif
duke@435	631
duke@435	632	public:
duke@435	633	// Tells assembler next instruction must NOT be in delay slot.
duke@435	634	// Use at start of multinstruction macros.
duke@435	635	void assert_not_delayed() {
duke@435	636	// This is a separate overloading to avoid creation of string constants
duke@435	637	// in non-asserted code--with some compilers this pollutes the object code.
duke@435	638	#ifdef CHECK_DELAY
duke@435	639	assert_not_delayed("next instruction should not be a delay slot");
duke@435	640	#endif
duke@435	641	}
duke@435	642	void assert_not_delayed(const char* msg) {
duke@435	643	#ifdef CHECK_DELAY
jcoomes@1845	644	assert(delay_state == no_delay, msg);
duke@435	645	#endif
duke@435	646	}
duke@435	647
duke@435	648	protected:
iveresov@6620	649	// Insert a nop if the previous is cbcond
iveresov@6620	650	void insert_nop_after_cbcond() {
iveresov@6620	651	if (UseCBCond && cbcond_before()) {
iveresov@6620	652	nop();
iveresov@6620	653	}
iveresov@6620	654	}
duke@435	655	// Delay slot helpers
duke@435	656	// cti is called when emitting control-transfer instruction,
duke@435	657	// BEFORE doing the emitting.
duke@435	658	// Only effective when assertion-checking is enabled.
duke@435	659	void cti() {
iveresov@6620	660	// A cbcond instruction immediately followed by a CTI
iveresov@6620	661	// instruction introduces pipeline stalls, we need to avoid that.
iveresov@6620	662	no_cbcond_before();
duke@435	663	#ifdef CHECK_DELAY
duke@435	664	assert_not_delayed("cti should not be in delay slot");
duke@435	665	#endif
duke@435	666	}
duke@435	667
duke@435	668	// called when emitting cti with a delay slot, AFTER emitting
duke@435	669	void has_delay_slot() {
duke@435	670	#ifdef CHECK_DELAY
duke@435	671	assert_not_delayed("just checking");
duke@435	672	delay_state = at_delay_slot;
duke@435	673	#endif
duke@435	674	}
duke@435	675
kvn@3037	676	// cbcond instruction should not be generated one after an other
kvn@3037	677	bool cbcond_before() {
kvn@3037	678	if (offset() == 0) return false; // it is first instruction
kvn@3037	679	int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
kvn@3037	680	return is_cbcond(x);
kvn@3037	681	}
kvn@3037	682
kvn@3037	683	void no_cbcond_before() {
kvn@3037	684	assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
kvn@3037	685	}
kvn@3049	686	public:
kvn@3049	687
kvn@3037	688	bool use_cbcond(Label& L) {
kvn@3037	689	if (!UseCBCond || cbcond_before()) return false;
kvn@3037	690	intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
kvn@3037	691	assert( (x & 3) == 0, "not word aligned");
twisti@3310	692	return is_simm12(x);
kvn@3037	693	}
kvn@3037	694
duke@435	695	// Tells assembler you know that next instruction is delayed
duke@435	696	Assembler* delayed() {
duke@435	697	#ifdef CHECK_DELAY
duke@435	698	assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
duke@435	699	delay_state = filling_delay_slot;
duke@435	700	#endif
duke@435	701	return this;
duke@435	702	}
duke@435	703
duke@435	704	void flush() {
duke@435	705	#ifdef CHECK_DELAY
duke@435	706	assert ( delay_state == no_delay, "ending code with a delay slot");
duke@435	707	#endif
duke@435	708	AbstractAssembler::flush();
duke@435	709	}
duke@435	710
twisti@4412	711	inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
twisti@4412	712	inline void emit_data(int x) { emit_int32(x); }
duke@435	713	inline void emit_data(int, RelocationHolder const&);
duke@435	714	inline void emit_data(int, relocInfo::relocType rtype);
duke@435	715	// helper for above fcns
duke@435	716	inline void check_delay();
duke@435	717
duke@435	718
duke@435	719	public:
duke@435	720	// instructions, refer to page numbers in the SPARC Architecture Manual, V9
duke@435	721
duke@435	722	// pp 135 (addc was addx in v8)
duke@435	723
twisti@1162	724	inline void add(Register s1, Register s2, Register d );
twisti@4323	725	inline void add(Register s1, int simm13a, Register d );
duke@435	726
twisti@4412	727	void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	728	void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	729	void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	730	void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	731	void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	732	void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	733
kvn@3037	734
kvn@6312	735	// 4-operand AES instructions
kvn@6312	736
kvn@6312	737	void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	738	void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	739	void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	740	void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	741	void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	742	void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	743	void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	744	void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	745	void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	746
kvn@6312	747
kvn@6312	748	// 3-operand AES instructions
kvn@6312	749
kvn@6312	750	void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	751	void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
kvn@6312	752
duke@435	753	// pp 136
duke@435	754
kvn@3037	755	inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
kvn@3037	756	inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
duke@435	757
kvn@3037	758	// compare and branch
kvn@3037	759	inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
kvn@3037	760	inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
kvn@3037	761
kvn@3049	762	protected: // use MacroAssembler::br instead
kvn@3049	763
kvn@3049	764	// pp 138
kvn@3049	765
kvn@3049	766	inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	767	inline void fb( Condition c, bool a, Label& L );
kvn@3049	768
kvn@3049	769	// pp 141
kvn@3049	770
kvn@3049	771	inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	772	inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
kvn@3049	773
kvn@3049	774	// pp 144
kvn@3049	775
kvn@3049	776	inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	777	inline void br( Condition c, bool a, Label& L );
kvn@3049	778
kvn@3049	779	// pp 146
kvn@3049	780
kvn@3049	781	inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	782	inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
kvn@3049	783
duke@435	784	// pp 149
duke@435	785
duke@435	786	inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	787	inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	788
kvn@3037	789	public:
kvn@3037	790
duke@435	791	// pp 150
duke@435	792
duke@435	793	// These instructions compare the contents of s2 with the contents of
duke@435	794	// memory at address in s1. If the values are equal, the contents of memory
duke@435	795	// at address s1 is swapped with the data in d. If the values are not equal,
duke@435	796	// the the contents of memory at s1 is loaded into d, without the swap.
duke@435	797
twisti@4412	798	void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
twisti@4412	799	void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
duke@435	800
duke@435	801	// pp 152
duke@435	802
twisti@4412	803	void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
twisti@4412	804	void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	805	void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
twisti@4412	806	void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	807	void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
twisti@4412	808	void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	809	void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
twisti@4412	810	void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	811
duke@435	812	// pp 155
duke@435	813
twisti@4412	814	void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
twisti@4412	815	void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
duke@435	816
duke@435	817	// pp 156
duke@435	818
twisti@4412	819	void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
twisti@4412	820	void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
duke@435	821
duke@435	822	// pp 157
duke@435	823
morris@5283	824	void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
morris@5283	825	void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
duke@435	826
duke@435	827	// pp 159
duke@435	828
twisti@4412	829	void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
twisti@4412	830	void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
duke@435	831
duke@435	832	// pp 160
duke@435	833
twisti@4412	834	void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
duke@435	835
duke@435	836	// pp 161
duke@435	837
twisti@4412	838	void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
twisti@4412	839	void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
duke@435	840
duke@435	841	// pp 162
duke@435	842
morris@5283	843	void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
duke@435	844
morris@5283	845	void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
duke@435	846
morris@5283	847	void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
duke@435	848
duke@435	849	// pp 163
duke@435	850
twisti@4412	851	void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
twisti@4412	852	void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
twisti@4412	853	void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
duke@435	854
kvn@6312	855	// FXORs/FXORd instructions
kvn@6312	856
kvn@6312	857	void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
kvn@6312	858
duke@435	859	// pp 164
duke@435	860
twisti@4412	861	void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
duke@435	862
duke@435	863	// pp 165
duke@435	864
duke@435	865	inline void flush( Register s1, Register s2 );
duke@435	866	inline void flush( Register s1, int simm13a);
duke@435	867
duke@435	868	// pp 167
duke@435	869
twisti@4412	870	void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
duke@435	871
duke@435	872	// pp 168
duke@435	873
twisti@4412	874	void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
duke@435	875	// v8 unimp == illtrap(0)
duke@435	876
duke@435	877	// pp 169
duke@435	878
twisti@4412	879	void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
twisti@4412	880	void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
duke@435	881
duke@435	882	// pp 170
duke@435	883
duke@435	884	void jmpl( Register s1, Register s2, Register d );
duke@435	885	void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	886
duke@435	887	// 171
duke@435	888
twisti@1162	889	inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
twisti@1162	890	inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
twisti@1162	891
duke@435	892
duke@435	893	inline void ldfsr( Register s1, Register s2 );
duke@435	894	inline void ldfsr( Register s1, int simm13a);
duke@435	895	inline void ldxfsr( Register s1, Register s2 );
duke@435	896	inline void ldxfsr( Register s1, int simm13a);
duke@435	897
duke@435	898	// 173
duke@435	899
twisti@4412	900	void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	901	void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	902
duke@435	903	// pp 175, lduw is ld on v8
duke@435	904
duke@435	905	inline void ldsb( Register s1, Register s2, Register d );
duke@435	906	inline void ldsb( Register s1, int simm13a, Register d);
duke@435	907	inline void ldsh( Register s1, Register s2, Register d );
duke@435	908	inline void ldsh( Register s1, int simm13a, Register d);
duke@435	909	inline void ldsw( Register s1, Register s2, Register d );
duke@435	910	inline void ldsw( Register s1, int simm13a, Register d);
duke@435	911	inline void ldub( Register s1, Register s2, Register d );
duke@435	912	inline void ldub( Register s1, int simm13a, Register d);
duke@435	913	inline void lduh( Register s1, Register s2, Register d );
duke@435	914	inline void lduh( Register s1, int simm13a, Register d);
duke@435	915	inline void lduw( Register s1, Register s2, Register d );
duke@435	916	inline void lduw( Register s1, int simm13a, Register d);
duke@435	917	inline void ldx( Register s1, Register s2, Register d );
duke@435	918	inline void ldx( Register s1, int simm13a, Register d);
duke@435	919	inline void ldd( Register s1, Register s2, Register d );
duke@435	920	inline void ldd( Register s1, int simm13a, Register d);
duke@435	921
duke@435	922	// pp 177
duke@435	923
twisti@4412	924	void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	925	void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	926	void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	927	void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	928	void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	929	void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	930	void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	931	void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	932	void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	933	void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	934	void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	935	void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	936	void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	937	void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	938
duke@435	939	// pp 181
duke@435	940
twisti@4412	941	void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	942	void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	943	void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	944	void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	945	void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	946	void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	947	void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	948	void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	949	void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	950	void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	951	void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	952	void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	953	void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	954	void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	955	void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	956	void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	957	void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	958	void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	959	void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	960	void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	961	void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	962	void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	963	void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	964	void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	965
duke@435	966	// pp 183
duke@435	967
twisti@4412	968	void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
duke@435	969
duke@435	970	// pp 185
duke@435	971
twisti@4412	972	void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
duke@435	973
duke@435	974	// pp 189
duke@435	975
twisti@4412	976	void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
duke@435	977
duke@435	978	// pp 191
duke@435	979
twisti@4412	980	void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
twisti@4412	981	void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
duke@435	982
duke@435	983	// pp 195
duke@435	984
twisti@4412	985	void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
twisti@4412	986	void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
duke@435	987
duke@435	988	// pp 196
duke@435	989
twisti@4412	990	void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	991	void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	992	void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	993	void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	994	void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	995	void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	996
duke@435	997	// pp 197
duke@435	998
twisti@4412	999	void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1000	void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1001	void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1002	void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1003	void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1004	void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1005	void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1006	void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1007
duke@435	1008	// pp 201
duke@435	1009
twisti@4412	1010	void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
duke@435	1011
duke@435	1012
duke@435	1013	// pp 202
duke@435	1014
twisti@4412	1015	void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
twisti@4412	1016	void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1017
duke@435	1018	// pp 203
duke@435	1019
twisti@4412	1020	void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
twisti@4323	1021	void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
twisti@4323	1022
twisti@4412	1023	void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1024	void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1025
duke@435	1026	// pp 208
duke@435	1027
duke@435	1028	// not implementing read privileged register
duke@435	1029
twisti@4412	1030	inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
twisti@4412	1031	inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
twisti@4412	1032	inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
twisti@4412	1033	inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
twisti@4412	1034	inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
twisti@4412	1035	inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
duke@435	1036
duke@435	1037	// pp 213
duke@435	1038
duke@435	1039	inline void rett( Register s1, Register s2);
duke@435	1040	inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
duke@435	1041
duke@435	1042	// pp 214
duke@435	1043
twisti@4412	1044	void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
ysr@777	1045	void save( Register s1, int simm13a, Register d ) {
ysr@777	1046	// make sure frame is at least large enough for the register save area
ysr@777	1047	assert(-simm13a >= 16 * wordSize, "frame too small");
twisti@4412	1048	emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
ysr@777	1049	}
duke@435	1050
twisti@4412	1051	void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1052	void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1053
duke@435	1054	// pp 216
duke@435	1055
twisti@4412	1056	void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
twisti@4412	1057	void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
duke@435	1058
duke@435	1059	// pp 217
duke@435	1060
duke@435	1061	inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1062	// pp 218
duke@435	1063
twisti@4412	1064	void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1065	void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
twisti@4412	1066	void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1067	void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
twisti@4412	1068	void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1069	void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
duke@435	1070
twisti@4412	1071	void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1072	void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
twisti@4412	1073	void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1074	void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
twisti@4412	1075	void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1076	void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
duke@435	1077
duke@435	1078	// pp 220
duke@435	1079
twisti@4412	1080	void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1081
duke@435	1082	// pp 221
duke@435	1083
twisti@4412	1084	void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
duke@435	1085
duke@435	1086	// pp 222
duke@435	1087
twisti@1441	1088	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
duke@435	1089	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
duke@435	1090
duke@435	1091	inline void stfsr( Register s1, Register s2 );
duke@435	1092	inline void stfsr( Register s1, int simm13a);
duke@435	1093	inline void stxfsr( Register s1, Register s2 );
duke@435	1094	inline void stxfsr( Register s1, int simm13a);
duke@435	1095
duke@435	1096	// pp 224
duke@435	1097
twisti@4412	1098	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1099	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1100
duke@435	1101	// p 226
duke@435	1102
duke@435	1103	inline void stb( Register d, Register s1, Register s2 );
duke@435	1104	inline void stb( Register d, Register s1, int simm13a);
duke@435	1105	inline void sth( Register d, Register s1, Register s2 );
duke@435	1106	inline void sth( Register d, Register s1, int simm13a);
duke@435	1107	inline void stw( Register d, Register s1, Register s2 );
duke@435	1108	inline void stw( Register d, Register s1, int simm13a);
duke@435	1109	inline void stx( Register d, Register s1, Register s2 );
duke@435	1110	inline void stx( Register d, Register s1, int simm13a);
duke@435	1111	inline void std( Register d, Register s1, Register s2 );
duke@435	1112	inline void std( Register d, Register s1, int simm13a);
duke@435	1113
duke@435	1114	// pp 177
duke@435	1115
twisti@4412	1116	void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1117	void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1118	void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1119	void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1120	void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1121	void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1122	void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1123	void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1124	void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1125	void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1126
duke@435	1127	// pp 230
duke@435	1128
twisti@4412	1129	void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1130	void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@2350	1131
twisti@4412	1132	void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1133	void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1134	void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1135	void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1136	void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1137	void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1138
duke@435	1139	// pp 231
duke@435	1140
duke@435	1141	inline void swap( Register s1, Register s2, Register d );
duke@435	1142	inline void swap( Register s1, int simm13a, Register d);
duke@435	1143
duke@435	1144	// pp 232
duke@435	1145
twisti@4412	1146	void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1147	void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1148
duke@435	1149	// pp 234, note op in book is wrong, see pp 268
duke@435	1150
twisti@4412	1151	void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1152	void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1153
duke@435	1154	// pp 235
duke@435	1155
twisti@4412	1156	void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1157	void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1158
duke@435	1159	// pp 237
duke@435	1160
morris@5283	1161	void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
morris@5283	1162	void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
duke@435	1163	// simple uncond. trap
duke@435	1164	void trap( int trapa ) { trap( always, icc, G0, trapa ); }
duke@435	1165
duke@435	1166	// pp 239 omit write priv register for now
duke@435	1167
twisti@4412	1168	inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
twisti@4412	1169	inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
twisti@4412	1170	inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
duke@435	1171	rs1(s) |
duke@435	1172	op3(wrreg_op3) |
duke@435	1173	u_field(2, 29, 25) |
kvn@3092	1174	immed(true) |
duke@435	1175	simm(simm13a, 13)); }
twisti@4412	1176	inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
kvn@3092	1177	// wrasi(d, imm) stores (d xor imm) to asi
twisti@4412	1178	inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
kvn@3092	1179	u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
twisti@4412	1180	inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
duke@435	1181
kvn@3001	1182
kvn@6653	1183	// VIS1 instructions
kvn@6653	1184
kvn@6653	1185	void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
kvn@6653	1186
kvn@6653	1187	void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
kvn@6653	1188
kvn@6653	1189	void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
kvn@6653	1190
kvn@6653	1191	void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
kvn@6653	1192
kvn@6653	1193	// VIS2 instructions
kvn@6653	1194
kvn@6653	1195	void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
kvn@6653	1196
kvn@3001	1197	// VIS3 instructions
kvn@3001	1198
twisti@4412	1199	void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
twisti@4412	1200	void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
twisti@4412	1201	void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
kvn@3001	1202
twisti@4412	1203	void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
twisti@4412	1204	void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
kvn@3001	1205
duke@435	1206	// Creation
duke@435	1207	Assembler(CodeBuffer* code) : AbstractAssembler(code) {
duke@435	1208	#ifdef CHECK_DELAY
duke@435	1209	delay_state = no_delay;
duke@435	1210	#endif
duke@435	1211	}
duke@435	1212	};
duke@435	1213
stefank@2314	1214	#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP