1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Thu May 01 15:02:46 2014 -0700
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Wed Apr 30 14:14:01 2014 -0700
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 *
1.9 * This code is free software; you can redistribute it and/or modify it
1.10 @@ -123,8 +123,13 @@
1.11 fpop2_op3 = 0x35,
1.12 impdep1_op3 = 0x36,
1.13 aes3_op3 = 0x36,
1.14 + alignaddr_op3 = 0x36,
1.15 + faligndata_op3 = 0x36,
1.16 flog3_op3 = 0x36,
1.17 + edge_op3 = 0x36,
1.18 + fsrc_op3 = 0x36,
1.19 impdep2_op3 = 0x37,
1.20 + stpartialf_op3 = 0x37,
1.21 jmpl_op3 = 0x38,
1.22 rett_op3 = 0x39,
1.23 trap_op3 = 0x3a,
1.24 @@ -175,17 +180,23 @@
1.25
1.26 enum opfs {
1.27 // selected opfs
1.28 + edge8n_opf = 0x01,
1.29 +
1.30 fmovs_opf = 0x01,
1.31 fmovd_opf = 0x02,
1.32
1.33 fnegs_opf = 0x05,
1.34 fnegd_opf = 0x06,
1.35
1.36 + alignaddr_opf = 0x18,
1.37 +
1.38 fadds_opf = 0x41,
1.39 faddd_opf = 0x42,
1.40 fsubs_opf = 0x45,
1.41 fsubd_opf = 0x46,
1.42
1.43 + faligndata_opf = 0x48,
1.44 +
1.45 fmuls_opf = 0x49,
1.46 fmuld_opf = 0x4a,
1.47 fdivs_opf = 0x4d,
1.48 @@ -348,6 +359,8 @@
1.49 ASI_PRIMARY = 0x80,
1.50 ASI_PRIMARY_NOFAULT = 0x82,
1.51 ASI_PRIMARY_LITTLE = 0x88,
1.52 + // 8x8-bit partial store
1.53 + ASI_PST8_PRIMARY = 0xC0,
1.54 // Block initializing store
1.55 ASI_ST_BLKINIT_PRIMARY = 0xE2,
1.56 // Most-Recently-Used (MRU) BIS variant
1.57 @@ -585,6 +598,9 @@
1.58 // instruction only in VIS1
1.59 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
1.60
1.61 + // instruction only in VIS2
1.62 + static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
1.63 +
1.64 // instruction only in VIS3
1.65 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
1.66
1.67 @@ -1164,6 +1180,20 @@
1.68 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1.69
1.70
1.71 + // VIS1 instructions
1.72 +
1.73 + void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1.74 +
1.75 + void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1.76 +
1.77 + void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1.78 +
1.79 + void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1.80 +
1.81 + // VIS2 instructions
1.82 +
1.83 + void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1.84 +
1.85 // VIS3 instructions
1.86
1.87 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
