Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/x86/vm/x86.ad	Thu Feb 16 11:33:49 2012 -0800
     1.2 +++ b/src/cpu/x86/vm/x86.ad	Thu Feb 16 17:12:49 2012 -0800
     1.3 @@ -1,5 +1,5 @@
     1.4  //
     1.5 -// Copyright (c) 2011, Oracle and/or its affiliates. All rights reserved.
     1.6 +// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
     1.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.8  //
     1.9  // This code is free software; you can redistribute it and/or modify it
    1.10 @@ -37,10 +37,87 @@
    1.11    static address double_signmask() { return (address)double_signmask_pool; }
    1.12    static address double_signflip() { return (address)double_signflip_pool; }
    1.13  #endif
    1.14 +
    1.15 +#ifndef PRODUCT
    1.16 +  void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
    1.17 +    st->print("nop \t# %d bytes pad for loops and calls", _count);
    1.18 +  }
    1.19 +#endif
    1.20 +
    1.21 +  void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
    1.22 +    MacroAssembler _masm(&cbuf);
    1.23 +    __ nop(_count);
    1.24 +  }
    1.25 +
    1.26 +  uint MachNopNode::size(PhaseRegAlloc*) const {
    1.27 +    return _count;
    1.28 +  }
    1.29 +
    1.30 +#ifndef PRODUCT
    1.31 +  void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
    1.32 +    st->print("# breakpoint");
    1.33 +  }
    1.34 +#endif
    1.35 +
    1.36 +  void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
    1.37 +    MacroAssembler _masm(&cbuf);
    1.38 +    __ int3();
    1.39 +  }
    1.40 +
    1.41 +  uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
    1.42 +    return MachNode::size(ra_);
    1.43 +  }
    1.44 +
    1.45 +%}
    1.46 +
    1.47 +encode %{
    1.48 +
    1.49 +  enc_class preserve_SP %{
    1.50 +    debug_only(int off0 = cbuf.insts_size());
    1.51 +    MacroAssembler _masm(&cbuf);
    1.52 +    // RBP is preserved across all calls, even compiled calls.
    1.53 +    // Use it to preserve RSP in places where the callee might change the SP.
    1.54 +    __ movptr(rbp_mh_SP_save, rsp);
    1.55 +    debug_only(int off1 = cbuf.insts_size());
    1.56 +    assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
    1.57 +  %}
    1.58 +
    1.59 +  enc_class restore_SP %{
    1.60 +    MacroAssembler _masm(&cbuf);
    1.61 +    __ movptr(rsp, rbp_mh_SP_save);
    1.62 +  %}
    1.63 +
    1.64 +  enc_class call_epilog %{
    1.65 +    if (VerifyStackAtCalls) {
    1.66 +      // Check that stack depth is unchanged: find majik cookie on stack
    1.67 +      int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
    1.68 +      MacroAssembler _masm(&cbuf);
    1.69 +      Label L;
    1.70 +      __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
    1.71 +      __ jccb(Assembler::equal, L);
    1.72 +      // Die if stack mismatch
    1.73 +      __ int3();
    1.74 +      __ bind(L);
    1.75 +    }
    1.76 +  %}
    1.77 +
    1.78  %}
    1.79  
    1.80  // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
    1.81  
    1.82 +// ============================================================================
    1.83 +
    1.84 +instruct ShouldNotReachHere() %{
    1.85 +  match(Halt);
    1.86 +  format %{ "int3\t# ShouldNotReachHere" %}
    1.87 +  ins_encode %{
    1.88 +    __ int3();
    1.89 +  %}
    1.90 +  ins_pipe(pipe_slow);
    1.91 +%}
    1.92 +
    1.93 +// ============================================================================
    1.94 +
    1.95  instruct addF_reg(regF dst, regF src) %{
    1.96    predicate((UseSSE>=1) && (UseAVX == 0));
    1.97    match(Set dst (AddF dst src));

     2.1 --- a/src/cpu/x86/vm/x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
     2.2 +++ b/src/cpu/x86/vm/x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
     2.3 @@ -1,5 +1,5 @@
     2.4  //
     2.5 -// Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
     2.6 +// Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
     2.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     2.8  //
     2.9  // This code is free software; you can redistribute it and/or modify it
    2.10 @@ -341,12 +341,6 @@
    2.11    return round_to(current_offset, alignment_required()) - current_offset;
    2.12  }
    2.13  
    2.14 -#ifndef PRODUCT
    2.15 -void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
    2.16 -  st->print("INT3");
    2.17 -}
    2.18 -#endif
    2.19 -
    2.20  // EMIT_RM()
    2.21  void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
    2.22    unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
    2.23 @@ -1117,7 +1111,7 @@
    2.24  }
    2.25  
    2.26  #ifndef PRODUCT
    2.27 -void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
    2.28 +void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
    2.29    implementation( NULL, ra_, false, st );
    2.30  }
    2.31  #endif
    2.32 @@ -1130,22 +1124,6 @@
    2.33    return implementation( NULL, ra_, true, NULL );
    2.34  }
    2.35  
    2.36 -//=============================================================================
    2.37 -#ifndef PRODUCT
    2.38 -void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
    2.39 -  st->print("NOP \t# %d bytes pad for loops and calls", _count);
    2.40 -}
    2.41 -#endif
    2.42 -
    2.43 -void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
    2.44 -  MacroAssembler _masm(&cbuf);
    2.45 -  __ nop(_count);
    2.46 -}
    2.47 -
    2.48 -uint MachNopNode::size(PhaseRegAlloc *) const {
    2.49 -  return _count;
    2.50 -}
    2.51 -
    2.52  
    2.53  //=============================================================================
    2.54  #ifndef PRODUCT
    2.55 @@ -1831,21 +1809,6 @@
    2.56      }
    2.57    %}
    2.58  
    2.59 -  enc_class preserve_SP %{
    2.60 -    debug_only(int off0 = cbuf.insts_size());
    2.61 -    MacroAssembler _masm(&cbuf);
    2.62 -    // RBP is preserved across all calls, even compiled calls.
    2.63 -    // Use it to preserve RSP in places where the callee might change the SP.
    2.64 -    __ movptr(rbp_mh_SP_save, rsp);
    2.65 -    debug_only(int off1 = cbuf.insts_size());
    2.66 -    assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
    2.67 -  %}
    2.68 -
    2.69 -  enc_class restore_SP %{
    2.70 -    MacroAssembler _masm(&cbuf);
    2.71 -    __ movptr(rsp, rbp_mh_SP_save);
    2.72 -  %}
    2.73 -
    2.74    enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
    2.75      // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
    2.76      // who we intended to call.
    2.77 @@ -3794,9 +3757,9 @@
    2.78    // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
    2.79    // Otherwise, it is above the locks and verification slot and alignment word
    2.80    return_addr(STACK - 1 +
    2.81 -              round_to(1+VerifyStackAtCalls+
    2.82 -              Compile::current()->fixed_slots(),
    2.83 -              (StackAlignmentInBytes/wordSize)));
    2.84 +              round_to((Compile::current()->in_preserve_stack_slots() +
    2.85 +                        Compile::current()->fixed_slots()),
    2.86 +                       stack_alignment_in_slots()));
    2.87  
    2.88    // Body of function which returns an integer array locating
    2.89    // arguments either in registers or in stack slots.  Passed an array
    2.90 @@ -13424,6 +13387,25 @@
    2.91    ins_pipe( ialu_reg_mem );
    2.92  %}
    2.93  
    2.94 +
    2.95 +// ============================================================================
    2.96 +// This name is KNOWN by the ADLC and cannot be changed.
    2.97 +// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    2.98 +// for this guy.
    2.99 +instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
   2.100 +  match(Set dst (ThreadLocal));
   2.101 +  effect(DEF dst, KILL cr);
   2.102 +
   2.103 +  format %{ "MOV    $dst, Thread::current()" %}
   2.104 +  ins_encode %{
   2.105 +    Register dstReg = as_Register($dst$$reg);
   2.106 +    __ get_thread(dstReg);
   2.107 +  %}
   2.108 +  ins_pipe( ialu_reg_fat );
   2.109 +%}
   2.110 +
   2.111 +
   2.112 +
   2.113  //----------PEEPHOLE RULES-----------------------------------------------------
   2.114  // These must follow all instruction definitions as they use the names
   2.115  // defined in the instructions definitions.

     3.1 --- a/src/cpu/x86/vm/x86_64.ad	Thu Feb 16 11:33:49 2012 -0800
     3.2 +++ b/src/cpu/x86/vm/x86_64.ad	Thu Feb 16 17:12:49 2012 -0800
     3.3 @@ -1,5 +1,5 @@
     3.4  //
     3.5 -// Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
     3.6 +// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
     3.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     3.8  //
     3.9  // This code is free software; you can redistribute it and/or modify it
    3.10 @@ -610,13 +610,6 @@
    3.11    return round_to(current_offset, alignment_required()) - current_offset;
    3.12  }
    3.13  
    3.14 -#ifndef PRODUCT
    3.15 -void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
    3.16 -{
    3.17 -  st->print("INT3");
    3.18 -}
    3.19 -#endif
    3.20 -
    3.21  // EMIT_RM()
    3.22  void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
    3.23    unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
    3.24 @@ -1530,26 +1523,6 @@
    3.25  
    3.26  //=============================================================================
    3.27  #ifndef PRODUCT
    3.28 -void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
    3.29 -{
    3.30 -  st->print("nop \t# %d bytes pad for loops and calls", _count);
    3.31 -}
    3.32 -#endif
    3.33 -
    3.34 -void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
    3.35 -{
    3.36 -  MacroAssembler _masm(&cbuf);
    3.37 -  __ nop(_count);
    3.38 -}
    3.39 -
    3.40 -uint MachNopNode::size(PhaseRegAlloc*) const
    3.41 -{
    3.42 -  return _count;
    3.43 -}
    3.44 -
    3.45 -
    3.46 -//=============================================================================
    3.47 -#ifndef PRODUCT
    3.48  void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
    3.49  {
    3.50    int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
    3.51 @@ -2255,21 +2228,6 @@
    3.52                     RELOC_DISP32);
    3.53    %}
    3.54  
    3.55 -  enc_class preserve_SP %{
    3.56 -    debug_only(int off0 = cbuf.insts_size());
    3.57 -    MacroAssembler _masm(&cbuf);
    3.58 -    // RBP is preserved across all calls, even compiled calls.
    3.59 -    // Use it to preserve RSP in places where the callee might change the SP.
    3.60 -    __ movptr(rbp_mh_SP_save, rsp);
    3.61 -    debug_only(int off1 = cbuf.insts_size());
    3.62 -    assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
    3.63 -  %}
    3.64 -
    3.65 -  enc_class restore_SP %{
    3.66 -    MacroAssembler _masm(&cbuf);
    3.67 -    __ movptr(rsp, rbp_mh_SP_save);
    3.68 -  %}
    3.69 -
    3.70    enc_class Java_Static_Call(method meth)
    3.71    %{
    3.72      // JAVA STATIC CALL
    3.73 @@ -3208,9 +3166,9 @@
    3.74    // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
    3.75    // Otherwise, it is above the locks and verification slot and alignment word
    3.76    return_addr(STACK - 2 +
    3.77 -              round_to(2 + 2 * VerifyStackAtCalls +
    3.78 -                       Compile::current()->fixed_slots(),
    3.79 -                       WordsPerLong * 2));
    3.80 +              round_to((Compile::current()->in_preserve_stack_slots() +
    3.81 +                        Compile::current()->fixed_slots()),
    3.82 +                       stack_alignment_in_slots()));
    3.83  
    3.84    // Body of function which returns an integer array locating
    3.85    // arguments either in registers or in stack slots.  Passed an array
    3.86 @@ -11668,6 +11626,21 @@
    3.87  %}
    3.88  
    3.89  
    3.90 +// ============================================================================
    3.91 +// This name is KNOWN by the ADLC and cannot be changed.
    3.92 +// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    3.93 +// for this guy.
    3.94 +instruct tlsLoadP(r15_RegP dst) %{
    3.95 +  match(Set dst (ThreadLocal));
    3.96 +  effect(DEF dst);
    3.97 +
    3.98 +  size(0);
    3.99 +  format %{ "# TLS is in R15" %}
   3.100 +  ins_encode( /*empty encoding*/ );
   3.101 +  ins_pipe(ialu_reg_reg);
   3.102 +%}
   3.103 +
   3.104 +
   3.105  //----------PEEPHOLE RULES-----------------------------------------------------
   3.106  // These must follow all instruction definitions as they use the names
   3.107  // defined in the instructions definitions.

     4.1 --- a/src/os_cpu/bsd_x86/vm/bsd_x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
     4.2 +++ b/src/os_cpu/bsd_x86/vm/bsd_x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
     4.3 @@ -1,5 +1,5 @@
     4.4  //
     4.5 -// Copyright (c) 1999, 2008, Oracle and/or its affiliates. All rights reserved.
     4.6 +// Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved.
     4.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4.8  //
     4.9  // This code is free software; you can redistribute it and/or modify it
    4.10 @@ -24,137 +24,3 @@
    4.11  
    4.12  // X86 Bsd Architecture Description File
    4.13  
    4.14 -//----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
    4.15 -// This block specifies the encoding classes used by the compiler to output
    4.16 -// byte streams.  Encoding classes generate functions which are called by
    4.17 -// Machine Instruction Nodes in order to generate the bit encoding of the
    4.18 -// instruction.  Operands specify their base encoding interface with the
    4.19 -// interface keyword.  There are currently supported four interfaces,
    4.20 -// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
    4.21 -// operand to generate a function which returns its register number when
    4.22 -// queried.   CONST_INTER causes an operand to generate a function which
    4.23 -// returns the value of the constant when queried.  MEMORY_INTER causes an
    4.24 -// operand to generate four functions which return the Base Register, the
    4.25 -// Index Register, the Scale Value, and the Offset Value of the operand when
    4.26 -// queried.  COND_INTER causes an operand to generate six functions which
    4.27 -// return the encoding code (ie - encoding bits for the instruction)
    4.28 -// associated with each basic boolean condition for a conditional instruction.
    4.29 -// Instructions specify two basic values for encoding.  They use the
    4.30 -// ins_encode keyword to specify their encoding class (which must be one of
    4.31 -// the class names specified in the encoding block), and they use the
    4.32 -// opcode keyword to specify, in order, their primary, secondary, and
    4.33 -// tertiary opcode.  Only the opcode sections which a particular instruction
    4.34 -// needs for encoding need to be specified.
    4.35 -encode %{
    4.36 -  // Build emit functions for each basic byte or larger field in the intel
    4.37 -  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
    4.38 -  // code in the enc_class source block.  Emit functions will live in the
    4.39 -  // main source block for now.  In future, we can generalize this by
    4.40 -  // adding a syntax that specifies the sizes of fields in an order,
    4.41 -  // so that the adlc can build the emit functions automagically
    4.42 -
    4.43 -  enc_class bsd_tlsencode (eRegP dst) %{
    4.44 -    Register dstReg = as_Register($dst$$reg);
    4.45 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    4.46 -      masm->get_thread(dstReg);
    4.47 -  %}
    4.48 -
    4.49 -  enc_class bsd_breakpoint  %{
    4.50 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    4.51 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    4.52 -  %}
    4.53 -
    4.54 -  enc_class call_epilog %{
    4.55 -    if( VerifyStackAtCalls ) {
    4.56 -      // Check that stack depth is unchanged: find majik cookie on stack
    4.57 -      int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
    4.58 -      if(framesize >= 128) {
    4.59 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    4.60 -        emit_d8(cbuf,0xBC);
    4.61 -        emit_d8(cbuf,0x24);
    4.62 -        emit_d32(cbuf,framesize); // Find majik cookie from ESP
    4.63 -        emit_d32(cbuf, 0xbadb100d);
    4.64 -      }
    4.65 -      else {
    4.66 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    4.67 -        emit_d8(cbuf,0x7C);
    4.68 -        emit_d8(cbuf,0x24);
    4.69 -        emit_d8(cbuf,framesize); // Find majik cookie from ESP
    4.70 -        emit_d32(cbuf, 0xbadb100d);
    4.71 -      }
    4.72 -      // jmp EQ around INT3
    4.73 -      // QQQ TODO
    4.74 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
    4.75 -      emit_opcode(cbuf,0x74);
    4.76 -      emit_d8(cbuf, jump_around);
    4.77 -      // QQQ temporary
    4.78 -      emit_break(cbuf);
    4.79 -      // Die if stack mismatch
    4.80 -      // emit_opcode(cbuf,0xCC);
    4.81 -    }
    4.82 -  %}
    4.83 -
    4.84 -%}
    4.85 -
    4.86 -// INSTRUCTIONS -- Platform dependent
    4.87 -
    4.88 -//----------OS and Locking Instructions----------------------------------------
    4.89 -
    4.90 -// This name is KNOWN by the ADLC and cannot be changed.
    4.91 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    4.92 -// for this guy.
    4.93 -instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
    4.94 -  match(Set dst (ThreadLocal));
    4.95 -  effect(DEF dst, KILL cr);
    4.96 -
    4.97 -  format %{ "MOV    $dst, Thread::current()" %}
    4.98 -  ins_encode( bsd_tlsencode(dst) );
    4.99 -  ins_pipe( ialu_reg_fat );
   4.100 -%}
   4.101 -
   4.102 -instruct TLS(eRegP dst) %{
   4.103 -  match(Set dst (ThreadLocal));
   4.104 -
   4.105 -  expand %{
   4.106 -    tlsLoadP(dst);
   4.107 -  %}
   4.108 -%}
   4.109 -
   4.110 -// Die now
   4.111 -instruct ShouldNotReachHere( )
   4.112 -%{
   4.113 -  match(Halt);
   4.114 -
   4.115 -  // Use the following format syntax
   4.116 -  format %{ "INT3   ; ShouldNotReachHere" %}
   4.117 -  // QQQ TODO for now call breakpoint
   4.118 -  // opcode(0xCC);
   4.119 -  // ins_encode(Opc);
   4.120 -  ins_encode(bsd_breakpoint);
   4.121 -  ins_pipe( pipe_slow );
   4.122 -%}
   4.123 -
   4.124 -
   4.125 -
   4.126 -// Platform dependent source
   4.127 -
   4.128 -source %{
   4.129 -
   4.130 -// emit an interrupt that is caught by the debugger
   4.131 -void emit_break(CodeBuffer &cbuf) {
   4.132 -
   4.133 -  // Debugger doesn't really catch this but best we can do so far QQQ
   4.134 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   4.135 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   4.136 -}
   4.137 -
   4.138 -void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
   4.139 -  emit_break(cbuf);
   4.140 -}
   4.141 -
   4.142 -
   4.143 -uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
   4.144 -  return 5;
   4.145 -}
   4.146 -
   4.147 -%}

     5.1 --- a/src/os_cpu/bsd_x86/vm/bsd_x86_64.ad	Thu Feb 16 11:33:49 2012 -0800
     5.2 +++ b/src/os_cpu/bsd_x86/vm/bsd_x86_64.ad	Thu Feb 16 17:12:49 2012 -0800
     5.3 @@ -1,5 +1,5 @@
     5.4  //
     5.5 -// Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved.
     5.6 +// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
     5.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5.8  //
     5.9  // This code is free software; you can redistribute it and/or modify it
    5.10 @@ -55,8 +55,7 @@
    5.11    // adding a syntax that specifies the sizes of fields in an order,
    5.12    // so that the adlc can build the emit functions automagically
    5.13  
    5.14 -  enc_class Java_To_Runtime(method meth)
    5.15 -  %{
    5.16 +  enc_class Java_To_Runtime(method meth) %{
    5.17      // No relocation needed
    5.18  
    5.19      // movq r10, <meth>
    5.20 @@ -70,104 +69,15 @@
    5.21      emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
    5.22    %}
    5.23  
    5.24 -  enc_class bsd_breakpoint
    5.25 -  %{
    5.26 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    5.27 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    5.28 -  %}
    5.29 -
    5.30 -  enc_class call_epilog
    5.31 -  %{
    5.32 -    if (VerifyStackAtCalls) {
    5.33 -      // Check that stack depth is unchanged: find majik cookie on stack
    5.34 -      int framesize =
    5.35 -        ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
    5.36 -      if (framesize) {
    5.37 -        if (framesize < 0x80) {
    5.38 -          emit_opcode(cbuf, Assembler::REX_W);
    5.39 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    5.40 -          emit_d8(cbuf, 0x7C);
    5.41 -          emit_d8(cbuf, 0x24);
    5.42 -          emit_d8(cbuf, framesize); // Find majik cookie from ESP
    5.43 -          emit_d32(cbuf, 0xbadb100d);
    5.44 -        } else {
    5.45 -          emit_opcode(cbuf, Assembler::REX_W);
    5.46 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    5.47 -          emit_d8(cbuf, 0xBC);
    5.48 -          emit_d8(cbuf, 0x24);
    5.49 -          emit_d32(cbuf, framesize); // Find majik cookie from ESP
    5.50 -          emit_d32(cbuf, 0xbadb100d);
    5.51 -        }
    5.52 -      }
    5.53 -      // jmp EQ around INT3
    5.54 -      // QQQ TODO
    5.55 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
    5.56 -      emit_opcode(cbuf, 0x74);
    5.57 -      emit_d8(cbuf, jump_around);
    5.58 -      // QQQ temporary
    5.59 -      emit_break(cbuf);
    5.60 -      // Die if stack mismatch
    5.61 -      // emit_opcode(cbuf,0xCC);
    5.62 -    }
    5.63 -  %}
    5.64 -
    5.65 -%}
    5.66 -
    5.67 -// INSTRUCTIONS -- Platform dependent
    5.68 -
    5.69 -//----------OS and Locking Instructions----------------------------------------
    5.70 -
    5.71 -// This name is KNOWN by the ADLC and cannot be changed.
    5.72 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    5.73 -// for this guy.
    5.74 -instruct tlsLoadP(r15_RegP dst)
    5.75 -%{
    5.76 -  match(Set dst (ThreadLocal));
    5.77 -  effect(DEF dst);
    5.78 -
    5.79 -  size(0);
    5.80 -  format %{ "# TLS is in R15" %}
    5.81 -  ins_encode( /*empty encoding*/ );
    5.82 -  ins_pipe(ialu_reg_reg);
    5.83 -%}
    5.84 -
    5.85 -// Die now
    5.86 -instruct ShouldNotReachHere()
    5.87 -%{
    5.88 -  match(Halt);
    5.89 -
    5.90 -  // Use the following format syntax
    5.91 -  format %{ "int3\t# ShouldNotReachHere" %}
    5.92 -  // QQQ TODO for now call breakpoint
    5.93 -  // opcode(0xCC);
    5.94 -  // ins_encode(Opc);
    5.95 -  ins_encode(bsd_breakpoint);
    5.96 -  ins_pipe(pipe_slow);
    5.97  %}
    5.98  
    5.99  
   5.100  // Platform dependent source
   5.101  
   5.102 -source
   5.103 -%{
   5.104 +source %{
   5.105  
   5.106  int MachCallRuntimeNode::ret_addr_offset() {
   5.107    return 13; // movq r10,#addr; callq (r10)
   5.108  }
   5.109  
   5.110 -// emit an interrupt that is caught by the debugger
   5.111 -void emit_break(CodeBuffer& cbuf) {
   5.112 -  // Debugger doesn't really catch this but best we can do so far QQQ
   5.113 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   5.114 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   5.115 -}
   5.116 -
   5.117 -void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
   5.118 -  emit_break(cbuf);
   5.119 -}
   5.120 -
   5.121 -uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
   5.122 -  return 5;
   5.123 -}
   5.124 -
   5.125  %}

     6.1 --- a/src/os_cpu/linux_x86/vm/linux_x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
     6.2 +++ b/src/os_cpu/linux_x86/vm/linux_x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
     6.3 @@ -1,5 +1,5 @@
     6.4  //
     6.5 -// Copyright (c) 1999, 2008, Oracle and/or its affiliates. All rights reserved.
     6.6 +// Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved.
     6.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     6.8  //
     6.9  // This code is free software; you can redistribute it and/or modify it
    6.10 @@ -24,137 +24,3 @@
    6.11  
    6.12  // X86 Linux Architecture Description File
    6.13  
    6.14 -//----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
    6.15 -// This block specifies the encoding classes used by the compiler to output
    6.16 -// byte streams.  Encoding classes generate functions which are called by
    6.17 -// Machine Instruction Nodes in order to generate the bit encoding of the
    6.18 -// instruction.  Operands specify their base encoding interface with the
    6.19 -// interface keyword.  There are currently supported four interfaces,
    6.20 -// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
    6.21 -// operand to generate a function which returns its register number when
    6.22 -// queried.   CONST_INTER causes an operand to generate a function which
    6.23 -// returns the value of the constant when queried.  MEMORY_INTER causes an
    6.24 -// operand to generate four functions which return the Base Register, the
    6.25 -// Index Register, the Scale Value, and the Offset Value of the operand when
    6.26 -// queried.  COND_INTER causes an operand to generate six functions which
    6.27 -// return the encoding code (ie - encoding bits for the instruction)
    6.28 -// associated with each basic boolean condition for a conditional instruction.
    6.29 -// Instructions specify two basic values for encoding.  They use the
    6.30 -// ins_encode keyword to specify their encoding class (which must be one of
    6.31 -// the class names specified in the encoding block), and they use the
    6.32 -// opcode keyword to specify, in order, their primary, secondary, and
    6.33 -// tertiary opcode.  Only the opcode sections which a particular instruction
    6.34 -// needs for encoding need to be specified.
    6.35 -encode %{
    6.36 -  // Build emit functions for each basic byte or larger field in the intel
    6.37 -  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
    6.38 -  // code in the enc_class source block.  Emit functions will live in the
    6.39 -  // main source block for now.  In future, we can generalize this by
    6.40 -  // adding a syntax that specifies the sizes of fields in an order,
    6.41 -  // so that the adlc can build the emit functions automagically
    6.42 -
    6.43 -  enc_class linux_tlsencode (eRegP dst) %{
    6.44 -    Register dstReg = as_Register($dst$$reg);
    6.45 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    6.46 -      masm->get_thread(dstReg);
    6.47 -  %}
    6.48 -
    6.49 -  enc_class linux_breakpoint  %{
    6.50 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    6.51 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    6.52 -  %}
    6.53 -
    6.54 -  enc_class call_epilog %{
    6.55 -    if( VerifyStackAtCalls ) {
    6.56 -      // Check that stack depth is unchanged: find majik cookie on stack
    6.57 -      int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
    6.58 -      if(framesize >= 128) {
    6.59 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    6.60 -        emit_d8(cbuf,0xBC);
    6.61 -        emit_d8(cbuf,0x24);
    6.62 -        emit_d32(cbuf,framesize); // Find majik cookie from ESP
    6.63 -        emit_d32(cbuf, 0xbadb100d);
    6.64 -      }
    6.65 -      else {
    6.66 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    6.67 -        emit_d8(cbuf,0x7C);
    6.68 -        emit_d8(cbuf,0x24);
    6.69 -        emit_d8(cbuf,framesize); // Find majik cookie from ESP
    6.70 -        emit_d32(cbuf, 0xbadb100d);
    6.71 -      }
    6.72 -      // jmp EQ around INT3
    6.73 -      // QQQ TODO
    6.74 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
    6.75 -      emit_opcode(cbuf,0x74);
    6.76 -      emit_d8(cbuf, jump_around);
    6.77 -      // QQQ temporary
    6.78 -      emit_break(cbuf);
    6.79 -      // Die if stack mismatch
    6.80 -      // emit_opcode(cbuf,0xCC);
    6.81 -    }
    6.82 -  %}
    6.83 -
    6.84 -%}
    6.85 -
    6.86 -// INSTRUCTIONS -- Platform dependent
    6.87 -
    6.88 -//----------OS and Locking Instructions----------------------------------------
    6.89 -
    6.90 -// This name is KNOWN by the ADLC and cannot be changed.
    6.91 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    6.92 -// for this guy.
    6.93 -instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
    6.94 -  match(Set dst (ThreadLocal));
    6.95 -  effect(DEF dst, KILL cr);
    6.96 -
    6.97 -  format %{ "MOV    $dst, Thread::current()" %}
    6.98 -  ins_encode( linux_tlsencode(dst) );
    6.99 -  ins_pipe( ialu_reg_fat );
   6.100 -%}
   6.101 -
   6.102 -instruct TLS(eRegP dst) %{
   6.103 -  match(Set dst (ThreadLocal));
   6.104 -
   6.105 -  expand %{
   6.106 -    tlsLoadP(dst);
   6.107 -  %}
   6.108 -%}
   6.109 -
   6.110 -// Die now
   6.111 -instruct ShouldNotReachHere( )
   6.112 -%{
   6.113 -  match(Halt);
   6.114 -
   6.115 -  // Use the following format syntax
   6.116 -  format %{ "INT3   ; ShouldNotReachHere" %}
   6.117 -  // QQQ TODO for now call breakpoint
   6.118 -  // opcode(0xCC);
   6.119 -  // ins_encode(Opc);
   6.120 -  ins_encode(linux_breakpoint);
   6.121 -  ins_pipe( pipe_slow );
   6.122 -%}
   6.123 -
   6.124 -
   6.125 -
   6.126 -// Platform dependent source
   6.127 -
   6.128 -source %{
   6.129 -
   6.130 -// emit an interrupt that is caught by the debugger
   6.131 -void emit_break(CodeBuffer &cbuf) {
   6.132 -
   6.133 -  // Debugger doesn't really catch this but best we can do so far QQQ
   6.134 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   6.135 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   6.136 -}
   6.137 -
   6.138 -void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
   6.139 -  emit_break(cbuf);
   6.140 -}
   6.141 -
   6.142 -
   6.143 -uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
   6.144 -  return MachNode::size(ra_);
   6.145 -}
   6.146 -
   6.147 -%}

     7.1 --- a/src/os_cpu/linux_x86/vm/linux_x86_64.ad	Thu Feb 16 11:33:49 2012 -0800
     7.2 +++ b/src/os_cpu/linux_x86/vm/linux_x86_64.ad	Thu Feb 16 17:12:49 2012 -0800
     7.3 @@ -1,5 +1,5 @@
     7.4  //
     7.5 -// Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved.
     7.6 +// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
     7.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     7.8  //
     7.9  // This code is free software; you can redistribute it and/or modify it
    7.10 @@ -55,8 +55,7 @@
    7.11    // adding a syntax that specifies the sizes of fields in an order,
    7.12    // so that the adlc can build the emit functions automagically
    7.13  
    7.14 -  enc_class Java_To_Runtime(method meth)
    7.15 -  %{
    7.16 +  enc_class Java_To_Runtime(method meth) %{
    7.17      // No relocation needed
    7.18  
    7.19      // movq r10, <meth>
    7.20 @@ -70,105 +69,15 @@
    7.21      emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
    7.22    %}
    7.23  
    7.24 -  enc_class linux_breakpoint
    7.25 -  %{
    7.26 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    7.27 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    7.28 -  %}
    7.29 -
    7.30 -  enc_class call_epilog
    7.31 -  %{
    7.32 -    if (VerifyStackAtCalls) {
    7.33 -      // Check that stack depth is unchanged: find majik cookie on stack
    7.34 -      int framesize =
    7.35 -        ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
    7.36 -      if (framesize) {
    7.37 -        if (framesize < 0x80) {
    7.38 -          emit_opcode(cbuf, Assembler::REX_W);
    7.39 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    7.40 -          emit_d8(cbuf, 0x7C);
    7.41 -          emit_d8(cbuf, 0x24);
    7.42 -          emit_d8(cbuf, framesize); // Find majik cookie from ESP
    7.43 -          emit_d32(cbuf, 0xbadb100d);
    7.44 -        } else {
    7.45 -          emit_opcode(cbuf, Assembler::REX_W);
    7.46 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    7.47 -          emit_d8(cbuf, 0xBC);
    7.48 -          emit_d8(cbuf, 0x24);
    7.49 -          emit_d32(cbuf, framesize); // Find majik cookie from ESP
    7.50 -          emit_d32(cbuf, 0xbadb100d);
    7.51 -        }
    7.52 -      }
    7.53 -      // jmp EQ around INT3
    7.54 -      // QQQ TODO
    7.55 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
    7.56 -      emit_opcode(cbuf, 0x74);
    7.57 -      emit_d8(cbuf, jump_around);
    7.58 -      // QQQ temporary
    7.59 -      emit_break(cbuf);
    7.60 -      // Die if stack mismatch
    7.61 -      // emit_opcode(cbuf,0xCC);
    7.62 -    }
    7.63 -  %}
    7.64 -
    7.65 -%}
    7.66 -
    7.67 -// INSTRUCTIONS -- Platform dependent
    7.68 -
    7.69 -//----------OS and Locking Instructions----------------------------------------
    7.70 -
    7.71 -// This name is KNOWN by the ADLC and cannot be changed.
    7.72 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    7.73 -// for this guy.
    7.74 -instruct tlsLoadP(r15_RegP dst)
    7.75 -%{
    7.76 -  match(Set dst (ThreadLocal));
    7.77 -  effect(DEF dst);
    7.78 -
    7.79 -  size(0);
    7.80 -  format %{ "# TLS is in R15" %}
    7.81 -  ins_encode( /*empty encoding*/ );
    7.82 -  ins_pipe(ialu_reg_reg);
    7.83 -%}
    7.84 -
    7.85 -// Die now
    7.86 -instruct ShouldNotReachHere()
    7.87 -%{
    7.88 -  match(Halt);
    7.89 -
    7.90 -  // Use the following format syntax
    7.91 -  format %{ "int3\t# ShouldNotReachHere" %}
    7.92 -  // QQQ TODO for now call breakpoint
    7.93 -  // opcode(0xCC);
    7.94 -  // ins_encode(Opc);
    7.95 -  ins_encode(linux_breakpoint);
    7.96 -  ins_pipe(pipe_slow);
    7.97  %}
    7.98  
    7.99  
   7.100  // Platform dependent source
   7.101  
   7.102 -source
   7.103 -%{
   7.104 +source %{
   7.105  
   7.106  int MachCallRuntimeNode::ret_addr_offset() {
   7.107    return 13; // movq r10,#addr; callq (r10)
   7.108  }
   7.109  
   7.110 -// emit an interrupt that is caught by the debugger
   7.111 -void emit_break(CodeBuffer& cbuf) {
   7.112 -  // Debugger doesn't really catch this but best we can do so far QQQ
   7.113 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   7.114 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   7.115 -}
   7.116 -
   7.117 -void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
   7.118 -  emit_break(cbuf);
   7.119 -}
   7.120 -
   7.121 -uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
   7.122 -  // distance could be far and requires load and call through register
   7.123 -  return MachNode::size(ra_);
   7.124 -}
   7.125 -
   7.126  %}

     8.1 --- a/src/os_cpu/solaris_x86/vm/solaris_x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
     8.2 +++ b/src/os_cpu/solaris_x86/vm/solaris_x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
     8.3 @@ -1,5 +1,5 @@
     8.4  //
     8.5 -// Copyright (c) 1999, 2008, Oracle and/or its affiliates. All rights reserved.
     8.6 +// Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved.
     8.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     8.8  //
     8.9  // This code is free software; you can redistribute it and/or modify it
    8.10 @@ -24,144 +24,3 @@
    8.11  
    8.12  // X86 Solaris Architecture Description File
    8.13  
    8.14 -//----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
    8.15 -// This block specifies the encoding classes used by the compiler to output
    8.16 -// byte streams.  Encoding classes generate functions which are called by
    8.17 -// Machine Instruction Nodes in order to generate the bit encoding of the
    8.18 -// instruction.  Operands specify their base encoding interface with the
    8.19 -// interface keyword.  There are currently supported four interfaces,
    8.20 -// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
    8.21 -// operand to generate a function which returns its register number when
    8.22 -// queried.   CONST_INTER causes an operand to generate a function which
    8.23 -// returns the value of the constant when queried.  MEMORY_INTER causes an
    8.24 -// operand to generate four functions which return the Base Register, the
    8.25 -// Index Register, the Scale Value, and the Offset Value of the operand when
    8.26 -// queried.  COND_INTER causes an operand to generate six functions which
    8.27 -// return the encoding code (ie - encoding bits for the instruction)
    8.28 -// associated with each basic boolean condition for a conditional instruction.
    8.29 -// Instructions specify two basic values for encoding.  They use the
    8.30 -// ins_encode keyword to specify their encoding class (which must be one of
    8.31 -// the class names specified in the encoding block), and they use the
    8.32 -// opcode keyword to specify, in order, their primary, secondary, and
    8.33 -// tertiary opcode.  Only the opcode sections which a particular instruction
    8.34 -// needs for encoding need to be specified.
    8.35 -encode %{
    8.36 -  // Build emit functions for each basic byte or larger field in the intel
    8.37 -  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
    8.38 -  // code in the enc_class source block.  Emit functions will live in the
    8.39 -  // main source block for now.  In future, we can generalize this by
    8.40 -  // adding a syntax that specifies the sizes of fields in an order,
    8.41 -  // so that the adlc can build the emit functions automagically
    8.42 -
    8.43 -  enc_class solaris_tlsencode (eRegP dst) %{
    8.44 -    Register dstReg = as_Register($dst$$reg);
    8.45 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    8.46 -    masm->get_thread(dstReg);
    8.47 -  %}
    8.48 -
    8.49 -  enc_class solaris_breakpoint  %{
    8.50 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    8.51 -    // Really need to fix this
    8.52 -    masm->push(rax);
    8.53 -    masm->push(rcx);
    8.54 -    masm->push(rdx);
    8.55 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    8.56 -    masm->pop(rdx);
    8.57 -    masm->pop(rcx);
    8.58 -    masm->pop(rax);
    8.59 -  %}
    8.60 -
    8.61 -  enc_class call_epilog %{
    8.62 -    if( VerifyStackAtCalls ) {
    8.63 -      // Check that stack depth is unchanged: find majik cookie on stack
    8.64 -      int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
    8.65 -      if(framesize >= 128) {
    8.66 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    8.67 -        emit_d8(cbuf,0xBC);
    8.68 -        emit_d8(cbuf,0x24);
    8.69 -        emit_d32(cbuf,framesize); // Find majik cookie from ESP
    8.70 -        emit_d32(cbuf, 0xbadb100d);
    8.71 -      }
    8.72 -      else {
    8.73 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
    8.74 -        emit_d8(cbuf,0x7C);
    8.75 -        emit_d8(cbuf,0x24);
    8.76 -        emit_d8(cbuf,framesize); // Find majik cookie from ESP
    8.77 -        emit_d32(cbuf, 0xbadb100d);
    8.78 -      }
    8.79 -      // jmp EQ around INT3
    8.80 -      // QQQ TODO
    8.81 -      const int jump_around = 11; // size of call to breakpoint (and register preserve), 1 for CC
    8.82 -      emit_opcode(cbuf,0x74);
    8.83 -      emit_d8(cbuf, jump_around);
    8.84 -      // QQQ temporary
    8.85 -      emit_break(cbuf);
    8.86 -      // Die if stack mismatch
    8.87 -      // emit_opcode(cbuf,0xCC);
    8.88 -    }
    8.89 -  %}
    8.90 -
    8.91 -%}
    8.92 -
    8.93 -// INSTRUCTIONS -- Platform dependent
    8.94 -
    8.95 -//----------OS and Locking Instructions----------------------------------------
    8.96 -
    8.97 -// This name is KNOWN by the ADLC and cannot be changed.
    8.98 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    8.99 -// for this guy.
   8.100 -instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
   8.101 -  match(Set dst (ThreadLocal));
   8.102 -  effect(DEF dst, KILL cr);
   8.103 -
   8.104 -  format %{ "MOV    $dst, Thread::current()" %}
   8.105 -  ins_encode( solaris_tlsencode(dst) );
   8.106 -  ins_pipe( ialu_reg_fat );
   8.107 -%}
   8.108 -
   8.109 -instruct TLS(eRegP dst) %{
   8.110 -  match(Set dst (ThreadLocal));
   8.111 -
   8.112 -  expand %{
   8.113 -    tlsLoadP(dst);
   8.114 -  %}
   8.115 -%}
   8.116 -
   8.117 -// Die now
   8.118 -instruct ShouldNotReachHere( )
   8.119 -%{
   8.120 -  match(Halt);
   8.121 -
   8.122 -  // Use the following format syntax
   8.123 -  format %{ "INT3   ; ShouldNotReachHere" %}
   8.124 -  // QQQ TODO for now call breakpoint
   8.125 -  // opcode(0xCC);
   8.126 -  // ins_encode(Opc);
   8.127 -  ins_encode(solaris_breakpoint);
   8.128 -  ins_pipe( pipe_slow );
   8.129 -%}
   8.130 -
   8.131 -
   8.132 -
   8.133 -// Platform dependent source
   8.134 -
   8.135 -source %{
   8.136 -
   8.137 -// emit an interrupt that is caught by the debugger
   8.138 -void emit_break(CodeBuffer &cbuf) {
   8.139 -
   8.140 -  // Debugger doesn't really catch this but best we can do so far QQQ
   8.141 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   8.142 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   8.143 -}
   8.144 -
   8.145 -void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
   8.146 -  emit_break(cbuf);
   8.147 -}
   8.148 -
   8.149 -
   8.150 -uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
   8.151 -  return MachNode::size(ra_);
   8.152 -}
   8.153 -
   8.154 -%}

     9.1 --- a/src/os_cpu/solaris_x86/vm/solaris_x86_64.ad	Thu Feb 16 11:33:49 2012 -0800
     9.2 +++ b/src/os_cpu/solaris_x86/vm/solaris_x86_64.ad	Thu Feb 16 17:12:49 2012 -0800
     9.3 @@ -1,5 +1,5 @@
     9.4  //
     9.5 -// Copyright (c) 2004, 2006, Oracle and/or its affiliates. All rights reserved.
     9.6 +// Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved.
     9.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     9.8  //
     9.9  // This code is free software; you can redistribute it and/or modify it
    9.10 @@ -55,8 +55,7 @@
    9.11    // adding a syntax that specifies the sizes of fields in an order,
    9.12    // so that the adlc can build the emit functions automagically
    9.13  
    9.14 -  enc_class Java_To_Runtime(method meth)
    9.15 -  %{
    9.16 +  enc_class Java_To_Runtime(method meth) %{
    9.17      // No relocation needed
    9.18  
    9.19      // movq r10, <meth>
    9.20 @@ -70,118 +69,24 @@
    9.21      emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
    9.22    %}
    9.23  
    9.24 -  enc_class solaris_breakpoint
    9.25 -  %{
    9.26 -    MacroAssembler* masm = new MacroAssembler(&cbuf);
    9.27 -    masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
    9.28 -  %}
    9.29 -
    9.30 -  enc_class call_epilog
    9.31 -  %{
    9.32 -    if (VerifyStackAtCalls) {
    9.33 -      // Check that stack depth is unchanged: find majik cookie on stack
    9.34 -      int framesize =
    9.35 -        ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
    9.36 -      if (framesize) {
    9.37 -        if (framesize < 0x80) {
    9.38 -          emit_opcode(cbuf, Assembler::REX_W);
    9.39 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    9.40 -          emit_d8(cbuf, 0x7C);
    9.41 -          emit_d8(cbuf, 0x24);
    9.42 -          emit_d8(cbuf, framesize); // Find majik cookie from ESP
    9.43 -          emit_d32(cbuf, 0xbadb100d);
    9.44 -        } else {
    9.45 -          emit_opcode(cbuf, Assembler::REX_W);
    9.46 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
    9.47 -          emit_d8(cbuf, 0xBC);
    9.48 -          emit_d8(cbuf, 0x24);
    9.49 -          emit_d32(cbuf, framesize); // Find majik cookie from ESP
    9.50 -          emit_d32(cbuf, 0xbadb100d);
    9.51 -        }
    9.52 -      }
    9.53 -      // jmp EQ around INT3
    9.54 -      // QQQ TODO
    9.55 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
    9.56 -      emit_opcode(cbuf, 0x74);
    9.57 -      emit_d8(cbuf, jump_around);
    9.58 -      // QQQ temporary
    9.59 -      emit_break(cbuf);
    9.60 -      // Die if stack mismatch
    9.61 -      // emit_opcode(cbuf,0xCC);
    9.62 -    }
    9.63 -  %}
    9.64 -
    9.65    enc_class post_call_verify_mxcsr %{
    9.66 -    MacroAssembler masm(&cbuf);
    9.67 +    MacroAssembler _masm(&cbuf);
    9.68      if (RestoreMXCSROnJNICalls) {
    9.69 -      masm.ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
    9.70 +      __ ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
    9.71      }
    9.72      else if (CheckJNICalls) {
    9.73 -      masm.call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::amd64::verify_mxcsr_entry())));
    9.74 +      __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::amd64::verify_mxcsr_entry())));
    9.75      }
    9.76    %}
    9.77  %}
    9.78  
    9.79 -// INSTRUCTIONS -- Platform dependent
    9.80 -
    9.81 -//----------OS and Locking Instructions----------------------------------------
    9.82 -
    9.83 -// This name is KNOWN by the ADLC and cannot be changed.
    9.84 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    9.85 -// for this guy.
    9.86 -instruct tlsLoadP(r15_RegP dst)
    9.87 -%{
    9.88 -  match(Set dst (ThreadLocal));
    9.89 -  effect(DEF dst);
    9.90 -
    9.91 -  size(0);
    9.92 -  format %{ "# TLS is in R15" %}
    9.93 -  ins_encode( /*empty encoding*/ );
    9.94 -  ins_pipe(ialu_reg_reg);
    9.95 -%}
    9.96 -
    9.97 -// Die now
    9.98 -instruct ShouldNotReachHere()
    9.99 -%{
   9.100 -  match(Halt);
   9.101 -
   9.102 -  // Use the following format syntax
   9.103 -  format %{ "int3\t# ShouldNotReachHere" %}
   9.104 -  // QQQ TODO for now call breakpoint
   9.105 -  // opcode(0xCC);
   9.106 -  // ins_encode(Opc);
   9.107 -  ins_encode(solaris_breakpoint);
   9.108 -  ins_pipe(pipe_slow);
   9.109 -%}
   9.110 -
   9.111  
   9.112  // Platform dependent source
   9.113  
   9.114 -source
   9.115 -%{
   9.116 +source %{
   9.117  
   9.118 -int MachCallRuntimeNode::ret_addr_offset()
   9.119 -{
   9.120 +int MachCallRuntimeNode::ret_addr_offset() {
   9.121    return 13; // movq r10,#addr; callq (r10)
   9.122  }
   9.123  
   9.124 -// emit an interrupt that is caught by the debugger
   9.125 -void emit_break(CodeBuffer& cbuf)
   9.126 -{
   9.127 -  // Debugger doesn't really catch this but best we can do so far QQQ
   9.128 -  MacroAssembler* masm = new MacroAssembler(&cbuf);
   9.129 -  masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
   9.130 -}
   9.131 -
   9.132 -void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
   9.133 -{
   9.134 -  emit_break(cbuf);
   9.135 -}
   9.136 -
   9.137 -uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const
   9.138 -{
   9.139 -  // distance could be far and requires load and call through register
   9.140 -  return MachNode::size(ra_);
   9.141 -}
   9.142 -
   9.143  %}

    10.1 --- a/src/os_cpu/windows_x86/vm/windows_x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
    10.2 +++ b/src/os_cpu/windows_x86/vm/windows_x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
    10.3 @@ -1,5 +1,5 @@
    10.4  //
    10.5 -// Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
    10.6 +// Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved.
    10.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    10.8  //
    10.9  // This code is free software; you can redistribute it and/or modify it
   10.10 @@ -24,134 +24,3 @@
   10.11  
   10.12  // X86 Win32 Architecture Description File
   10.13  
   10.14 -//----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
   10.15 -// This block specifies the encoding classes used by the compiler to output
   10.16 -// byte streams.  Encoding classes generate functions which are called by
   10.17 -// Machine Instruction Nodes in order to generate the bit encoding of the
   10.18 -// instruction.  Operands specify their base encoding interface with the
   10.19 -// interface keyword.  There are currently supported four interfaces,
   10.20 -// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
   10.21 -// operand to generate a function which returns its register number when
   10.22 -// queried.   CONST_INTER causes an operand to generate a function which
   10.23 -// returns the value of the constant when queried.  MEMORY_INTER causes an
   10.24 -// operand to generate four functions which return the Base Register, the
   10.25 -// Index Register, the Scale Value, and the Offset Value of the operand when
   10.26 -// queried.  COND_INTER causes an operand to generate six functions which
   10.27 -// return the encoding code (ie - encoding bits for the instruction)
   10.28 -// associated with each basic boolean condition for a conditional instruction.
   10.29 -// Instructions specify two basic values for encoding.  They use the
   10.30 -// ins_encode keyword to specify their encoding class (which must be one of
   10.31 -// the class names specified in the encoding block), and they use the
   10.32 -// opcode keyword to specify, in order, their primary, secondary, and
   10.33 -// tertiary opcode.  Only the opcode sections which a particular instruction
   10.34 -// needs for encoding need to be specified.
   10.35 -encode %{
   10.36 -  // Build emit functions for each basic byte or larger field in the intel
   10.37 -  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
   10.38 -  // code in the enc_class source block.  Emit functions will live in the
   10.39 -  // main source block for now.  In future, we can generalize this by
   10.40 -  // adding a syntax that specifies the sizes of fields in an order,
   10.41 -  // so that the adlc can build the emit functions automagically
   10.42 -
   10.43 -  enc_class tlsencode (eRegP dst, eRegP src) %{
   10.44 -    emit_rm(cbuf, 0x2, $dst$$reg, $src$$reg);
   10.45 -    emit_d32(cbuf, ThreadLocalStorage::get_thread_ptr_offset() );
   10.46 -  %}
   10.47 -
   10.48 -  enc_class call_epilog %{
   10.49 -    if( VerifyStackAtCalls ) {
   10.50 -      // Check that stack depth is unchanged: find majik cookie on stack
   10.51 -      int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
   10.52 -      if(framesize >= 128) {
   10.53 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
   10.54 -        emit_d8(cbuf,0xBC);
   10.55 -        emit_d8(cbuf,0x24);
   10.56 -        emit_d32(cbuf,framesize); // Find majik cookie from ESP
   10.57 -        emit_d32(cbuf, 0xbadb100d);
   10.58 -      }
   10.59 -      else {
   10.60 -        emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
   10.61 -        emit_d8(cbuf,0x7C);
   10.62 -        emit_d8(cbuf,0x24);
   10.63 -        emit_d8(cbuf,framesize); // Find majik cookie from ESP
   10.64 -        emit_d32(cbuf, 0xbadb100d);
   10.65 -      }
   10.66 -      // jmp EQ around INT3
   10.67 -      emit_opcode(cbuf,0x74);
   10.68 -      emit_d8(cbuf,1);
   10.69 -      // Die if stack mismatch
   10.70 -      emit_opcode(cbuf,0xCC);
   10.71 -    }
   10.72 -  %}
   10.73 -
   10.74 -%}
   10.75 -
   10.76 -// INSTRUCTIONS -- Platform dependent
   10.77 -
   10.78 -
   10.79 -//----------OS and Locking Instructions----------------------------------------
   10.80 -
   10.81 -// The prefix of this name is KNOWN by the ADLC and cannot be changed.
   10.82 -instruct tlsLoadP_prefixLoadP(eRegP t1) %{
   10.83 -  effect(DEF t1);
   10.84 -
   10.85 -  format %{ "MOV    $t1,FS:[0x00] "%}
   10.86 -  opcode(0x8B, 0x64);
   10.87 -  ins_encode(OpcS, OpcP, conmemref(t1));
   10.88 -  ins_pipe( ialu_reg_fat );
   10.89 -%}
   10.90 -
   10.91 -// This name is KNOWN by the ADLC and cannot be changed.
   10.92 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
   10.93 -// for this guy.
   10.94 -// %%% Should do this with a clause like:  bottom_type(TypeRawPtr::BOTTOM);
   10.95 -instruct tlsLoadP(eRegP dst, eRegP t1) %{
   10.96 -  effect(DEF dst, USE t1);
   10.97 -
   10.98 -  format %{ "MOV    $dst,[$t1 + TLS::thread_ptr_offset()]" %}
   10.99 -  opcode(0x8B);
  10.100 -  ins_encode(OpcP, tlsencode(dst, t1));
  10.101 -  ins_pipe( ialu_reg_reg_fat );
  10.102 -%}
  10.103 -
  10.104 -instruct TLS(eRegP dst) %{
  10.105 -  match(Set dst (ThreadLocal));
  10.106 -  expand %{
  10.107 -    eRegP t1;
  10.108 -    tlsLoadP_prefixLoadP(t1);
  10.109 -    tlsLoadP(dst, t1);
  10.110 -  %}
  10.111 -%}
  10.112 -
  10.113 -// Die now
  10.114 -instruct ShouldNotReachHere( )
  10.115 -%{
  10.116 -  match(Halt);
  10.117 -  // Use the following format syntax
  10.118 -  format %{ "INT3   ; ShouldNotReachHere" %}
  10.119 -  opcode(0xCC);
  10.120 -  ins_encode(OpcP);
  10.121 -  ins_pipe( pipe_slow );
  10.122 -%}
  10.123 -
  10.124 -//
  10.125 -// Platform dependent source
  10.126 -//
  10.127 -source %{
  10.128 -
  10.129 -// emit an interrupt that is caught by the debugger
  10.130 -void emit_break(CodeBuffer &cbuf) {
  10.131 -  cbuf.insts()->emit_int8((unsigned char) 0xcc);
  10.132 -}
  10.133 -
  10.134 -void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  10.135 -  emit_break(cbuf);
  10.136 -}
  10.137 -
  10.138 -
  10.139 -uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
  10.140 -  return 1;
  10.141 -}
  10.142 -
  10.143 -
  10.144 -%}

    11.1 --- a/src/os_cpu/windows_x86/vm/windows_x86_64.ad	Thu Feb 16 11:33:49 2012 -0800
    11.2 +++ b/src/os_cpu/windows_x86/vm/windows_x86_64.ad	Thu Feb 16 17:12:49 2012 -0800
    11.3 @@ -1,5 +1,5 @@
    11.4  //
    11.5 -// Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
    11.6 +// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
    11.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    11.8  //
    11.9  // This code is free software; you can redistribute it and/or modify it
   11.10 @@ -67,69 +67,6 @@
   11.11      emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
   11.12    %}
   11.13  
   11.14 -  enc_class call_epilog %{
   11.15 -    if (VerifyStackAtCalls) {
   11.16 -      // Check that stack depth is unchanged: find majik cookie on stack
   11.17 -      int framesize =
   11.18 -        ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
   11.19 -      if (framesize) {
   11.20 -        if (framesize < 0x80) {
   11.21 -          emit_opcode(cbuf, Assembler::REX_W);
   11.22 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
   11.23 -          emit_d8(cbuf, 0x7C);
   11.24 -          emit_d8(cbuf, 0x24);
   11.25 -          emit_d8(cbuf, framesize); // Find majik cookie from ESP
   11.26 -          emit_d32(cbuf, 0xbadb100d);
   11.27 -        } else {
   11.28 -          emit_opcode(cbuf, Assembler::REX_W);
   11.29 -          emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
   11.30 -          emit_d8(cbuf, 0xBC);
   11.31 -          emit_d8(cbuf, 0x24);
   11.32 -          emit_d32(cbuf, framesize); // Find majik cookie from ESP
   11.33 -          emit_d32(cbuf, 0xbadb100d);
   11.34 -        }
   11.35 -      }
   11.36 -      // jmp EQ around INT3
   11.37 -      // QQQ TODO
   11.38 -      const int jump_around = 5; // size of call to breakpoint, 1 for CC
   11.39 -      emit_opcode(cbuf, 0x74);
   11.40 -      emit_d8(cbuf, jump_around);
   11.41 -      // QQQ temporary
   11.42 -      emit_break(cbuf);
   11.43 -      // Die if stack mismatch
   11.44 -      // emit_opcode(cbuf,0xCC);
   11.45 -    }
   11.46 -  %}
   11.47 -%}
   11.48 -
   11.49 -// INSTRUCTIONS -- Platform dependent
   11.50 -
   11.51 -
   11.52 -//----------OS and Locking Instructions----------------------------------------
   11.53 -
   11.54 -// This name is KNOWN by the ADLC and cannot be changed.
   11.55 -// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
   11.56 -// for this guy.
   11.57 -instruct tlsLoadP(r15_RegP dst)
   11.58 -%{
   11.59 -  match(Set dst (ThreadLocal));
   11.60 -  effect(DEF dst);
   11.61 -
   11.62 -  size(0);
   11.63 -  format %{ "# TLS is in R15" %}
   11.64 -  ins_encode( /*empty encoding*/ );
   11.65 -  ins_pipe(ialu_reg_reg);
   11.66 -%}
   11.67 -
   11.68 -// Die now
   11.69 -instruct ShouldNotReachHere( )
   11.70 -%{
   11.71 -  match(Halt);
   11.72 -  // Use the following format syntax
   11.73 -  format %{ "INT3   ; ShouldNotReachHere" %}
   11.74 -  opcode(0xCC);
   11.75 -  ins_encode(OpcP);
   11.76 -  ins_pipe( pipe_slow );
   11.77  %}
   11.78  
   11.79  //
   11.80 @@ -142,17 +79,4 @@
   11.81    return 13; // movq r10,#addr; callq (r10)
   11.82  }
   11.83  
   11.84 -// emit an interrupt that is caught by the debugger
   11.85 -void emit_break(CodeBuffer &cbuf) {
   11.86 -  cbuf.insts()->emit_int8((unsigned char) 0xcc);
   11.87 -}
   11.88 -
   11.89 -void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
   11.90 -  emit_break(cbuf);
   11.91 -}
   11.92 -
   11.93 -uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
   11.94 -  return 1;
   11.95 -}
   11.96 -
   11.97  %}

    12.1 --- a/src/share/vm/opto/chaitin.cpp	Thu Feb 16 11:33:49 2012 -0800
    12.2 +++ b/src/share/vm/opto/chaitin.cpp	Thu Feb 16 17:12:49 2012 -0800
    12.3 @@ -1,5 +1,5 @@
    12.4  /*
    12.5 - * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
    12.6 + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
    12.7   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    12.8   *
    12.9   * This code is free software; you can redistribute it and/or modify it
   12.10 @@ -1946,18 +1946,29 @@
   12.11      reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
   12.12  
   12.13    // Preserve area dump
   12.14 +  int fixed_slots = C->fixed_slots();
   12.15 +  OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
   12.16 +  OptoReg::Name return_addr = _matcher.return_addr();
   12.17 +
   12.18    reg = OptoReg::add(reg, -1);
   12.19 -  while( OptoReg::is_stack(reg)) {
   12.20 +  while (OptoReg::is_stack(reg)) {
   12.21      tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
   12.22 -    if( _matcher.return_addr() == reg )
   12.23 +    if (return_addr == reg) {
   12.24        tty->print_cr("return address");
   12.25 -    else if( _matcher.return_addr() == OptoReg::add(reg,1) &&
   12.26 -             VerifyStackAtCalls )
   12.27 -      tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
   12.28 -    else if ((int)OptoReg::reg2stack(reg) < C->fixed_slots())
   12.29 +    } else if (reg >= begin_in_preserve) {
   12.30 +      // Preserved slots are present on x86
   12.31 +      if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
   12.32 +        tty->print_cr("saved fp register");
   12.33 +      else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
   12.34 +               VerifyStackAtCalls)
   12.35 +        tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
   12.36 +      else
   12.37 +        tty->print_cr("in_preserve");
   12.38 +    } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
   12.39        tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
   12.40 -    else
   12.41 -      tty->print_cr("pad2, in_preserve");
   12.42 +    } else {
   12.43 +      tty->print_cr("pad2, stack alignment");
   12.44 +    }
   12.45      reg = OptoReg::add(reg, -1);
   12.46    }
   12.47