src/cpu/x86/vm/x86_32.ad

changeset 3577
9b8ce46870df
parent 3574
fd8114661503
child 3637
61b82be3b1ff
     1.1 --- a/src/cpu/x86/vm/x86_32.ad	Thu Feb 16 11:33:49 2012 -0800
     1.2 +++ b/src/cpu/x86/vm/x86_32.ad	Thu Feb 16 17:12:49 2012 -0800
     1.3 @@ -1,5 +1,5 @@
     1.4  //
     1.5 -// Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
     1.6 +// Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
     1.7  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.8  //
     1.9  // This code is free software; you can redistribute it and/or modify it
    1.10 @@ -341,12 +341,6 @@
    1.11    return round_to(current_offset, alignment_required()) - current_offset;
    1.12  }
    1.13  
    1.14 -#ifndef PRODUCT
    1.15 -void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
    1.16 -  st->print("INT3");
    1.17 -}
    1.18 -#endif
    1.19 -
    1.20  // EMIT_RM()
    1.21  void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
    1.22    unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
    1.23 @@ -1117,7 +1111,7 @@
    1.24  }
    1.25  
    1.26  #ifndef PRODUCT
    1.27 -void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
    1.28 +void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
    1.29    implementation( NULL, ra_, false, st );
    1.30  }
    1.31  #endif
    1.32 @@ -1130,22 +1124,6 @@
    1.33    return implementation( NULL, ra_, true, NULL );
    1.34  }
    1.35  
    1.36 -//=============================================================================
    1.37 -#ifndef PRODUCT
    1.38 -void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
    1.39 -  st->print("NOP \t# %d bytes pad for loops and calls", _count);
    1.40 -}
    1.41 -#endif
    1.42 -
    1.43 -void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
    1.44 -  MacroAssembler _masm(&cbuf);
    1.45 -  __ nop(_count);
    1.46 -}
    1.47 -
    1.48 -uint MachNopNode::size(PhaseRegAlloc *) const {
    1.49 -  return _count;
    1.50 -}
    1.51 -
    1.52  
    1.53  //=============================================================================
    1.54  #ifndef PRODUCT
    1.55 @@ -1831,21 +1809,6 @@
    1.56      }
    1.57    %}
    1.58  
    1.59 -  enc_class preserve_SP %{
    1.60 -    debug_only(int off0 = cbuf.insts_size());
    1.61 -    MacroAssembler _masm(&cbuf);
    1.62 -    // RBP is preserved across all calls, even compiled calls.
    1.63 -    // Use it to preserve RSP in places where the callee might change the SP.
    1.64 -    __ movptr(rbp_mh_SP_save, rsp);
    1.65 -    debug_only(int off1 = cbuf.insts_size());
    1.66 -    assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
    1.67 -  %}
    1.68 -
    1.69 -  enc_class restore_SP %{
    1.70 -    MacroAssembler _masm(&cbuf);
    1.71 -    __ movptr(rsp, rbp_mh_SP_save);
    1.72 -  %}
    1.73 -
    1.74    enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
    1.75      // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
    1.76      // who we intended to call.
    1.77 @@ -3794,9 +3757,9 @@
    1.78    // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
    1.79    // Otherwise, it is above the locks and verification slot and alignment word
    1.80    return_addr(STACK - 1 +
    1.81 -              round_to(1+VerifyStackAtCalls+
    1.82 -              Compile::current()->fixed_slots(),
    1.83 -              (StackAlignmentInBytes/wordSize)));
    1.84 +              round_to((Compile::current()->in_preserve_stack_slots() +
    1.85 +                        Compile::current()->fixed_slots()),
    1.86 +                       stack_alignment_in_slots()));
    1.87  
    1.88    // Body of function which returns an integer array locating
    1.89    // arguments either in registers or in stack slots.  Passed an array
    1.90 @@ -13424,6 +13387,25 @@
    1.91    ins_pipe( ialu_reg_mem );
    1.92  %}
    1.93  
    1.94 +
    1.95 +// ============================================================================
    1.96 +// This name is KNOWN by the ADLC and cannot be changed.
    1.97 +// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
    1.98 +// for this guy.
    1.99 +instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
   1.100 +  match(Set dst (ThreadLocal));
   1.101 +  effect(DEF dst, KILL cr);
   1.102 +
   1.103 +  format %{ "MOV    $dst, Thread::current()" %}
   1.104 +  ins_encode %{
   1.105 +    Register dstReg = as_Register($dst$$reg);
   1.106 +    __ get_thread(dstReg);
   1.107 +  %}
   1.108 +  ins_pipe( ialu_reg_fat );
   1.109 +%}
   1.110 +
   1.111 +
   1.112 +
   1.113  //----------PEEPHOLE RULES-----------------------------------------------------
   1.114  // These must follow all instruction definitions as they use the names
   1.115  // defined in the instructions definitions.

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