Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/ppc/vm/assembler_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
     1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
     1.3 @@ -1,6 +1,6 @@
     1.4  /*
     1.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     1.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     1.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     1.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.9   *
    1.10   * This code is free software; you can redistribute it and/or modify it
    1.11 @@ -24,7 +24,6 @@
    1.12   */
    1.13  
    1.14  #include "precompiled.hpp"
    1.15 -#include "asm/assembler.hpp"
    1.16  #include "asm/assembler.inline.hpp"
    1.17  #include "gc_interface/collectedHeap.inline.hpp"
    1.18  #include "interpreter/interpreter.hpp"
    1.19 @@ -37,6 +36,7 @@
    1.20  #include "runtime/os.hpp"
    1.21  #include "runtime/sharedRuntime.hpp"
    1.22  #include "runtime/stubRoutines.hpp"
    1.23 +#include "utilities/macros.hpp"
    1.24  #if INCLUDE_ALL_GCS
    1.25  #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
    1.26  #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
    1.27 @@ -384,10 +384,10 @@
    1.28        bool load_xa = (xa != 0) || (xb < 0);
    1.29        bool return_xd = false;
    1.30  
    1.31 -      if (load_xa) lis(tmp, xa);
    1.32 -      if (xc) lis(d, xc);
    1.33 +      if (load_xa) { lis(tmp, xa); }
    1.34 +      if (xc) { lis(d, xc); }
    1.35        if (load_xa) {
    1.36 -        if (xb) ori(tmp, tmp, xb); // No addi, we support tmp == R0.
    1.37 +        if (xb) { ori(tmp, tmp, (unsigned short)xb); } // No addi, we support tmp == R0.
    1.38        } else {
    1.39          li(tmp, xb); // non-negative
    1.40        }
    1.41 @@ -409,18 +409,18 @@
    1.42      // opt 4: avoid adding 0
    1.43      if (xa) { // Highest 16-bit needed?
    1.44        lis(d, xa);
    1.45 -      if (xb) addi(d, d, xb);
    1.46 +      if (xb) { addi(d, d, xb); }
    1.47      } else {
    1.48        li(d, xb);
    1.49      }
    1.50      sldi(d, d, 32);
    1.51 -    if (xc) addis(d, d, xc);
    1.52 +    if (xc) { addis(d, d, xc); }
    1.53    }
    1.54  
    1.55    // opt 5: Return offset to be inserted into following instruction.
    1.56    if (return_simm16_rest) return xd;
    1.57  
    1.58 -  if (xd) addi(d, d, xd);
    1.59 +  if (xd) { addi(d, d, xd); }
    1.60    return 0;
    1.61  }
    1.62  
    1.63 @@ -696,4 +696,5 @@
    1.64    tty->print_cr("\ntest_asm disassembly (0x%lx 0x%lx):", code()->insts_begin(), code()->insts_end());
    1.65    code()->decode();
    1.66  }
    1.67 +
    1.68  #endif // !PRODUCT

     2.1 --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Thu Feb 20 14:44:33 2014 +0100
     2.2 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Thu Mar 20 11:03:06 2014 +0100
     2.3 @@ -1,6 +1,6 @@
     2.4  /*
     2.5   * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
     2.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     2.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     2.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     2.9   *
    2.10   * This code is free software; you can redistribute it and/or modify it
    2.11 @@ -139,7 +139,8 @@
    2.12  inline void Assembler::cmplw( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 0, a, b); }
    2.13  inline void Assembler::cmpld( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 1, a, b); }
    2.14  
    2.15 -inline void Assembler::isel(Register d, Register a, Register b, int c) { emit_int32(ISEL_OPCODE    | rt(d)  | ra(a) | rb(b) | bc(c)); }
    2.16 +inline void Assembler::isel(Register d, Register a, Register b, int c) { guarantee(VM_Version::has_isel(), "opcode not supported on this hardware");
    2.17 +                                                                         emit_int32(ISEL_OPCODE    | rt(d)  | ra(a) | rb(b) | bc(c)); }
    2.18  
    2.19  // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
    2.20  inline void Assembler::andi_(   Register a, Register s, int ui16)      { emit_int32(ANDI_OPCODE    | rta(a) | rs(s) | uimm(ui16, 16)); }
    2.21 @@ -531,9 +532,12 @@
    2.22  //inline void Assembler::mffgpr( FloatRegister d, Register b)   { emit_int32( MFFGPR_OPCODE | frt(d) | rb(b) | rc(0)); }
    2.23  //inline void Assembler::mftgpr( Register d, FloatRegister b)   { emit_int32( MFTGPR_OPCODE | rt(d) | frb(b) | rc(0)); }
    2.24  // add cmpb and popcntb to detect ppc power version.
    2.25 -inline void Assembler::cmpb(   Register a, Register s, Register b) { emit_int32( CMPB_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
    2.26 -inline void Assembler::popcntb(Register a, Register s)             { emit_int32( POPCNTB_OPCODE | rta(a) | rs(s)); };
    2.27 -inline void Assembler::popcntw(Register a, Register s)             { emit_int32( POPCNTW_OPCODE | rta(a) | rs(s)); };
    2.28 +inline void Assembler::cmpb(   Register a, Register s, Register b) { guarantee(VM_Version::has_cmpb(), "opcode not supported on this hardware");
    2.29 +                                                                     emit_int32( CMPB_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
    2.30 +inline void Assembler::popcntb(Register a, Register s)             { guarantee(VM_Version::has_popcntb(), "opcode not supported on this hardware");
    2.31 +                                                                     emit_int32( POPCNTB_OPCODE | rta(a) | rs(s)); };
    2.32 +inline void Assembler::popcntw(Register a, Register s)             { guarantee(VM_Version::has_popcntw(), "opcode not supported on this hardware");
    2.33 +                                                                     emit_int32( POPCNTW_OPCODE | rta(a) | rs(s)); };
    2.34  inline void Assembler::popcntd(Register a, Register s)             { emit_int32( POPCNTD_OPCODE | rta(a) | rs(s)); };
    2.35  
    2.36  inline void Assembler::fneg(  FloatRegister d, FloatRegister b) { emit_int32( FNEG_OPCODE  | frt(d) | frb(b) | rc(0)); }
    2.37 @@ -568,14 +572,17 @@
    2.38  inline void Assembler::fctiw( FloatRegister d, FloatRegister b) { emit_int32( FCTIW_OPCODE  | frt(d) | frb(b) | rc(0)); }
    2.39  inline void Assembler::fctiwz(FloatRegister d, FloatRegister b) { emit_int32( FCTIWZ_OPCODE | frt(d) | frb(b) | rc(0)); }
    2.40  inline void Assembler::fcfid( FloatRegister d, FloatRegister b) { emit_int32( FCFID_OPCODE  | frt(d) | frb(b) | rc(0)); }
    2.41 -inline void Assembler::fcfids(FloatRegister d, FloatRegister b) { emit_int32( FCFIDS_OPCODE | frt(d) | frb(b) | rc(0)); }
    2.42 +inline void Assembler::fcfids(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fcfids(), "opcode not supported on this hardware");
    2.43 +                                                                  emit_int32( FCFIDS_OPCODE | frt(d) | frb(b) | rc(0)); }
    2.44  
    2.45  // PPC 1, section 4.6.7 Floating-Point Compare Instructions
    2.46  inline void Assembler::fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b) { emit_int32( FCMPU_OPCODE | bf(crx) | fra(a) | frb(b)); }
    2.47  
    2.48  // PPC 1, section 5.2.1 Floating-Point Arithmetic Instructions
    2.49 -inline void Assembler::fsqrt( FloatRegister d, FloatRegister b) { emit_int32( FSQRT_OPCODE  | frt(d) | frb(b) | rc(0)); }
    2.50 -inline void Assembler::fsqrts(FloatRegister d, FloatRegister b) { emit_int32( FSQRTS_OPCODE | frt(d) | frb(b) | rc(0)); }
    2.51 +inline void Assembler::fsqrt( FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrt(), "opcode not supported on this hardware");
    2.52 +                                                                  emit_int32( FSQRT_OPCODE  | frt(d) | frb(b) | rc(0)); }
    2.53 +inline void Assembler::fsqrts(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrts(), "opcode not supported on this hardware");
    2.54 +                                                                  emit_int32( FSQRTS_OPCODE | frt(d) | frb(b) | rc(0)); }
    2.55  
    2.56  // Vector instructions for >= Power6.
    2.57  inline void Assembler::lvebx( VectorRegister d, Register s1, Register s2) { emit_int32( LVEBX_OPCODE  | vrt(d) | ra0mem(s1) | rb(s2)); }
    2.58 @@ -703,7 +710,8 @@
    2.59  inline void Assembler::vcmpgtub_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
    2.60  inline void Assembler::vcmpgtuh_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
    2.61  inline void Assembler::vcmpgtuw_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
    2.62 -inline void Assembler::vand(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAND_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
    2.63 +inline void Assembler::vand(    VectorRegister d, VectorRegister a, VectorRegister b) { guarantee(VM_Version::has_vand(), "opcode not supported on this hardware");
    2.64 +                                                                                        emit_int32( VAND_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
    2.65  inline void Assembler::vandc(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VANDC_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
    2.66  inline void Assembler::vnor(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNOR_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
    2.67  inline void Assembler::vor(     VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VOR_OPCODE      | vrt(d) | vra(a) | vrb(b)); }

     3.1 --- a/src/cpu/ppc/vm/c2_globals_ppc.hpp	Thu Feb 20 14:44:33 2014 +0100
     3.2 +++ b/src/cpu/ppc/vm/c2_globals_ppc.hpp	Thu Mar 20 11:03:06 2014 +0100
     3.3 @@ -1,6 +1,6 @@
     3.4  /*
     3.5   * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
     3.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     3.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     3.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     3.9   *
    3.10   * This code is free software; you can redistribute it and/or modify it
    3.11 @@ -87,7 +87,7 @@
    3.12  define_pd_global(uintx, CodeCacheMinBlockLength,     4);
    3.13  define_pd_global(uintx, CodeCacheMinimumUseSpace,    400*K);
    3.14  
    3.15 -define_pd_global(bool,  TrapBasedRangeChecks,        false);
    3.16 +define_pd_global(bool,  TrapBasedRangeChecks,        true);
    3.17  
    3.18  // Heap related flags
    3.19  define_pd_global(uintx,MetaspaceSize,                ScaleForWordSize(16*M));

     4.1 --- a/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
     4.2 +++ b/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
     4.3 @@ -1,6 +1,6 @@
     4.4  /*
     4.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     4.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     4.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     4.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4.9   *
    4.10   * This code is free software; you can redistribute it and/or modify it
    4.11 @@ -24,8 +24,6 @@
    4.12   */
    4.13  
    4.14  #include "precompiled.hpp"
    4.15 -#include "asm/assembler.hpp"
    4.16 -#include "asm/assembler.inline.hpp"
    4.17  #include "asm/macroAssembler.inline.hpp"
    4.18  #include "compiler/disassembler.hpp"
    4.19  #include "gc_interface/collectedHeap.inline.hpp"
    4.20 @@ -1120,7 +1118,7 @@
    4.21    }
    4.22    return _last_calls_return_pc;
    4.23  }
    4.24 -#endif
    4.25 +#endif // ABI_ELFv2
    4.26  
    4.27  void MacroAssembler::call_VM_base(Register oop_result,
    4.28                                    Register last_java_sp,
    4.29 @@ -1794,7 +1792,7 @@
    4.30    cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
    4.31    bne(cr_reg, cas_label);
    4.32  
    4.33 -  load_klass_with_trap_null_check(temp_reg, obj_reg);
    4.34 +  load_klass(temp_reg, obj_reg);
    4.35  
    4.36    load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
    4.37    ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
    4.38 @@ -1891,7 +1889,7 @@
    4.39    // the bias from one thread to another directly in this situation.
    4.40    andi(temp_reg, mark_reg, markOopDesc::age_mask_in_place);
    4.41    orr(temp_reg, R16_thread, temp_reg);
    4.42 -  load_klass_with_trap_null_check(temp2_reg, obj_reg);
    4.43 +  load_klass(temp2_reg, obj_reg);
    4.44    ld(temp2_reg, in_bytes(Klass::prototype_header_offset()), temp2_reg);
    4.45    orr(temp_reg, temp_reg, temp2_reg);
    4.46  
    4.47 @@ -1927,7 +1925,7 @@
    4.48    // that another thread raced us for the privilege of revoking the
    4.49    // bias of this particular object, so it's okay to continue in the
    4.50    // normal locking code.
    4.51 -  load_klass_with_trap_null_check(temp_reg, obj_reg);
    4.52 +  load_klass(temp_reg, obj_reg);
    4.53    ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
    4.54    andi(temp2_reg, mark_reg, markOopDesc::age_mask_in_place);
    4.55    orr(temp_reg, temp_reg, temp2_reg);
    4.56 @@ -2213,8 +2211,7 @@
    4.57    stbx(R0, Rtmp, Robj);
    4.58  }
    4.59  
    4.60 -#ifndef SERIALGC
    4.61 -
    4.62 +#if INCLUDE_ALL_GCS
    4.63  // General G1 pre-barrier generator.
    4.64  // Goal: record the previous value if it is not null.
    4.65  void MacroAssembler::g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val,
    4.66 @@ -2328,14 +2325,17 @@
    4.67  
    4.68    // Get the address of the card.
    4.69    lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr);
    4.70 -
    4.71 -  assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
    4.72 -  cmpwi(CCR0, Rtmp3 /* card value */, 0);
    4.73 +  cmpwi(CCR0, Rtmp3, (int)G1SATBCardTableModRefBS::g1_young_card_val());
    4.74 +  beq(CCR0, filtered);
    4.75 +
    4.76 +  membar(Assembler::StoreLoad);
    4.77 +  lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr);  // Reload after membar.
    4.78 +  cmpwi(CCR0, Rtmp3 /* card value */, CardTableModRefBS::dirty_card_val());
    4.79    beq(CCR0, filtered);
    4.80  
    4.81    // Storing a region crossing, non-NULL oop, card is clean.
    4.82    // Dirty card and log.
    4.83 -  li(Rtmp3, 0); // dirty
    4.84 +  li(Rtmp3, CardTableModRefBS::dirty_card_val());
    4.85    //release(); // G1: oops are allowed to get visible after dirty marking.
    4.86    stbx(Rtmp3, Rbase, Rcard_addr);
    4.87  
    4.88 @@ -2362,7 +2362,7 @@
    4.89  
    4.90    bind(filtered_int);
    4.91  }
    4.92 -#endif // SERIALGC
    4.93 +#endif // INCLUDE_ALL_GCS
    4.94  
    4.95  // Values for last_Java_pc, and last_Java_sp must comply to the rules
    4.96  // in frame_ppc64.hpp.
    4.97 @@ -2453,7 +2453,8 @@
    4.98  void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
    4.99    Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided.
   4.100    if (Universe::narrow_klass_base() != 0) {
   4.101 -    load_const(R0, Universe::narrow_klass_base(), (dst != current) ? dst : noreg); // Use dst as temp if it is free.
   4.102 +    // Use dst as temp if it is free.
   4.103 +    load_const(R0, Universe::narrow_klass_base(), (dst != current && dst != R0) ? dst : noreg);
   4.104      sub(dst, current, R0);
   4.105      current = dst;
   4.106    }

     5.1 --- a/src/cpu/ppc/vm/macroAssembler_ppc.hpp	Thu Feb 20 14:44:33 2014 +0100
     5.2 +++ b/src/cpu/ppc/vm/macroAssembler_ppc.hpp	Thu Mar 20 11:03:06 2014 +0100
     5.3 @@ -514,14 +514,14 @@
     5.4    void card_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp);
     5.5    void card_table_write(jbyte* byte_map_base, Register Rtmp, Register Robj);
     5.6  
     5.7 -#ifndef SERIALGC
     5.8 +#if INCLUDE_ALL_GCS
     5.9    // General G1 pre-barrier generator.
    5.10    void g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val,
    5.11                              Register Rtmp1, Register Rtmp2, bool needs_frame = false);
    5.12    // General G1 post-barrier generator
    5.13    void g1_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp1,
    5.14                               Register Rtmp2, Register Rtmp3, Label *filtered_ext = NULL);
    5.15 -#endif // SERIALGC
    5.16 +#endif
    5.17  
    5.18    // Support for managing the JavaThread pointer (i.e.; the reference to
    5.19    // thread-local information).

     6.1 --- a/src/cpu/ppc/vm/methodHandles_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
     6.2 +++ b/src/cpu/ppc/vm/methodHandles_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
     6.3 @@ -1,6 +1,6 @@
     6.4  /*
     6.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     6.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     6.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     6.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     6.9   *
    6.10   * This code is free software; you can redistribute it and/or modify it
    6.11 @@ -119,6 +119,7 @@
    6.12  
    6.13  void MethodHandles::jump_from_method_handle(MacroAssembler* _masm, Register method, Register target, Register temp,
    6.14                                              bool for_compiler_entry) {
    6.15 +  Label L_no_such_method;
    6.16    assert(method == R19_method, "interpreter calling convention");
    6.17    assert_different_registers(method, target, temp);
    6.18  
    6.19 @@ -131,17 +132,31 @@
    6.20      __ lwz(temp, in_bytes(JavaThread::interp_only_mode_offset()), R16_thread);
    6.21      __ cmplwi(CCR0, temp, 0);
    6.22      __ beq(CCR0, run_compiled_code);
    6.23 +    // Null method test is replicated below in compiled case,
    6.24 +    // it might be able to address across the verify_thread()
    6.25 +    __ cmplwi(CCR0, R19_method, 0);
    6.26 +    __ beq(CCR0, L_no_such_method);
    6.27      __ ld(target, in_bytes(Method::interpreter_entry_offset()), R19_method);
    6.28      __ mtctr(target);
    6.29      __ bctr();
    6.30      __ BIND(run_compiled_code);
    6.31    }
    6.32  
    6.33 +  // Compiled case, either static or fall-through from runtime conditional
    6.34 +  __ cmplwi(CCR0, R19_method, 0);
    6.35 +  __ beq(CCR0, L_no_such_method);
    6.36 +
    6.37    const ByteSize entry_offset = for_compiler_entry ? Method::from_compiled_offset() :
    6.38                                                       Method::from_interpreted_offset();
    6.39    __ ld(target, in_bytes(entry_offset), R19_method);
    6.40    __ mtctr(target);
    6.41    __ bctr();
    6.42 +
    6.43 +  __ bind(L_no_such_method);
    6.44 +  assert(StubRoutines::throw_AbstractMethodError_entry() != NULL, "not yet generated!");
    6.45 +  __ load_const_optimized(target, StubRoutines::throw_AbstractMethodError_entry());
    6.46 +  __ mtctr(target);
    6.47 +  __ bctr();
    6.48  }
    6.49  
    6.50  

     7.1 --- a/src/cpu/ppc/vm/ppc.ad	Thu Feb 20 14:44:33 2014 +0100
     7.2 +++ b/src/cpu/ppc/vm/ppc.ad	Thu Mar 20 11:03:06 2014 +0100
     7.3 @@ -8777,6 +8777,7 @@
     7.4  // Single-precision sqrt.
     7.5  instruct sqrtF_reg(regF dst, regF src) %{
     7.6    match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
     7.7 +  predicate(VM_Version::has_fsqrts());
     7.8    ins_cost(DEFAULT_COST);
     7.9  
    7.10    format %{ "FSQRTS  $dst, $src" %}
    7.11 @@ -11572,8 +11573,7 @@
    7.12    // effect no longer needs to be mentioned, since r0 is not contained
    7.13    // in a reg_class.
    7.14  
    7.15 -  format %{ "LD      R12, addr of polling page\n\t"
    7.16 -            "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
    7.17 +  format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
    7.18    ins_encode( enc_poll(0x0, poll) );
    7.19    ins_pipe(pipe_class_default);
    7.20  %}

     8.1 --- a/src/cpu/ppc/vm/stubRoutines_ppc_64.cpp	Thu Feb 20 14:44:33 2014 +0100
     8.2 +++ b/src/cpu/ppc/vm/stubRoutines_ppc_64.cpp	Thu Mar 20 11:03:06 2014 +0100
     8.3 @@ -1,6 +1,6 @@
     8.4  /*
     8.5   * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
     8.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     8.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     8.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     8.9   *
    8.10   * This code is free software; you can redistribute it and/or modify it
    8.11 @@ -23,17 +23,6 @@
    8.12   *
    8.13   */
    8.14  
    8.15 -#include "precompiled.hpp"
    8.16 -#include "runtime/deoptimization.hpp"
    8.17 -#include "runtime/frame.inline.hpp"
    8.18 -#include "runtime/stubRoutines.hpp"
    8.19 -#ifdef TARGET_OS_FAMILY_aix
    8.20 -# include "thread_aix.inline.hpp"
    8.21 -#endif
    8.22 -#ifdef TARGET_OS_FAMILY_linux
    8.23 -# include "thread_linux.inline.hpp"
    8.24 -#endif
    8.25 -
    8.26  // Implementation of the platform-specific part of StubRoutines - for
    8.27  // a description of how to extend it, see the stubRoutines.hpp file.
    8.28  

     9.1 --- a/src/cpu/ppc/vm/vm_version_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
     9.2 +++ b/src/cpu/ppc/vm/vm_version_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
     9.3 @@ -1,6 +1,6 @@
     9.4  /*
     9.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     9.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
     9.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
     9.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     9.9   *
    9.10   * This code is free software; you can redistribute it and/or modify it
    9.11 @@ -402,6 +402,9 @@
    9.12    CodeBuffer cb("detect_cpu_features", code_size, 0);
    9.13    MacroAssembler* a = new MacroAssembler(&cb);
    9.14  
    9.15 +  // Must be set to true so we can generate the test code.
    9.16 +  _features = VM_Version::all_features_m;
    9.17 +
    9.18    // Emit code.
    9.19    void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
    9.20    uint32_t *code = (uint32_t *)a->pc();
    9.21 @@ -409,14 +412,15 @@
    9.22    // Keep R3_ARG1 unmodified, it contains &field (see below).
    9.23    // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
    9.24    a->fsqrt(F3, F4);                            // code[0] -> fsqrt_m
    9.25 -  a->isel(R7, R5, R6, 0);                      // code[1] -> isel_m
    9.26 -  a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[2] -> lxarx_m
    9.27 -  a->cmpb(R7, R5, R6);                         // code[3] -> bcmp
    9.28 -  //a->mftgpr(R7, F3);                         // code[4] -> mftgpr
    9.29 -  a->popcntb(R7, R5);                          // code[5] -> popcntb
    9.30 -  a->popcntw(R7, R5);                          // code[6] -> popcntw
    9.31 -  a->fcfids(F3, F4);                           // code[7] -> fcfids
    9.32 -  a->vand(VR0, VR0, VR0);                      // code[8] -> vand
    9.33 +  a->fsqrts(F3, F4);                           // code[1] -> fsqrts_m
    9.34 +  a->isel(R7, R5, R6, 0);                      // code[2] -> isel_m
    9.35 +  a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
    9.36 +  a->cmpb(R7, R5, R6);                         // code[4] -> bcmp
    9.37 +  //a->mftgpr(R7, F3);                         // code[5] -> mftgpr
    9.38 +  a->popcntb(R7, R5);                          // code[6] -> popcntb
    9.39 +  a->popcntw(R7, R5);                          // code[7] -> popcntw
    9.40 +  a->fcfids(F3, F4);                           // code[8] -> fcfids
    9.41 +  a->vand(VR0, VR0, VR0);                      // code[9] -> vand
    9.42    a->blr();
    9.43  
    9.44    // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
    9.45 @@ -426,6 +430,7 @@
    9.46  
    9.47    uint32_t *code_end = (uint32_t *)a->pc();
    9.48    a->flush();
    9.49 +  _features = VM_Version::unknown_m;
    9.50  
    9.51    // Print the detection code.
    9.52    if (PrintAssembly) {
    9.53 @@ -450,6 +455,7 @@
    9.54    // determine which instructions are legal.
    9.55    int feature_cntr = 0;
    9.56    if (code[feature_cntr++]) features |= fsqrt_m;
    9.57 +  if (code[feature_cntr++]) features |= fsqrts_m;
    9.58    if (code[feature_cntr++]) features |= isel_m;
    9.59    if (code[feature_cntr++]) features |= lxarxeh_m;
    9.60    if (code[feature_cntr++]) features |= cmpb_m;

    10.1 --- a/src/cpu/ppc/vm/vm_version_ppc.hpp	Thu Feb 20 14:44:33 2014 +0100
    10.2 +++ b/src/cpu/ppc/vm/vm_version_ppc.hpp	Thu Mar 20 11:03:06 2014 +0100
    10.3 @@ -1,6 +1,6 @@
    10.4  /*
    10.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    10.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    10.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    10.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    10.9   *
   10.10   * This code is free software; you can redistribute it and/or modify it
   10.11 @@ -33,6 +33,7 @@
   10.12  protected:
   10.13    enum Feature_Flag {
   10.14      fsqrt,
   10.15 +    fsqrts,
   10.16      isel,
   10.17      lxarxeh,
   10.18      cmpb,
   10.19 @@ -46,6 +47,7 @@
   10.20    enum Feature_Flag_Set {
   10.21      unknown_m             = 0,
   10.22      fsqrt_m               = (1 << fsqrt  ),
   10.23 +    fsqrts_m              = (1 << fsqrts ),
   10.24      isel_m                = (1 << isel   ),
   10.25      lxarxeh_m             = (1 << lxarxeh),
   10.26      cmpb_m                = (1 << cmpb   ),
   10.27 @@ -72,6 +74,7 @@
   10.28    static bool is_determine_features_test_running() { return _is_determine_features_test_running; }
   10.29    // CPU instruction support
   10.30    static bool has_fsqrt()   { return (_features & fsqrt_m) != 0; }
   10.31 +  static bool has_fsqrts()  { return (_features & fsqrts_m) != 0; }
   10.32    static bool has_isel()    { return (_features & isel_m) != 0; }
   10.33    static bool has_lxarxeh() { return (_features & lxarxeh_m) !=0; }
   10.34    static bool has_cmpb()    { return (_features & cmpb_m) != 0; }

    11.1 --- a/src/cpu/ppc/vm/vtableStubs_ppc_64.cpp	Thu Feb 20 14:44:33 2014 +0100
    11.2 +++ b/src/cpu/ppc/vm/vtableStubs_ppc_64.cpp	Thu Mar 20 11:03:06 2014 +0100
    11.3 @@ -1,6 +1,6 @@
    11.4  /*
    11.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    11.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    11.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    11.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    11.9   *
   11.10   * This code is free software; you can redistribute it and/or modify it
   11.11 @@ -79,7 +79,7 @@
   11.12    address npe_addr = __ pc(); // npe = null pointer exception
   11.13    __ load_klass_with_trap_null_check(rcvr_klass, R3);
   11.14  
   11.15 - // Set methodOop (in case of interpreted method), and destination address.
   11.16 + // Set method (in case of interpreted method), and destination address.
   11.17    int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
   11.18  
   11.19  #ifndef PRODUCT
   11.20 @@ -161,8 +161,6 @@
   11.21    address npe_addr = __ pc(); // npe = null pointer exception
   11.22    __ load_klass_with_trap_null_check(rcvr_klass, R3_ARG1);
   11.23  
   11.24 -  //__ ld(rcvr_klass, oopDesc::klass_offset_in_bytes(), R3_ARG1);
   11.25 -
   11.26    BLOCK_COMMENT("Load start of itable entries into itable_entry.");
   11.27    __ lwz(vtable_len, InstanceKlass::vtable_length_offset() * wordSize, rcvr_klass);
   11.28    __ slwi(vtable_len, vtable_len, exact_log2(vtableEntry::size() * wordSize));
   11.29 @@ -199,7 +197,7 @@
   11.30                                     itable_offset_search_inc;
   11.31    __ lwz(vtable_offset, vtable_offset_offset, itable_entry_addr);
   11.32  
   11.33 -  // Compute itableMethodEntry and get methodOop and entry point for compiler.
   11.34 +  // Compute itableMethodEntry and get method and entry point for compiler.
   11.35    const int method_offset = (itableMethodEntry::size() * wordSize * vtable_index) +
   11.36      itableMethodEntry::method_offset_in_bytes();
   11.37  
   11.38 @@ -211,7 +209,7 @@
   11.39      Label ok;
   11.40      __ cmpd(CCR0, R19_method, 0);
   11.41      __ bne(CCR0, ok);
   11.42 -    __ stop("methodOop is null", 103);
   11.43 +    __ stop("method is null", 103);
   11.44      __ bind(ok);
   11.45    }
   11.46  #endif

    12.1 --- a/src/os/aix/vm/mutex_aix.inline.hpp	Thu Feb 20 14:44:33 2014 +0100
    12.2 +++ b/src/os/aix/vm/mutex_aix.inline.hpp	Thu Mar 20 11:03:06 2014 +0100
    12.3 @@ -1,6 +1,6 @@
    12.4  /*
    12.5   * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
    12.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    12.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    12.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    12.9   *
   12.10   * This code is free software; you can redistribute it and/or modify it
   12.11 @@ -28,6 +28,6 @@
   12.12  
   12.13  #include "os_aix.inline.hpp"
   12.14  #include "runtime/interfaceSupport.hpp"
   12.15 -#include "thread_aix.inline.hpp"
   12.16 +#include "runtime/thread.inline.hpp"
   12.17  
   12.18  #endif // OS_AIX_VM_MUTEX_AIX_INLINE_HPP

    13.1 --- a/src/os/aix/vm/os_aix.cpp	Thu Feb 20 14:44:33 2014 +0100
    13.2 +++ b/src/os/aix/vm/os_aix.cpp	Thu Mar 20 11:03:06 2014 +0100
    13.3 @@ -1,6 +1,6 @@
    13.4  /*
    13.5   * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
    13.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    13.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    13.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    13.9   *
   13.10   * This code is free software; you can redistribute it and/or modify it
   13.11 @@ -61,10 +61,10 @@
   13.12  #include "runtime/statSampler.hpp"
   13.13  #include "runtime/stubRoutines.hpp"
   13.14  #include "runtime/threadCritical.hpp"
   13.15 +#include "runtime/thread.inline.hpp"
   13.16  #include "runtime/timer.hpp"
   13.17  #include "services/attachListener.hpp"
   13.18  #include "services/runtimeService.hpp"
   13.19 -#include "thread_aix.inline.hpp"
   13.20  #include "utilities/decoder.hpp"
   13.21  #include "utilities/defaultStream.hpp"
   13.22  #include "utilities/events.hpp"

    14.1 --- a/src/os/aix/vm/threadCritical_aix.cpp	Thu Feb 20 14:44:33 2014 +0100
    14.2 +++ b/src/os/aix/vm/threadCritical_aix.cpp	Thu Mar 20 11:03:06 2014 +0100
    14.3 @@ -1,6 +1,6 @@
    14.4  /*
    14.5   * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
    14.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    14.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    14.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    14.9   *
   14.10   * This code is free software; you can redistribute it and/or modify it
   14.11 @@ -25,7 +25,7 @@
   14.12  
   14.13  #include "precompiled.hpp"
   14.14  #include "runtime/threadCritical.hpp"
   14.15 -#include "thread_aix.inline.hpp"
   14.16 +#include "runtime/thread.inline.hpp"
   14.17  
   14.18  // put OS-includes here
   14.19  # include <pthread.h>

    15.1 --- a/src/os_cpu/aix_ppc/vm/os_aix_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
    15.2 +++ b/src/os_cpu/aix_ppc/vm/os_aix_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
    15.3 @@ -1,6 +1,6 @@
    15.4  /*
    15.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    15.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    15.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    15.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    15.9   *
   15.10   * This code is free software; you can redistribute it and/or modify it
   15.11 @@ -49,8 +49,8 @@
   15.12  #include "runtime/osThread.hpp"
   15.13  #include "runtime/sharedRuntime.hpp"
   15.14  #include "runtime/stubRoutines.hpp"
   15.15 +#include "runtime/thread.inline.hpp"
   15.16  #include "runtime/timer.hpp"
   15.17 -#include "thread_aix.inline.hpp"
   15.18  #include "utilities/events.hpp"
   15.19  #include "utilities/vmError.hpp"
   15.20  #ifdef COMPILER1

    16.1 --- a/src/os_cpu/aix_ppc/vm/threadLS_aix_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
    16.2 +++ b/src/os_cpu/aix_ppc/vm/threadLS_aix_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
    16.3 @@ -1,6 +1,6 @@
    16.4  /*
    16.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    16.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    16.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    16.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    16.9   *
   16.10   * This code is free software; you can redistribute it and/or modify it
   16.11 @@ -25,14 +25,14 @@
   16.12  
   16.13  #include "precompiled.hpp"
   16.14  #include "runtime/threadLocalStorage.hpp"
   16.15 -#include "thread_aix.inline.hpp"
   16.16 +#include "runtime/thread.hpp"
   16.17  
   16.18  void ThreadLocalStorage::generate_code_for_get_thread() {
   16.19 -    // nothing we can do here for user-level thread
   16.20 +  // Nothing we can do here for user-level thread.
   16.21  }
   16.22  
   16.23  void ThreadLocalStorage::pd_init() {
   16.24 -  // Nothing to do
   16.25 +  // Nothing to do.
   16.26  }
   16.27  
   16.28  void ThreadLocalStorage::pd_set_thread(Thread* thread) {

    17.1 --- a/src/os_cpu/aix_ppc/vm/thread_aix_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
    17.2 +++ b/src/os_cpu/aix_ppc/vm/thread_aix_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
    17.3 @@ -1,6 +1,6 @@
    17.4  /*
    17.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    17.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    17.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    17.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    17.9   *
   17.10   * This code is free software; you can redistribute it and/or modify it
   17.11 @@ -24,8 +24,8 @@
   17.12   */
   17.13  
   17.14  #include "precompiled.hpp"
   17.15 -#include "runtime/frame.inline.hpp"
   17.16 -#include "thread_aix.inline.hpp"
   17.17 +#include "runtime/frame.hpp"
   17.18 +#include "runtime/thread.hpp"
   17.19  
   17.20  // Forte Analyzer AsyncGetCallTrace profiling support is not implemented on Aix/PPC.
   17.21  bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext, bool isInJava) {

    18.1 --- a/src/os_cpu/linux_ppc/vm/thread_linux_ppc.cpp	Thu Feb 20 14:44:33 2014 +0100
    18.2 +++ b/src/os_cpu/linux_ppc/vm/thread_linux_ppc.cpp	Thu Mar 20 11:03:06 2014 +0100
    18.3 @@ -1,6 +1,6 @@
    18.4  /*
    18.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
    18.6 - * Copyright 2012, 2013 SAP AG. All rights reserved.
    18.7 + * Copyright 2012, 2014 SAP AG. All rights reserved.
    18.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    18.9   *
   18.10   * This code is free software; you can redistribute it and/or modify it
   18.11 @@ -24,8 +24,8 @@
   18.12   */
   18.13  
   18.14  #include "precompiled.hpp"
   18.15 -#include "runtime/frame.inline.hpp"
   18.16 -#include "thread_linux.inline.hpp"
   18.17 +#include "runtime/frame.hpp"
   18.18 +#include "runtime/thread.hpp"
   18.19  
   18.20  // Forte Analyzer AsyncGetCallTrace profiling support is not implemented on Linux/PPC.
   18.21  bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext, bool isInJava) {