Thu, 20 Mar 2014 11:03:06 +0100
8037915: PPC64/AIX: Several smaller fixes
Reviewed-by: kvn
1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 //
27 // PPC64 Architecture Description File
28 //
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
79 // PPC64 has 32 64-bit integer registers.
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
233 // Condition Codes Flag Registers
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
248 // Special registers of PPC64
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
267 // It's worth about 1% on SPEC geomean to get this right.
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
335 // scratch register
336 F0, F0_H,
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
398 //-------Architecture Description Register Classes-----------------------
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
560 reg_class r19_bits64_reg(R19_H, R19);
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
861 %}
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Returns true if Node n is followed by a MemBar node that
895 // will do an acquire. If so, this node must not do the acquire
896 // operation.
897 bool followed_by_acquire(const Node *n);
898 %}
900 source %{
902 // Optimize load-acquire.
903 //
904 // Check if acquire is unnecessary due to following operation that does
905 // acquire anyways.
906 // Walk the pattern:
907 //
908 // n: Load.acq
909 // |
910 // MemBarAcquire
911 // | |
912 // Proj(ctrl) Proj(mem)
913 // | |
914 // MemBarRelease/Volatile
915 //
916 bool followed_by_acquire(const Node *load) {
917 assert(load->is_Load(), "So far implemented only for loads.");
919 // Find MemBarAcquire.
920 const Node *mba = NULL;
921 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
922 const Node *out = load->fast_out(i);
923 if (out->Opcode() == Op_MemBarAcquire) {
924 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
925 mba = out;
926 break;
927 }
928 }
929 if (!mba) return false;
931 // Find following MemBar node.
932 //
933 // The following node must be reachable by control AND memory
934 // edge to assure no other operations are in between the two nodes.
935 //
936 // So first get the Proj node, mem_proj, to use it to iterate forward.
937 Node *mem_proj = NULL;
938 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
939 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
940 assert(mem_proj->is_Proj(), "only projections here");
941 ProjNode *proj = mem_proj->as_Proj();
942 if (proj->_con == TypeFunc::Memory &&
943 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
944 break;
945 }
946 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
948 // Search MemBar behind Proj. If there are other memory operations
949 // behind the Proj we lost.
950 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
951 Node *x = mem_proj->fast_out(j);
952 // Proj might have an edge to a store or load node which precedes the membar.
953 if (x->is_Mem()) return false;
955 // On PPC64 release and volatile are implemented by an instruction
956 // that also has acquire semantics. I.e. there is no need for an
957 // acquire before these.
958 int xop = x->Opcode();
959 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
960 // Make sure we're not missing Call/Phi/MergeMem by checking
961 // control edges. The control edge must directly lead back
962 // to the MemBarAcquire
963 Node *ctrl_proj = x->in(0);
964 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
965 return true;
966 }
967 }
968 }
970 return false;
971 }
973 #define __ _masm.
975 // Tertiary op of a LoadP or StoreP encoding.
976 #define REGP_OP true
978 // ****************************************************************************
980 // REQUIRED FUNCTIONALITY
982 // !!!!! Special hack to get all type of calls to specify the byte offset
983 // from the start of the call to the point where the return address
984 // will point.
986 // PPC port: Removed use of lazy constant construct.
988 int MachCallStaticJavaNode::ret_addr_offset() {
989 // It's only a single branch-and-link instruction.
990 return 4;
991 }
993 int MachCallDynamicJavaNode::ret_addr_offset() {
994 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
995 // postalloc expanded calls if we use inline caches and do not update method data.
996 if (UseInlineCaches)
997 return 4;
999 int vtable_index = this->_vtable_index;
1000 if (vtable_index < 0) {
1001 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1002 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1003 return 12;
1004 } else {
1005 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1006 return 24;
1007 }
1008 }
1010 int MachCallRuntimeNode::ret_addr_offset() {
1011 #if defined(ABI_ELFv2)
1012 return 28;
1013 #else
1014 return 40;
1015 #endif
1016 }
1018 //=============================================================================
1020 // condition code conversions
1022 static int cc_to_boint(int cc) {
1023 return Assembler::bcondCRbiIs0 | (cc & 8);
1024 }
1026 static int cc_to_inverse_boint(int cc) {
1027 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1028 }
1030 static int cc_to_biint(int cc, int flags_reg) {
1031 return (flags_reg << 2) | (cc & 3);
1032 }
1034 //=============================================================================
1036 // Compute padding required for nodes which need alignment. The padding
1037 // is the number of bytes (not instructions) which will be inserted before
1038 // the instruction. The padding must match the size of a NOP instruction.
1040 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1041 return (3*4-current_offset)&31;
1042 }
1044 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1045 return (2*4-current_offset)&31;
1046 }
1048 int string_indexOf_immNode::compute_padding(int current_offset) const {
1049 return (3*4-current_offset)&31;
1050 }
1052 int string_indexOfNode::compute_padding(int current_offset) const {
1053 return (1*4-current_offset)&31;
1054 }
1056 int string_compareNode::compute_padding(int current_offset) const {
1057 return (4*4-current_offset)&31;
1058 }
1060 int string_equals_immNode::compute_padding(int current_offset) const {
1061 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1062 return (2*4-current_offset)&31;
1063 }
1065 int string_equalsNode::compute_padding(int current_offset) const {
1066 return (7*4-current_offset)&31;
1067 }
1069 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1070 return (2*4-current_offset)&31;
1071 }
1073 //=============================================================================
1075 // Indicate if the safepoint node needs the polling page as an input.
1076 bool SafePointNode::needs_polling_address_input() {
1077 // The address is loaded from thread by a seperate node.
1078 return true;
1079 }
1081 //=============================================================================
1083 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1084 void emit_break(CodeBuffer &cbuf) {
1085 MacroAssembler _masm(&cbuf);
1086 __ illtrap();
1087 }
1089 #ifndef PRODUCT
1090 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1091 st->print("BREAKPOINT");
1092 }
1093 #endif
1095 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1096 emit_break(cbuf);
1097 }
1099 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1100 return MachNode::size(ra_);
1101 }
1103 //=============================================================================
1105 void emit_nop(CodeBuffer &cbuf) {
1106 MacroAssembler _masm(&cbuf);
1107 __ nop();
1108 }
1110 static inline void emit_long(CodeBuffer &cbuf, int value) {
1111 *((int*)(cbuf.insts_end())) = value;
1112 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1113 }
1115 //=============================================================================
1117 // Emit a trampoline stub for a call to a target which is too far away.
1118 //
1119 // code sequences:
1120 //
1121 // call-site:
1122 // branch-and-link to <destination> or <trampoline stub>
1123 //
1124 // Related trampoline stub for this call-site in the stub section:
1125 // load the call target from the constant pool
1126 // branch via CTR (LR/link still points to the call-site above)
1128 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1130 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1131 // Start the stub.
1132 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1133 if (stub == NULL) {
1134 Compile::current()->env()->record_out_of_memory_failure();
1135 return;
1136 }
1138 // For java_to_interp stubs we use R11_scratch1 as scratch register
1139 // and in call trampoline stubs we use R12_scratch2. This way we
1140 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1141 Register reg_scratch = R12_scratch2;
1143 // Create a trampoline stub relocation which relates this trampoline stub
1144 // with the call instruction at insts_call_instruction_offset in the
1145 // instructions code-section.
1146 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1147 const int stub_start_offset = __ offset();
1149 // Now, create the trampoline stub's code:
1150 // - load the TOC
1151 // - load the call target from the constant pool
1152 // - call
1153 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1154 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1155 __ mtctr(reg_scratch);
1156 __ bctr();
1158 const address stub_start_addr = __ addr_at(stub_start_offset);
1160 // FIXME: Assert that the trampoline stub can be identified and patched.
1162 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1163 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1164 "encoded offset into the constant pool must match");
1165 // Trampoline_stub_size should be good.
1166 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1167 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1169 // End the stub.
1170 __ end_a_stub();
1171 }
1173 // Size of trampoline stub, this doesn't need to be accurate but it must
1174 // be larger or equal to the real size of the stub.
1175 // Used for optimization in Compile::Shorten_branches.
1176 uint size_call_trampoline() {
1177 return trampoline_stub_size;
1178 }
1180 // Number of relocation entries needed by trampoline stub.
1181 // Used for optimization in Compile::Shorten_branches.
1182 uint reloc_call_trampoline() {
1183 return 5;
1184 }
1186 //=============================================================================
1188 // Emit an inline branch-and-link call and a related trampoline stub.
1189 //
1190 // code sequences:
1191 //
1192 // call-site:
1193 // branch-and-link to <destination> or <trampoline stub>
1194 //
1195 // Related trampoline stub for this call-site in the stub section:
1196 // load the call target from the constant pool
1197 // branch via CTR (LR/link still points to the call-site above)
1198 //
1200 typedef struct {
1201 int insts_call_instruction_offset;
1202 int ret_addr_offset;
1203 } EmitCallOffsets;
1205 // Emit a branch-and-link instruction that branches to a trampoline.
1206 // - Remember the offset of the branch-and-link instruction.
1207 // - Add a relocation at the branch-and-link instruction.
1208 // - Emit a branch-and-link.
1209 // - Remember the return pc offset.
1210 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1211 EmitCallOffsets offsets = { -1, -1 };
1212 const int start_offset = __ offset();
1213 offsets.insts_call_instruction_offset = __ offset();
1215 // No entry point given, use the current pc.
1216 if (entry_point == NULL) entry_point = __ pc();
1218 if (!Compile::current()->in_scratch_emit_size()) {
1219 // Put the entry point as a constant into the constant pool.
1220 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1221 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1223 // Emit the trampoline stub which will be related to the branch-and-link below.
1224 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1225 __ relocate(rtype);
1226 }
1228 // Note: At this point we do not have the address of the trampoline
1229 // stub, and the entry point might be too far away for bl, so __ pc()
1230 // serves as dummy and the bl will be patched later.
1231 __ bl((address) __ pc());
1233 offsets.ret_addr_offset = __ offset() - start_offset;
1235 return offsets;
1236 }
1238 //=============================================================================
1240 // Factory for creating loadConL* nodes for large/small constant pool.
1242 static inline jlong replicate_immF(float con) {
1243 // Replicate float con 2 times and pack into vector.
1244 int val = *((int*)&con);
1245 jlong lval = val;
1246 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1247 return lval;
1248 }
1250 //=============================================================================
1252 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1253 int Compile::ConstantTable::calculate_table_base_offset() const {
1254 return 0; // absolute addressing, no offset
1255 }
1257 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1258 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1259 Compile *C = ra_->C;
1261 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1262 MachNode *m1 = new (C) loadToc_hiNode();
1263 MachNode *m2 = new (C) loadToc_loNode();
1265 m1->add_req(NULL);
1266 m2->add_req(NULL, m1);
1267 m1->_opnds[0] = op_dst;
1268 m2->_opnds[0] = op_dst;
1269 m2->_opnds[1] = op_dst;
1270 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1271 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1272 nodes->push(m1);
1273 nodes->push(m2);
1274 }
1276 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1277 // Is postalloc expanded.
1278 ShouldNotReachHere();
1279 }
1281 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1282 return 0;
1283 }
1285 #ifndef PRODUCT
1286 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1287 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1288 }
1289 #endif
1291 //=============================================================================
1293 #ifndef PRODUCT
1294 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1295 Compile* C = ra_->C;
1296 const long framesize = C->frame_slots() << LogBytesPerInt;
1298 st->print("PROLOG\n\t");
1299 if (C->need_stack_bang(framesize)) {
1300 st->print("stack_overflow_check\n\t");
1301 }
1303 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1304 st->print("save return pc\n\t");
1305 st->print("push frame %d\n\t", -framesize);
1306 }
1307 }
1308 #endif
1310 // Macro used instead of the common __ to emulate the pipes of PPC.
1311 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1312 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1313 // still no scheduling of this code is possible, the micro scheduler is aware of the
1314 // code and can update its internal data. The following mechanism is used to achieve this:
1315 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1316 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1317 #if 0 // TODO: PPC port
1318 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1319 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1320 _masm.
1321 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1322 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1323 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1324 C->hb_scheduling()->_pdScheduling->advance_offset
1325 #else
1326 #define ___(op) if (UsePower6SchedulerPPC64) \
1327 Unimplemented(); \
1328 _masm.
1329 #define ___stop if (UsePower6SchedulerPPC64) \
1330 Unimplemented()
1331 #define ___advance if (UsePower6SchedulerPPC64) \
1332 Unimplemented()
1333 #endif
1335 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1336 Compile* C = ra_->C;
1337 MacroAssembler _masm(&cbuf);
1339 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1340 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1342 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1344 const Register return_pc = R20; // Must match return_addr() in frame section.
1345 const Register callers_sp = R21;
1346 const Register push_frame_temp = R22;
1347 const Register toc_temp = R23;
1348 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1350 if (method_is_frameless) {
1351 // Add nop at beginning of all frameless methods to prevent any
1352 // oop instructions from getting overwritten by make_not_entrant
1353 // (patching attempt would fail).
1354 ___(nop) nop();
1355 } else {
1356 // Get return pc.
1357 ___(mflr) mflr(return_pc);
1358 }
1360 // Calls to C2R adapters often do not accept exceptional returns.
1361 // We require that their callers must bang for them. But be
1362 // careful, because some VM calls (such as call site linkage) can
1363 // use several kilobytes of stack. But the stack safety zone should
1364 // account for that. See bugs 4446381, 4468289, 4497237.
1365 if (C->need_stack_bang(framesize) && UseStackBanging) {
1366 // Unfortunately we cannot use the function provided in
1367 // assembler.cpp as we have to emulate the pipes. So I had to
1368 // insert the code of generate_stack_overflow_check(), see
1369 // assembler.cpp for some illuminative comments.
1370 const int page_size = os::vm_page_size();
1371 int bang_end = StackShadowPages*page_size;
1373 // This is how far the previous frame's stack banging extended.
1374 const int bang_end_safe = bang_end;
1376 if (framesize > page_size) {
1377 bang_end += framesize;
1378 }
1380 int bang_offset = bang_end_safe;
1382 while (bang_offset <= bang_end) {
1383 // Need at least one stack bang at end of shadow zone.
1385 // Again I had to copy code, this time from assembler_ppc64.cpp,
1386 // bang_stack_with_offset - see there for comments.
1388 // Stack grows down, caller passes positive offset.
1389 assert(bang_offset > 0, "must bang with positive offset");
1391 long stdoffset = -bang_offset;
1393 if (Assembler::is_simm(stdoffset, 16)) {
1394 // Signed 16 bit offset, a simple std is ok.
1395 if (UseLoadInstructionsForStackBangingPPC64) {
1396 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1397 } else {
1398 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1399 }
1400 } else if (Assembler::is_simm(stdoffset, 31)) {
1401 // Use largeoffset calculations for addis & ld/std.
1402 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1403 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1405 Register tmp = R11;
1406 ___(addis) addis(tmp, R1_SP, hi);
1407 if (UseLoadInstructionsForStackBangingPPC64) {
1408 ___(ld) ld(R0, lo, tmp);
1409 } else {
1410 ___(std) std(R0, lo, tmp);
1411 }
1412 } else {
1413 ShouldNotReachHere();
1414 }
1416 bang_offset += page_size;
1417 }
1418 // R11 trashed
1419 } // C->need_stack_bang(framesize) && UseStackBanging
1421 unsigned int bytes = (unsigned int)framesize;
1422 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1423 ciMethod *currMethod = C -> method();
1425 // Optimized version for most common case.
1426 if (UsePower6SchedulerPPC64 &&
1427 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1428 !(false /* ConstantsALot TODO: PPC port*/)) {
1429 ___(or) mr(callers_sp, R1_SP);
1430 ___(std) std(return_pc, _abi(lr), R1_SP);
1431 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1432 return;
1433 }
1435 if (!method_is_frameless) {
1436 // Get callers sp.
1437 ___(or) mr(callers_sp, R1_SP);
1439 // Push method's frame, modifies SP.
1440 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1441 // The ABI is already accounted for in 'framesize' via the
1442 // 'out_preserve' area.
1443 Register tmp = push_frame_temp;
1444 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1445 if (Assembler::is_simm(-offset, 16)) {
1446 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1447 } else {
1448 long x = -offset;
1449 // Had to insert load_const(tmp, -offset).
1450 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1451 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1452 ___(rldicr) sldi(tmp, tmp, 32);
1453 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1454 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1456 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1457 }
1458 }
1459 #if 0 // TODO: PPC port
1460 // For testing large constant pools, emit a lot of constants to constant pool.
1461 // "Randomize" const_size.
1462 if (ConstantsALot) {
1463 const int num_consts = const_size();
1464 for (int i = 0; i < num_consts; i++) {
1465 __ long_constant(0xB0B5B00BBABE);
1466 }
1467 }
1468 #endif
1469 if (!method_is_frameless) {
1470 // Save return pc.
1471 ___(std) std(return_pc, _abi(lr), callers_sp);
1472 }
1473 }
1474 #undef ___
1475 #undef ___stop
1476 #undef ___advance
1478 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1479 // Variable size. determine dynamically.
1480 return MachNode::size(ra_);
1481 }
1483 int MachPrologNode::reloc() const {
1484 // Return number of relocatable values contained in this instruction.
1485 return 1; // 1 reloc entry for load_const(toc).
1486 }
1488 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1492 Compile* C = ra_->C;
1494 st->print("EPILOG\n\t");
1495 st->print("restore return pc\n\t");
1496 st->print("pop frame\n\t");
1498 if (do_polling() && C->is_method_compilation()) {
1499 st->print("touch polling page\n\t");
1500 }
1501 }
1502 #endif
1504 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1505 Compile* C = ra_->C;
1506 MacroAssembler _masm(&cbuf);
1508 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1509 assert(framesize >= 0, "negative frame-size?");
1511 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1512 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1513 const Register return_pc = R11;
1514 const Register polling_page = R12;
1516 if (!method_is_frameless) {
1517 // Restore return pc relative to callers' sp.
1518 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1519 }
1521 if (method_needs_polling) {
1522 if (LoadPollAddressFromThread) {
1523 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1524 Unimplemented();
1525 } else {
1526 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1527 }
1528 }
1530 if (!method_is_frameless) {
1531 // Move return pc to LR.
1532 __ mtlr(return_pc);
1533 // Pop frame (fixed frame-size).
1534 __ addi(R1_SP, R1_SP, (int)framesize);
1535 }
1537 if (method_needs_polling) {
1538 // We need to mark the code position where the load from the safepoint
1539 // polling page was emitted as relocInfo::poll_return_type here.
1540 __ relocate(relocInfo::poll_return_type);
1541 __ load_from_polling_page(polling_page);
1542 }
1543 }
1545 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1546 // Variable size. Determine dynamically.
1547 return MachNode::size(ra_);
1548 }
1550 int MachEpilogNode::reloc() const {
1551 // Return number of relocatable values contained in this instruction.
1552 return 1; // 1 for load_from_polling_page.
1553 }
1555 const Pipeline * MachEpilogNode::pipeline() const {
1556 return MachNode::pipeline_class();
1557 }
1559 // This method seems to be obsolete. It is declared in machnode.hpp
1560 // and defined in all *.ad files, but it is never called. Should we
1561 // get rid of it?
1562 int MachEpilogNode::safepoint_offset() const {
1563 assert(do_polling(), "no return for this epilog node");
1564 return 0;
1565 }
1567 #if 0 // TODO: PPC port
1568 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1569 MacroAssembler _masm(&cbuf);
1570 if (LoadPollAddressFromThread) {
1571 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1572 } else {
1573 _masm.nop();
1574 }
1575 }
1577 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1578 if (LoadPollAddressFromThread) {
1579 return 4;
1580 } else {
1581 return 4;
1582 }
1583 }
1585 #ifndef PRODUCT
1586 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1587 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1588 }
1589 #endif
1591 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1592 return RSCRATCH1_BITS64_REG_mask();
1593 }
1594 #endif // PPC port
1596 // =============================================================================
1598 // Figure out which register class each belongs in: rc_int, rc_float or
1599 // rc_stack.
1600 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1602 static enum RC rc_class(OptoReg::Name reg) {
1603 // Return the register class for the given register. The given register
1604 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1605 // enumeration in adGlobals_ppc64.hpp.
1607 if (reg == OptoReg::Bad) return rc_bad;
1609 // We have 64 integer register halves, starting at index 0.
1610 if (reg < 64) return rc_int;
1612 // We have 64 floating-point register halves, starting at index 64.
1613 if (reg < 64+64) return rc_float;
1615 // Between float regs & stack are the flags regs.
1616 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1618 return rc_stack;
1619 }
1621 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1622 bool do_print, Compile* C, outputStream *st) {
1624 assert(opcode == Assembler::LD_OPCODE ||
1625 opcode == Assembler::STD_OPCODE ||
1626 opcode == Assembler::LWZ_OPCODE ||
1627 opcode == Assembler::STW_OPCODE ||
1628 opcode == Assembler::LFD_OPCODE ||
1629 opcode == Assembler::STFD_OPCODE ||
1630 opcode == Assembler::LFS_OPCODE ||
1631 opcode == Assembler::STFS_OPCODE,
1632 "opcode not supported");
1634 if (cbuf) {
1635 int d =
1636 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1637 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1638 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1639 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1640 }
1641 #ifndef PRODUCT
1642 else if (do_print) {
1643 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1644 op_str,
1645 Matcher::regName[reg],
1646 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1647 }
1648 #endif
1649 return 4; // size
1650 }
1652 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1653 Compile* C = ra_->C;
1655 // Get registers to move.
1656 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1657 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1658 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1659 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1661 enum RC src_hi_rc = rc_class(src_hi);
1662 enum RC src_lo_rc = rc_class(src_lo);
1663 enum RC dst_hi_rc = rc_class(dst_hi);
1664 enum RC dst_lo_rc = rc_class(dst_lo);
1666 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1667 if (src_hi != OptoReg::Bad)
1668 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1669 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1670 "expected aligned-adjacent pairs");
1671 // Generate spill code!
1672 int size = 0;
1674 if (src_lo == dst_lo && src_hi == dst_hi)
1675 return size; // Self copy, no move.
1677 // --------------------------------------
1678 // Memory->Memory Spill. Use R0 to hold the value.
1679 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1680 int src_offset = ra_->reg2offset(src_lo);
1681 int dst_offset = ra_->reg2offset(dst_lo);
1682 if (src_hi != OptoReg::Bad) {
1683 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1684 "expected same type of move for high parts");
1685 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1686 if (!cbuf && !do_size) st->print("\n\t");
1687 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1688 } else {
1689 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1690 if (!cbuf && !do_size) st->print("\n\t");
1691 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1692 }
1693 return size;
1694 }
1696 // --------------------------------------
1697 // Check for float->int copy; requires a trip through memory.
1698 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1699 Unimplemented();
1700 }
1702 // --------------------------------------
1703 // Check for integer reg-reg copy.
1704 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1705 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1706 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1707 size = (Rsrc != Rdst) ? 4 : 0;
1709 if (cbuf) {
1710 MacroAssembler _masm(cbuf);
1711 if (size) {
1712 __ mr(Rdst, Rsrc);
1713 }
1714 }
1715 #ifndef PRODUCT
1716 else if (!do_size) {
1717 if (size) {
1718 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1719 } else {
1720 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1721 }
1722 }
1723 #endif
1724 return size;
1725 }
1727 // Check for integer store.
1728 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1729 int dst_offset = ra_->reg2offset(dst_lo);
1730 if (src_hi != OptoReg::Bad) {
1731 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1732 "expected same type of move for high parts");
1733 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1734 } else {
1735 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1736 }
1737 return size;
1738 }
1740 // Check for integer load.
1741 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1742 int src_offset = ra_->reg2offset(src_lo);
1743 if (src_hi != OptoReg::Bad) {
1744 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1745 "expected same type of move for high parts");
1746 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1747 } else {
1748 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1749 }
1750 return size;
1751 }
1753 // Check for float reg-reg copy.
1754 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1755 if (cbuf) {
1756 MacroAssembler _masm(cbuf);
1757 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1758 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1759 __ fmr(Rdst, Rsrc);
1760 }
1761 #ifndef PRODUCT
1762 else if (!do_size) {
1763 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1764 }
1765 #endif
1766 return 4;
1767 }
1769 // Check for float store.
1770 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1771 int dst_offset = ra_->reg2offset(dst_lo);
1772 if (src_hi != OptoReg::Bad) {
1773 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1774 "expected same type of move for high parts");
1775 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1776 } else {
1777 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1778 }
1779 return size;
1780 }
1782 // Check for float load.
1783 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1784 int src_offset = ra_->reg2offset(src_lo);
1785 if (src_hi != OptoReg::Bad) {
1786 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1787 "expected same type of move for high parts");
1788 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1789 } else {
1790 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1791 }
1792 return size;
1793 }
1795 // --------------------------------------------------------------------
1796 // Check for hi bits still needing moving. Only happens for misaligned
1797 // arguments to native calls.
1798 if (src_hi == dst_hi)
1799 return size; // Self copy; no move.
1801 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1802 ShouldNotReachHere(); // Unimplemented
1803 return 0;
1804 }
1806 #ifndef PRODUCT
1807 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1808 if (!ra_)
1809 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1810 else
1811 implementation(NULL, ra_, false, st);
1812 }
1813 #endif
1815 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1816 implementation(&cbuf, ra_, false, NULL);
1817 }
1819 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1820 return implementation(NULL, ra_, true, NULL);
1821 }
1823 #if 0 // TODO: PPC port
1824 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1825 #ifndef PRODUCT
1826 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1827 #endif
1828 assert(ra_->node_regs_max_index() != 0, "");
1830 // Get registers to move.
1831 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1832 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1833 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1834 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1836 enum RC src_lo_rc = rc_class(src_lo);
1837 enum RC dst_lo_rc = rc_class(dst_lo);
1839 if (src_lo == dst_lo && src_hi == dst_hi)
1840 return ppc64Opcode_none; // Self copy, no move.
1842 // --------------------------------------
1843 // Memory->Memory Spill. Use R0 to hold the value.
1844 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1845 return ppc64Opcode_compound;
1846 }
1848 // --------------------------------------
1849 // Check for float->int copy; requires a trip through memory.
1850 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1851 Unimplemented();
1852 }
1854 // --------------------------------------
1855 // Check for integer reg-reg copy.
1856 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1857 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1858 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1859 if (Rsrc == Rdst) {
1860 return ppc64Opcode_none;
1861 } else {
1862 return ppc64Opcode_or;
1863 }
1864 }
1866 // Check for integer store.
1867 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1868 if (src_hi != OptoReg::Bad) {
1869 return ppc64Opcode_std;
1870 } else {
1871 return ppc64Opcode_stw;
1872 }
1873 }
1875 // Check for integer load.
1876 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1877 if (src_hi != OptoReg::Bad) {
1878 return ppc64Opcode_ld;
1879 } else {
1880 return ppc64Opcode_lwz;
1881 }
1882 }
1884 // Check for float reg-reg copy.
1885 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1886 return ppc64Opcode_fmr;
1887 }
1889 // Check for float store.
1890 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1891 if (src_hi != OptoReg::Bad) {
1892 return ppc64Opcode_stfd;
1893 } else {
1894 return ppc64Opcode_stfs;
1895 }
1896 }
1898 // Check for float load.
1899 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1900 if (src_hi != OptoReg::Bad) {
1901 return ppc64Opcode_lfd;
1902 } else {
1903 return ppc64Opcode_lfs;
1904 }
1905 }
1907 // --------------------------------------------------------------------
1908 // Check for hi bits still needing moving. Only happens for misaligned
1909 // arguments to native calls.
1910 if (src_hi == dst_hi)
1911 return ppc64Opcode_none; // Self copy; no move.
1913 ShouldNotReachHere();
1914 return ppc64Opcode_undefined;
1915 }
1916 #endif // PPC port
1918 #ifndef PRODUCT
1919 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1920 st->print("NOP \t// %d nops to pad for loops.", _count);
1921 }
1922 #endif
1924 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1925 MacroAssembler _masm(&cbuf);
1926 // _count contains the number of nops needed for padding.
1927 for (int i = 0; i < _count; i++) {
1928 __ nop();
1929 }
1930 }
1932 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1933 return _count * 4;
1934 }
1936 #ifndef PRODUCT
1937 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1938 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1939 int reg = ra_->get_reg_first(this);
1940 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1941 }
1942 #endif
1944 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1945 MacroAssembler _masm(&cbuf);
1947 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1948 int reg = ra_->get_encode(this);
1950 if (Assembler::is_simm(offset, 16)) {
1951 __ addi(as_Register(reg), R1, offset);
1952 } else {
1953 ShouldNotReachHere();
1954 }
1955 }
1957 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1958 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1959 return 4;
1960 }
1962 #ifndef PRODUCT
1963 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1964 st->print_cr("---- MachUEPNode ----");
1965 st->print_cr("...");
1966 }
1967 #endif
1969 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1970 // This is the unverified entry point.
1971 MacroAssembler _masm(&cbuf);
1973 // Inline_cache contains a klass.
1974 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1975 Register receiver_klass = R0; // tmp
1977 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1978 assert(R11_scratch1 == R11, "need prologue scratch register");
1980 // Check for NULL argument if we don't have implicit null checks.
1981 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1982 if (TrapBasedNullChecks) {
1983 __ trap_null_check(R3_ARG1);
1984 } else {
1985 Label valid;
1986 __ cmpdi(CCR0, R3_ARG1, 0);
1987 __ bne_predict_taken(CCR0, valid);
1988 // We have a null argument, branch to ic_miss_stub.
1989 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1990 relocInfo::runtime_call_type);
1991 __ bind(valid);
1992 }
1993 }
1994 // Assume argument is not NULL, load klass from receiver.
1995 __ load_klass(receiver_klass, R3_ARG1);
1997 if (TrapBasedICMissChecks) {
1998 __ trap_ic_miss_check(receiver_klass, ic_klass);
1999 } else {
2000 Label valid;
2001 __ cmpd(CCR0, receiver_klass, ic_klass);
2002 __ beq_predict_taken(CCR0, valid);
2003 // We have an unexpected klass, branch to ic_miss_stub.
2004 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2005 relocInfo::runtime_call_type);
2006 __ bind(valid);
2007 }
2009 // Argument is valid and klass is as expected, continue.
2010 }
2012 #if 0 // TODO: PPC port
2013 // Optimize UEP code on z (save a load_const() call in main path).
2014 int MachUEPNode::ep_offset() {
2015 return 0;
2016 }
2017 #endif
2019 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2020 // Variable size. Determine dynamically.
2021 return MachNode::size(ra_);
2022 }
2024 //=============================================================================
2026 uint size_exception_handler() {
2027 // The exception_handler is a b64_patchable.
2028 return MacroAssembler::b64_patchable_size;
2029 }
2031 uint size_deopt_handler() {
2032 // The deopt_handler is a bl64_patchable.
2033 return MacroAssembler::bl64_patchable_size;
2034 }
2036 int emit_exception_handler(CodeBuffer &cbuf) {
2037 MacroAssembler _masm(&cbuf);
2039 address base = __ start_a_stub(size_exception_handler());
2040 if (base == NULL) return 0; // CodeBuffer::expand failed
2042 int offset = __ offset();
2043 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2044 relocInfo::runtime_call_type);
2045 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2046 __ end_a_stub();
2048 return offset;
2049 }
2051 // The deopt_handler is like the exception handler, but it calls to
2052 // the deoptimization blob instead of jumping to the exception blob.
2053 int emit_deopt_handler(CodeBuffer& cbuf) {
2054 MacroAssembler _masm(&cbuf);
2056 address base = __ start_a_stub(size_deopt_handler());
2057 if (base == NULL) return 0; // CodeBuffer::expand failed
2059 int offset = __ offset();
2060 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2061 relocInfo::runtime_call_type);
2062 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2063 __ end_a_stub();
2065 return offset;
2066 }
2068 //=============================================================================
2070 // Use a frame slots bias for frameless methods if accessing the stack.
2071 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2072 if (as_Register(reg_enc) == R1_SP) {
2073 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2074 }
2075 return 0;
2076 }
2078 const bool Matcher::match_rule_supported(int opcode) {
2079 if (!has_match_rule(opcode))
2080 return false;
2082 switch (opcode) {
2083 case Op_SqrtD:
2084 return VM_Version::has_fsqrt();
2085 case Op_CountLeadingZerosI:
2086 case Op_CountLeadingZerosL:
2087 case Op_CountTrailingZerosI:
2088 case Op_CountTrailingZerosL:
2089 if (!UseCountLeadingZerosInstructionsPPC64)
2090 return false;
2091 break;
2093 case Op_PopCountI:
2094 case Op_PopCountL:
2095 return (UsePopCountInstruction && VM_Version::has_popcntw());
2097 case Op_StrComp:
2098 return SpecialStringCompareTo;
2099 case Op_StrEquals:
2100 return SpecialStringEquals;
2101 case Op_StrIndexOf:
2102 return SpecialStringIndexOf;
2103 }
2105 return true; // Per default match rules are supported.
2106 }
2108 int Matcher::regnum_to_fpu_offset(int regnum) {
2109 // No user for this method?
2110 Unimplemented();
2111 return 999;
2112 }
2114 const bool Matcher::convL2FSupported(void) {
2115 // fcfids can do the conversion (>= Power7).
2116 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2117 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2118 }
2120 // Vector width in bytes.
2121 const int Matcher::vector_width_in_bytes(BasicType bt) {
2122 assert(MaxVectorSize == 8, "");
2123 return 8;
2124 }
2126 // Vector ideal reg.
2127 const int Matcher::vector_ideal_reg(int size) {
2128 assert(MaxVectorSize == 8 && size == 8, "");
2129 return Op_RegL;
2130 }
2132 const int Matcher::vector_shift_count_ideal_reg(int size) {
2133 fatal("vector shift is not supported");
2134 return Node::NotAMachineReg;
2135 }
2137 // Limits on vector size (number of elements) loaded into vector.
2138 const int Matcher::max_vector_size(const BasicType bt) {
2139 assert(is_java_primitive(bt), "only primitive type vectors");
2140 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2141 }
2143 const int Matcher::min_vector_size(const BasicType bt) {
2144 return max_vector_size(bt); // Same as max.
2145 }
2147 // PPC doesn't support misaligned vectors store/load.
2148 const bool Matcher::misaligned_vectors_ok() {
2149 return false;
2150 }
2152 // PPC AES support not yet implemented
2153 const bool Matcher::pass_original_key_for_aes() {
2154 return false;
2155 }
2157 // RETURNS: whether this branch offset is short enough that a short
2158 // branch can be used.
2159 //
2160 // If the platform does not provide any short branch variants, then
2161 // this method should return `false' for offset 0.
2162 //
2163 // `Compile::Fill_buffer' will decide on basis of this information
2164 // whether to do the pass `Compile::Shorten_branches' at all.
2165 //
2166 // And `Compile::Shorten_branches' will decide on basis of this
2167 // information whether to replace particular branch sites by short
2168 // ones.
2169 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2170 // Is the offset within the range of a ppc64 pc relative branch?
2171 bool b;
2173 const int safety_zone = 3 * BytesPerInstWord;
2174 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2175 29 - 16 + 1 + 2);
2176 return b;
2177 }
2179 const bool Matcher::isSimpleConstant64(jlong value) {
2180 // Probably always true, even if a temp register is required.
2181 return true;
2182 }
2183 /* TODO: PPC port
2184 // Make a new machine dependent decode node (with its operands).
2185 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2186 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2187 "This method is only implemented for unscaled cOops mode so far");
2188 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2189 decode->set_opnd_array(0, new (C) iRegPdstOper());
2190 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2191 return decode;
2192 }
2193 */
2194 // Threshold size for cleararray.
2195 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2197 // false => size gets scaled to BytesPerLong, ok.
2198 const bool Matcher::init_array_count_is_in_bytes = false;
2200 // Use conditional move (CMOVL) on Power7.
2201 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2203 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2204 // fsel doesn't accept a condition register as input, so this would be slightly different.
2205 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2207 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2208 const bool Matcher::require_postalloc_expand = true;
2210 // Should the Matcher clone shifts on addressing modes, expecting them to
2211 // be subsumed into complex addressing expressions or compute them into
2212 // registers? True for Intel but false for most RISCs.
2213 const bool Matcher::clone_shift_expressions = false;
2215 // Do we need to mask the count passed to shift instructions or does
2216 // the cpu only look at the lower 5/6 bits anyway?
2217 // Off, as masks are generated in expand rules where required.
2218 // Constant shift counts are handled in Ideal phase.
2219 const bool Matcher::need_masked_shift_count = false;
2221 // This affects two different things:
2222 // - how Decode nodes are matched
2223 // - how ImplicitNullCheck opportunities are recognized
2224 // If true, the matcher will try to remove all Decodes and match them
2225 // (as operands) into nodes. NullChecks are not prepared to deal with
2226 // Decodes by final_graph_reshaping().
2227 // If false, final_graph_reshaping() forces the decode behind the Cmp
2228 // for a NullCheck. The matcher matches the Decode node into a register.
2229 // Implicit_null_check optimization moves the Decode along with the
2230 // memory operation back up before the NullCheck.
2231 bool Matcher::narrow_oop_use_complex_address() {
2232 // TODO: PPC port if (MatchDecodeNodes) return true;
2233 return false;
2234 }
2236 bool Matcher::narrow_klass_use_complex_address() {
2237 NOT_LP64(ShouldNotCallThis());
2238 assert(UseCompressedClassPointers, "only for compressed klass code");
2239 // TODO: PPC port if (MatchDecodeNodes) return true;
2240 return false;
2241 }
2243 // Is it better to copy float constants, or load them directly from memory?
2244 // Intel can load a float constant from a direct address, requiring no
2245 // extra registers. Most RISCs will have to materialize an address into a
2246 // register first, so they would do better to copy the constant from stack.
2247 const bool Matcher::rematerialize_float_constants = false;
2249 // If CPU can load and store mis-aligned doubles directly then no fixup is
2250 // needed. Else we split the double into 2 integer pieces and move it
2251 // piece-by-piece. Only happens when passing doubles into C code as the
2252 // Java calling convention forces doubles to be aligned.
2253 const bool Matcher::misaligned_doubles_ok = true;
2255 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2256 Unimplemented();
2257 }
2259 // Advertise here if the CPU requires explicit rounding operations
2260 // to implement the UseStrictFP mode.
2261 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2263 // Do floats take an entire double register or just half?
2264 //
2265 // A float occupies a ppc64 double register. For the allocator, a
2266 // ppc64 double register appears as a pair of float registers.
2267 bool Matcher::float_in_double() { return true; }
2269 // Do ints take an entire long register or just half?
2270 // The relevant question is how the int is callee-saved:
2271 // the whole long is written but de-opt'ing will have to extract
2272 // the relevant 32 bits.
2273 const bool Matcher::int_in_long = true;
2275 // Constants for c2c and c calling conventions.
2277 const MachRegisterNumbers iarg_reg[8] = {
2278 R3_num, R4_num, R5_num, R6_num,
2279 R7_num, R8_num, R9_num, R10_num
2280 };
2282 const MachRegisterNumbers farg_reg[13] = {
2283 F1_num, F2_num, F3_num, F4_num,
2284 F5_num, F6_num, F7_num, F8_num,
2285 F9_num, F10_num, F11_num, F12_num,
2286 F13_num
2287 };
2289 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2291 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2293 // Return whether or not this register is ever used as an argument. This
2294 // function is used on startup to build the trampoline stubs in generateOptoStub.
2295 // Registers not mentioned will be killed by the VM call in the trampoline, and
2296 // arguments in those registers not be available to the callee.
2297 bool Matcher::can_be_java_arg(int reg) {
2298 // We return true for all registers contained in iarg_reg[] and
2299 // farg_reg[] and their virtual halves.
2300 // We must include the virtual halves in order to get STDs and LDs
2301 // instead of STWs and LWs in the trampoline stubs.
2303 if ( reg == R3_num || reg == R3_H_num
2304 || reg == R4_num || reg == R4_H_num
2305 || reg == R5_num || reg == R5_H_num
2306 || reg == R6_num || reg == R6_H_num
2307 || reg == R7_num || reg == R7_H_num
2308 || reg == R8_num || reg == R8_H_num
2309 || reg == R9_num || reg == R9_H_num
2310 || reg == R10_num || reg == R10_H_num)
2311 return true;
2313 if ( reg == F1_num || reg == F1_H_num
2314 || reg == F2_num || reg == F2_H_num
2315 || reg == F3_num || reg == F3_H_num
2316 || reg == F4_num || reg == F4_H_num
2317 || reg == F5_num || reg == F5_H_num
2318 || reg == F6_num || reg == F6_H_num
2319 || reg == F7_num || reg == F7_H_num
2320 || reg == F8_num || reg == F8_H_num
2321 || reg == F9_num || reg == F9_H_num
2322 || reg == F10_num || reg == F10_H_num
2323 || reg == F11_num || reg == F11_H_num
2324 || reg == F12_num || reg == F12_H_num
2325 || reg == F13_num || reg == F13_H_num)
2326 return true;
2328 return false;
2329 }
2331 bool Matcher::is_spillable_arg(int reg) {
2332 return can_be_java_arg(reg);
2333 }
2335 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2336 return false;
2337 }
2339 // Register for DIVI projection of divmodI.
2340 RegMask Matcher::divI_proj_mask() {
2341 ShouldNotReachHere();
2342 return RegMask();
2343 }
2345 // Register for MODI projection of divmodI.
2346 RegMask Matcher::modI_proj_mask() {
2347 ShouldNotReachHere();
2348 return RegMask();
2349 }
2351 // Register for DIVL projection of divmodL.
2352 RegMask Matcher::divL_proj_mask() {
2353 ShouldNotReachHere();
2354 return RegMask();
2355 }
2357 // Register for MODL projection of divmodL.
2358 RegMask Matcher::modL_proj_mask() {
2359 ShouldNotReachHere();
2360 return RegMask();
2361 }
2363 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2364 return RegMask();
2365 }
2367 const RegMask Matcher::mathExactI_result_proj_mask() {
2368 return RARG4_BITS64_REG_mask();
2369 }
2371 const RegMask Matcher::mathExactL_result_proj_mask() {
2372 return RARG4_BITS64_REG_mask();
2373 }
2375 const RegMask Matcher::mathExactI_flags_proj_mask() {
2376 return INT_FLAGS_mask();
2377 }
2379 %}
2381 //----------ENCODING BLOCK-----------------------------------------------------
2382 // This block specifies the encoding classes used by the compiler to output
2383 // byte streams. Encoding classes are parameterized macros used by
2384 // Machine Instruction Nodes in order to generate the bit encoding of the
2385 // instruction. Operands specify their base encoding interface with the
2386 // interface keyword. There are currently supported four interfaces,
2387 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2388 // operand to generate a function which returns its register number when
2389 // queried. CONST_INTER causes an operand to generate a function which
2390 // returns the value of the constant when queried. MEMORY_INTER causes an
2391 // operand to generate four functions which return the Base Register, the
2392 // Index Register, the Scale Value, and the Offset Value of the operand when
2393 // queried. COND_INTER causes an operand to generate six functions which
2394 // return the encoding code (ie - encoding bits for the instruction)
2395 // associated with each basic boolean condition for a conditional instruction.
2396 //
2397 // Instructions specify two basic values for encoding. Again, a function
2398 // is available to check if the constant displacement is an oop. They use the
2399 // ins_encode keyword to specify their encoding classes (which must be
2400 // a sequence of enc_class names, and their parameters, specified in
2401 // the encoding block), and they use the
2402 // opcode keyword to specify, in order, their primary, secondary, and
2403 // tertiary opcode. Only the opcode sections which a particular instruction
2404 // needs for encoding need to be specified.
2405 encode %{
2406 enc_class enc_unimplemented %{
2407 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2408 MacroAssembler _masm(&cbuf);
2409 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2410 %}
2412 enc_class enc_untested %{
2413 #ifdef ASSERT
2414 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2415 MacroAssembler _masm(&cbuf);
2416 __ untested("Untested mach node encoding in AD file.");
2417 #else
2418 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2419 #endif
2420 %}
2422 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2423 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2424 MacroAssembler _masm(&cbuf);
2425 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2426 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2427 %}
2429 // Load acquire.
2430 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2431 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2432 MacroAssembler _masm(&cbuf);
2433 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2434 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2435 __ twi_0($dst$$Register);
2436 __ isync();
2437 %}
2439 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2440 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2442 MacroAssembler _masm(&cbuf);
2443 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2444 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2445 %}
2447 // Load acquire.
2448 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2449 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2451 MacroAssembler _masm(&cbuf);
2452 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2453 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2454 __ twi_0($dst$$Register);
2455 __ isync();
2456 %}
2458 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2459 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2461 MacroAssembler _masm(&cbuf);
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2464 %}
2466 // Load acquire.
2467 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2468 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2470 MacroAssembler _masm(&cbuf);
2471 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2472 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2473 __ twi_0($dst$$Register);
2474 __ isync();
2475 %}
2477 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2478 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2479 MacroAssembler _masm(&cbuf);
2480 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2481 // Operand 'ds' requires 4-alignment.
2482 assert((Idisp & 0x3) == 0, "unaligned offset");
2483 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2484 %}
2486 // Load acquire.
2487 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2488 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2489 MacroAssembler _masm(&cbuf);
2490 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2491 // Operand 'ds' requires 4-alignment.
2492 assert((Idisp & 0x3) == 0, "unaligned offset");
2493 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2494 __ twi_0($dst$$Register);
2495 __ isync();
2496 %}
2498 enc_class enc_lfd(RegF dst, memory mem) %{
2499 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2500 MacroAssembler _masm(&cbuf);
2501 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2502 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2503 %}
2505 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2506 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2508 MacroAssembler _masm(&cbuf);
2509 int toc_offset = 0;
2511 if (!ra_->C->in_scratch_emit_size()) {
2512 address const_toc_addr;
2513 // Create a non-oop constant, no relocation needed.
2514 // If it is an IC, it has a virtual_call_Relocation.
2515 const_toc_addr = __ long_constant((jlong)$src$$constant);
2517 // Get the constant's TOC offset.
2518 toc_offset = __ offset_to_method_toc(const_toc_addr);
2520 // Keep the current instruction offset in mind.
2521 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2522 }
2524 __ ld($dst$$Register, toc_offset, $toc$$Register);
2525 %}
2527 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2528 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2530 MacroAssembler _masm(&cbuf);
2532 if (!ra_->C->in_scratch_emit_size()) {
2533 address const_toc_addr;
2534 // Create a non-oop constant, no relocation needed.
2535 // If it is an IC, it has a virtual_call_Relocation.
2536 const_toc_addr = __ long_constant((jlong)$src$$constant);
2538 // Get the constant's TOC offset.
2539 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2540 // Store the toc offset of the constant.
2541 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2543 // Also keep the current instruction offset in mind.
2544 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2545 }
2547 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2548 %}
2550 %} // encode
2552 source %{
2554 typedef struct {
2555 loadConL_hiNode *_large_hi;
2556 loadConL_loNode *_large_lo;
2557 loadConLNode *_small;
2558 MachNode *_last;
2559 } loadConLNodesTuple;
2561 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2562 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2563 loadConLNodesTuple nodes;
2565 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2566 if (large_constant_pool) {
2567 // Create new nodes.
2568 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2569 loadConL_loNode *m2 = new (C) loadConL_loNode();
2571 // inputs for new nodes
2572 m1->add_req(NULL, toc);
2573 m2->add_req(NULL, m1);
2575 // operands for new nodes
2576 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2577 m1->_opnds[1] = immSrc; // src
2578 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2579 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2580 m2->_opnds[1] = immSrc; // src
2581 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2583 // Initialize ins_attrib TOC fields.
2584 m1->_const_toc_offset = -1;
2585 m2->_const_toc_offset_hi_node = m1;
2587 // Initialize ins_attrib instruction offset.
2588 m1->_cbuf_insts_offset = -1;
2590 // register allocation for new nodes
2591 ra_->set_pair(m1->_idx, reg_second, reg_first);
2592 ra_->set_pair(m2->_idx, reg_second, reg_first);
2594 // Create result.
2595 nodes._large_hi = m1;
2596 nodes._large_lo = m2;
2597 nodes._small = NULL;
2598 nodes._last = nodes._large_lo;
2599 assert(m2->bottom_type()->isa_long(), "must be long");
2600 } else {
2601 loadConLNode *m2 = new (C) loadConLNode();
2603 // inputs for new nodes
2604 m2->add_req(NULL, toc);
2606 // operands for new nodes
2607 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2608 m2->_opnds[1] = immSrc; // src
2609 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2611 // Initialize ins_attrib instruction offset.
2612 m2->_cbuf_insts_offset = -1;
2614 // register allocation for new nodes
2615 ra_->set_pair(m2->_idx, reg_second, reg_first);
2617 // Create result.
2618 nodes._large_hi = NULL;
2619 nodes._large_lo = NULL;
2620 nodes._small = m2;
2621 nodes._last = nodes._small;
2622 assert(m2->bottom_type()->isa_long(), "must be long");
2623 }
2625 return nodes;
2626 }
2628 %} // source
2630 encode %{
2631 // Postalloc expand emitter for loading a long constant from the method's TOC.
2632 // Enc_class needed as consttanttablebase is not supported by postalloc
2633 // expand.
2634 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2635 // Create new nodes.
2636 loadConLNodesTuple loadConLNodes =
2637 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2638 ra_->get_reg_second(this), ra_->get_reg_first(this));
2640 // Push new nodes.
2641 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2642 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2644 // some asserts
2645 assert(nodes->length() >= 1, "must have created at least 1 node");
2646 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2647 %}
2649 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2650 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2652 MacroAssembler _masm(&cbuf);
2653 int toc_offset = 0;
2655 if (!ra_->C->in_scratch_emit_size()) {
2656 intptr_t val = $src$$constant;
2657 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2658 address const_toc_addr;
2659 if (constant_reloc == relocInfo::oop_type) {
2660 // Create an oop constant and a corresponding relocation.
2661 AddressLiteral a = __ allocate_oop_address((jobject)val);
2662 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2663 __ relocate(a.rspec());
2664 } else if (constant_reloc == relocInfo::metadata_type) {
2665 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2666 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2667 __ relocate(a.rspec());
2668 } else {
2669 // Create a non-oop constant, no relocation needed.
2670 const_toc_addr = __ long_constant((jlong)$src$$constant);
2671 }
2673 // Get the constant's TOC offset.
2674 toc_offset = __ offset_to_method_toc(const_toc_addr);
2675 }
2677 __ ld($dst$$Register, toc_offset, $toc$$Register);
2678 %}
2680 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2681 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2683 MacroAssembler _masm(&cbuf);
2684 if (!ra_->C->in_scratch_emit_size()) {
2685 intptr_t val = $src$$constant;
2686 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2687 address const_toc_addr;
2688 if (constant_reloc == relocInfo::oop_type) {
2689 // Create an oop constant and a corresponding relocation.
2690 AddressLiteral a = __ allocate_oop_address((jobject)val);
2691 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2692 __ relocate(a.rspec());
2693 } else if (constant_reloc == relocInfo::metadata_type) {
2694 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2695 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2696 __ relocate(a.rspec());
2697 } else { // non-oop pointers, e.g. card mark base, heap top
2698 // Create a non-oop constant, no relocation needed.
2699 const_toc_addr = __ long_constant((jlong)$src$$constant);
2700 }
2702 // Get the constant's TOC offset.
2703 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2704 // Store the toc offset of the constant.
2705 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2706 }
2708 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2709 %}
2711 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2712 // Enc_class needed as consttanttablebase is not supported by postalloc
2713 // expand.
2714 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2715 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2716 if (large_constant_pool) {
2717 // Create new nodes.
2718 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2719 loadConP_loNode *m2 = new (C) loadConP_loNode();
2721 // inputs for new nodes
2722 m1->add_req(NULL, n_toc);
2723 m2->add_req(NULL, m1);
2725 // operands for new nodes
2726 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2727 m1->_opnds[1] = op_src; // src
2728 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2729 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2730 m2->_opnds[1] = op_src; // src
2731 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2733 // Initialize ins_attrib TOC fields.
2734 m1->_const_toc_offset = -1;
2735 m2->_const_toc_offset_hi_node = m1;
2737 // Register allocation for new nodes.
2738 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2739 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2741 nodes->push(m1);
2742 nodes->push(m2);
2743 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2744 } else {
2745 loadConPNode *m2 = new (C) loadConPNode();
2747 // inputs for new nodes
2748 m2->add_req(NULL, n_toc);
2750 // operands for new nodes
2751 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2752 m2->_opnds[1] = op_src; // src
2753 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2755 // Register allocation for new nodes.
2756 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2758 nodes->push(m2);
2759 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2760 }
2761 %}
2763 // Enc_class needed as consttanttablebase is not supported by postalloc
2764 // expand.
2765 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2766 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2768 MachNode *m2;
2769 if (large_constant_pool) {
2770 m2 = new (C) loadConFCompNode();
2771 } else {
2772 m2 = new (C) loadConFNode();
2773 }
2774 // inputs for new nodes
2775 m2->add_req(NULL, n_toc);
2777 // operands for new nodes
2778 m2->_opnds[0] = op_dst;
2779 m2->_opnds[1] = op_src;
2780 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2782 // register allocation for new nodes
2783 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2784 nodes->push(m2);
2785 %}
2787 // Enc_class needed as consttanttablebase is not supported by postalloc
2788 // expand.
2789 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2790 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2792 MachNode *m2;
2793 if (large_constant_pool) {
2794 m2 = new (C) loadConDCompNode();
2795 } else {
2796 m2 = new (C) loadConDNode();
2797 }
2798 // inputs for new nodes
2799 m2->add_req(NULL, n_toc);
2801 // operands for new nodes
2802 m2->_opnds[0] = op_dst;
2803 m2->_opnds[1] = op_src;
2804 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2806 // register allocation for new nodes
2807 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2808 nodes->push(m2);
2809 %}
2811 enc_class enc_stw(iRegIsrc src, memory mem) %{
2812 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2813 MacroAssembler _masm(&cbuf);
2814 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2815 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2816 %}
2818 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2819 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2820 MacroAssembler _masm(&cbuf);
2821 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2822 // Operand 'ds' requires 4-alignment.
2823 assert((Idisp & 0x3) == 0, "unaligned offset");
2824 __ std($src$$Register, Idisp, $mem$$base$$Register);
2825 %}
2827 enc_class enc_stfs(RegF src, memory mem) %{
2828 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2829 MacroAssembler _masm(&cbuf);
2830 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2831 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2832 %}
2834 enc_class enc_stfd(RegF src, memory mem) %{
2835 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2836 MacroAssembler _masm(&cbuf);
2837 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2838 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2839 %}
2841 // Use release_store for card-marking to ensure that previous
2842 // oop-stores are visible before the card-mark change.
2843 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2844 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2845 // FIXME: Implement this as a cmove and use a fixed condition code
2846 // register which is written on every transition to compiled code,
2847 // e.g. in call-stub and when returning from runtime stubs.
2848 //
2849 // Proposed code sequence for the cmove implementation:
2850 //
2851 // Label skip_release;
2852 // __ beq(CCRfixed, skip_release);
2853 // __ release();
2854 // __ bind(skip_release);
2855 // __ stb(card mark);
2857 MacroAssembler _masm(&cbuf);
2858 Label skip_storestore;
2860 #if 0 // TODO: PPC port
2861 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2862 // StoreStore barrier conditionally.
2863 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2864 __ cmpwi(CCR0, R0, 0);
2865 __ beq_predict_taken(CCR0, skip_storestore);
2866 #endif
2867 __ li(R0, 0);
2868 __ membar(Assembler::StoreStore);
2869 #if 0 // TODO: PPC port
2870 __ bind(skip_storestore);
2871 #endif
2873 // Do the store.
2874 if ($mem$$index == 0) {
2875 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2876 } else {
2877 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2878 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2879 }
2880 %}
2882 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2884 if (VM_Version::has_isel()) {
2885 // use isel instruction with Power 7
2886 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2887 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2888 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2889 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2891 n_compare->add_req(n_region, n_src);
2892 n_compare->_opnds[0] = op_crx;
2893 n_compare->_opnds[1] = op_src;
2894 n_compare->_opnds[2] = new (C) immL16Oper(0);
2896 n_sub_base->add_req(n_region, n_src);
2897 n_sub_base->_opnds[0] = op_dst;
2898 n_sub_base->_opnds[1] = op_src;
2899 n_sub_base->_bottom_type = _bottom_type;
2901 n_shift->add_req(n_region, n_sub_base);
2902 n_shift->_opnds[0] = op_dst;
2903 n_shift->_opnds[1] = op_dst;
2904 n_shift->_bottom_type = _bottom_type;
2906 n_cond_set->add_req(n_region, n_compare, n_shift);
2907 n_cond_set->_opnds[0] = op_dst;
2908 n_cond_set->_opnds[1] = op_crx;
2909 n_cond_set->_opnds[2] = op_dst;
2910 n_cond_set->_bottom_type = _bottom_type;
2912 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2913 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2914 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2915 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2917 nodes->push(n_compare);
2918 nodes->push(n_sub_base);
2919 nodes->push(n_shift);
2920 nodes->push(n_cond_set);
2922 } else {
2923 // before Power 7
2924 moveRegNode *n_move = new (C) moveRegNode();
2925 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2926 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2927 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2929 n_move->add_req(n_region, n_src);
2930 n_move->_opnds[0] = op_dst;
2931 n_move->_opnds[1] = op_src;
2932 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2934 n_compare->add_req(n_region, n_src);
2935 n_compare->add_prec(n_move);
2937 n_compare->_opnds[0] = op_crx;
2938 n_compare->_opnds[1] = op_src;
2939 n_compare->_opnds[2] = new (C) immL16Oper(0);
2941 n_sub_base->add_req(n_region, n_compare, n_src);
2942 n_sub_base->_opnds[0] = op_dst;
2943 n_sub_base->_opnds[1] = op_crx;
2944 n_sub_base->_opnds[2] = op_src;
2945 n_sub_base->_bottom_type = _bottom_type;
2947 n_shift->add_req(n_region, n_sub_base);
2948 n_shift->_opnds[0] = op_dst;
2949 n_shift->_opnds[1] = op_dst;
2950 n_shift->_bottom_type = _bottom_type;
2952 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2953 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2954 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2955 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2957 nodes->push(n_move);
2958 nodes->push(n_compare);
2959 nodes->push(n_sub_base);
2960 nodes->push(n_shift);
2961 }
2963 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2964 %}
2966 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2968 encodeP_subNode *n1 = new (C) encodeP_subNode();
2969 n1->add_req(n_region, n_src);
2970 n1->_opnds[0] = op_dst;
2971 n1->_opnds[1] = op_src;
2972 n1->_bottom_type = _bottom_type;
2974 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
2975 n2->add_req(n_region, n1);
2976 n2->_opnds[0] = op_dst;
2977 n2->_opnds[1] = op_dst;
2978 n2->_bottom_type = _bottom_type;
2979 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2980 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2982 nodes->push(n1);
2983 nodes->push(n2);
2984 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2985 %}
2987 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2988 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
2989 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
2991 n_compare->add_req(n_region, n_src);
2992 n_compare->_opnds[0] = op_crx;
2993 n_compare->_opnds[1] = op_src;
2994 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
2996 n_shift->add_req(n_region, n_src);
2997 n_shift->_opnds[0] = op_dst;
2998 n_shift->_opnds[1] = op_src;
2999 n_shift->_bottom_type = _bottom_type;
3001 if (VM_Version::has_isel()) {
3002 // use isel instruction with Power 7
3004 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3005 n_add_base->add_req(n_region, n_shift);
3006 n_add_base->_opnds[0] = op_dst;
3007 n_add_base->_opnds[1] = op_dst;
3008 n_add_base->_bottom_type = _bottom_type;
3010 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3011 n_cond_set->add_req(n_region, n_compare, n_add_base);
3012 n_cond_set->_opnds[0] = op_dst;
3013 n_cond_set->_opnds[1] = op_crx;
3014 n_cond_set->_opnds[2] = op_dst;
3015 n_cond_set->_bottom_type = _bottom_type;
3017 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3018 ra_->set_oop(n_cond_set, true);
3020 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3021 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3022 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3023 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3025 nodes->push(n_compare);
3026 nodes->push(n_shift);
3027 nodes->push(n_add_base);
3028 nodes->push(n_cond_set);
3030 } else {
3031 // before Power 7
3032 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3034 n_add_base->add_req(n_region, n_compare, n_shift);
3035 n_add_base->_opnds[0] = op_dst;
3036 n_add_base->_opnds[1] = op_crx;
3037 n_add_base->_opnds[2] = op_dst;
3038 n_add_base->_bottom_type = _bottom_type;
3040 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3041 ra_->set_oop(n_add_base, true);
3043 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3044 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3045 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3047 nodes->push(n_compare);
3048 nodes->push(n_shift);
3049 nodes->push(n_add_base);
3050 }
3051 %}
3053 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3054 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3055 n1->add_req(n_region, n_src);
3056 n1->_opnds[0] = op_dst;
3057 n1->_opnds[1] = op_src;
3058 n1->_bottom_type = _bottom_type;
3060 decodeN_addNode *n2 = new (C) decodeN_addNode();
3061 n2->add_req(n_region, n1);
3062 n2->_opnds[0] = op_dst;
3063 n2->_opnds[1] = op_dst;
3064 n2->_bottom_type = _bottom_type;
3065 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3066 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3068 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3069 ra_->set_oop(n2, true);
3071 nodes->push(n1);
3072 nodes->push(n2);
3073 %}
3075 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3076 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3078 MacroAssembler _masm(&cbuf);
3079 int cc = $cmp$$cmpcode;
3080 int flags_reg = $crx$$reg;
3081 Label done;
3082 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3083 // Branch if not (cmp crx).
3084 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3085 __ mr($dst$$Register, $src$$Register);
3086 // TODO PPC port __ endgroup_if_needed(_size == 12);
3087 __ bind(done);
3088 %}
3090 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3091 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3093 MacroAssembler _masm(&cbuf);
3094 Label done;
3095 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3096 // Branch if not (cmp crx).
3097 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3098 __ li($dst$$Register, $src$$constant);
3099 // TODO PPC port __ endgroup_if_needed(_size == 12);
3100 __ bind(done);
3101 %}
3103 // New atomics.
3104 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3105 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3107 MacroAssembler _masm(&cbuf);
3108 Register Rtmp = R0;
3109 Register Rres = $res$$Register;
3110 Register Rsrc = $src$$Register;
3111 Register Rptr = $mem_ptr$$Register;
3112 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3113 Register Rold = RegCollision ? Rtmp : Rres;
3115 Label Lretry;
3116 __ bind(Lretry);
3117 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3118 __ add(Rtmp, Rsrc, Rold);
3119 __ stwcx_(Rtmp, Rptr);
3120 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3121 __ bne_predict_not_taken(CCR0, Lretry);
3122 } else {
3123 __ bne( CCR0, Lretry);
3124 }
3125 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3126 __ fence();
3127 %}
3129 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3130 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3132 MacroAssembler _masm(&cbuf);
3133 Register Rtmp = R0;
3134 Register Rres = $res$$Register;
3135 Register Rsrc = $src$$Register;
3136 Register Rptr = $mem_ptr$$Register;
3137 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3138 Register Rold = RegCollision ? Rtmp : Rres;
3140 Label Lretry;
3141 __ bind(Lretry);
3142 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3143 __ add(Rtmp, Rsrc, Rold);
3144 __ stdcx_(Rtmp, Rptr);
3145 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3146 __ bne_predict_not_taken(CCR0, Lretry);
3147 } else {
3148 __ bne( CCR0, Lretry);
3149 }
3150 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3151 __ fence();
3152 %}
3154 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3155 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3157 MacroAssembler _masm(&cbuf);
3158 Register Rtmp = R0;
3159 Register Rres = $res$$Register;
3160 Register Rsrc = $src$$Register;
3161 Register Rptr = $mem_ptr$$Register;
3162 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3163 Register Rold = RegCollision ? Rtmp : Rres;
3165 Label Lretry;
3166 __ bind(Lretry);
3167 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3168 __ stwcx_(Rsrc, Rptr);
3169 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3170 __ bne_predict_not_taken(CCR0, Lretry);
3171 } else {
3172 __ bne( CCR0, Lretry);
3173 }
3174 if (RegCollision) __ mr(Rres, Rtmp);
3175 __ fence();
3176 %}
3178 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3179 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3181 MacroAssembler _masm(&cbuf);
3182 Register Rtmp = R0;
3183 Register Rres = $res$$Register;
3184 Register Rsrc = $src$$Register;
3185 Register Rptr = $mem_ptr$$Register;
3186 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3187 Register Rold = RegCollision ? Rtmp : Rres;
3189 Label Lretry;
3190 __ bind(Lretry);
3191 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3192 __ stdcx_(Rsrc, Rptr);
3193 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3194 __ bne_predict_not_taken(CCR0, Lretry);
3195 } else {
3196 __ bne( CCR0, Lretry);
3197 }
3198 if (RegCollision) __ mr(Rres, Rtmp);
3199 __ fence();
3200 %}
3202 // This enc_class is needed so that scheduler gets proper
3203 // input mapping for latency computation.
3204 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3205 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3206 MacroAssembler _masm(&cbuf);
3207 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3208 %}
3210 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3211 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3213 MacroAssembler _masm(&cbuf);
3215 Label done;
3216 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3217 __ li($dst$$Register, $zero$$constant);
3218 __ beq($crx$$CondRegister, done);
3219 __ li($dst$$Register, $notzero$$constant);
3220 __ bind(done);
3221 %}
3223 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3224 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3226 MacroAssembler _masm(&cbuf);
3228 Label done;
3229 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3230 __ li($dst$$Register, $zero$$constant);
3231 __ beq($crx$$CondRegister, done);
3232 __ li($dst$$Register, $notzero$$constant);
3233 __ bind(done);
3234 %}
3236 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3237 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3239 MacroAssembler _masm(&cbuf);
3240 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3241 Label done;
3242 __ bso($crx$$CondRegister, done);
3243 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3244 // TODO PPC port __ endgroup_if_needed(_size == 12);
3245 __ bind(done);
3246 %}
3248 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3249 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3251 MacroAssembler _masm(&cbuf);
3252 Label d; // dummy
3253 __ bind(d);
3254 Label* p = ($lbl$$label);
3255 // `p' is `NULL' when this encoding class is used only to
3256 // determine the size of the encoded instruction.
3257 Label& l = (NULL == p)? d : *(p);
3258 int cc = $cmp$$cmpcode;
3259 int flags_reg = $crx$$reg;
3260 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3261 int bhint = Assembler::bhintNoHint;
3263 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3264 if (_prob <= PROB_NEVER) {
3265 bhint = Assembler::bhintIsNotTaken;
3266 } else if (_prob >= PROB_ALWAYS) {
3267 bhint = Assembler::bhintIsTaken;
3268 }
3269 }
3271 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3272 cc_to_biint(cc, flags_reg),
3273 l);
3274 %}
3276 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3277 // The scheduler doesn't know about branch shortening, so we set the opcode
3278 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3279 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3281 MacroAssembler _masm(&cbuf);
3282 Label d; // dummy
3283 __ bind(d);
3284 Label* p = ($lbl$$label);
3285 // `p' is `NULL' when this encoding class is used only to
3286 // determine the size of the encoded instruction.
3287 Label& l = (NULL == p)? d : *(p);
3288 int cc = $cmp$$cmpcode;
3289 int flags_reg = $crx$$reg;
3290 int bhint = Assembler::bhintNoHint;
3292 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3293 if (_prob <= PROB_NEVER) {
3294 bhint = Assembler::bhintIsNotTaken;
3295 } else if (_prob >= PROB_ALWAYS) {
3296 bhint = Assembler::bhintIsTaken;
3297 }
3298 }
3300 // Tell the conditional far branch to optimize itself when being relocated.
3301 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3302 cc_to_biint(cc, flags_reg),
3303 l,
3304 MacroAssembler::bc_far_optimize_on_relocate);
3305 %}
3307 // Branch used with Power6 scheduling (can be shortened without changing the node).
3308 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3309 // The scheduler doesn't know about branch shortening, so we set the opcode
3310 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3311 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3313 MacroAssembler _masm(&cbuf);
3314 Label d; // dummy
3315 __ bind(d);
3316 Label* p = ($lbl$$label);
3317 // `p' is `NULL' when this encoding class is used only to
3318 // determine the size of the encoded instruction.
3319 Label& l = (NULL == p)? d : *(p);
3320 int cc = $cmp$$cmpcode;
3321 int flags_reg = $crx$$reg;
3322 int bhint = Assembler::bhintNoHint;
3324 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3325 if (_prob <= PROB_NEVER) {
3326 bhint = Assembler::bhintIsNotTaken;
3327 } else if (_prob >= PROB_ALWAYS) {
3328 bhint = Assembler::bhintIsTaken;
3329 }
3330 }
3332 #if 0 // TODO: PPC port
3333 if (_size == 8) {
3334 // Tell the conditional far branch to optimize itself when being relocated.
3335 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3336 cc_to_biint(cc, flags_reg),
3337 l,
3338 MacroAssembler::bc_far_optimize_on_relocate);
3339 } else {
3340 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3341 cc_to_biint(cc, flags_reg),
3342 l);
3343 }
3344 #endif
3345 Unimplemented();
3346 %}
3348 // Postalloc expand emitter for loading a replicatef float constant from
3349 // the method's TOC.
3350 // Enc_class needed as consttanttablebase is not supported by postalloc
3351 // expand.
3352 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3353 // Create new nodes.
3355 // Make an operand with the bit pattern to load as float.
3356 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3358 loadConLNodesTuple loadConLNodes =
3359 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3360 ra_->get_reg_second(this), ra_->get_reg_first(this));
3362 // Push new nodes.
3363 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3364 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3366 assert(nodes->length() >= 1, "must have created at least 1 node");
3367 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3368 %}
3370 // This enc_class is needed so that scheduler gets proper
3371 // input mapping for latency computation.
3372 enc_class enc_poll(immI dst, iRegLdst poll) %{
3373 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3374 // Fake operand dst needed for PPC scheduler.
3375 assert($dst$$constant == 0x0, "dst must be 0x0");
3377 MacroAssembler _masm(&cbuf);
3378 // Mark the code position where the load from the safepoint
3379 // polling page was emitted as relocInfo::poll_type.
3380 __ relocate(relocInfo::poll_type);
3381 __ load_from_polling_page($poll$$Register);
3382 %}
3384 // A Java static call or a runtime call.
3385 //
3386 // Branch-and-link relative to a trampoline.
3387 // The trampoline loads the target address and does a long branch to there.
3388 // In case we call java, the trampoline branches to a interpreter_stub
3389 // which loads the inline cache and the real call target from the constant pool.
3390 //
3391 // This basically looks like this:
3392 //
3393 // >>>> consts -+ -+
3394 // | |- offset1
3395 // [call target1] | <-+
3396 // [IC cache] |- offset2
3397 // [call target2] <--+
3398 //
3399 // <<<< consts
3400 // >>>> insts
3401 //
3402 // bl offset16 -+ -+ ??? // How many bits available?
3403 // | |
3404 // <<<< insts | |
3405 // >>>> stubs | |
3406 // | |- trampoline_stub_Reloc
3407 // trampoline stub: | <-+
3408 // r2 = toc |
3409 // r2 = [r2 + offset1] | // Load call target1 from const section
3410 // mtctr r2 |
3411 // bctr |- static_stub_Reloc
3412 // comp_to_interp_stub: <---+
3413 // r1 = toc
3414 // ICreg = [r1 + IC_offset] // Load IC from const section
3415 // r1 = [r1 + offset2] // Load call target2 from const section
3416 // mtctr r1
3417 // bctr
3418 //
3419 // <<<< stubs
3420 //
3421 // The call instruction in the code either
3422 // - Branches directly to a compiled method if the offset is encodable in instruction.
3423 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3424 // - Branches to the compiled_to_interp stub if the target is interpreted.
3425 //
3426 // Further there are three relocations from the loads to the constants in
3427 // the constant section.
3428 //
3429 // Usage of r1 and r2 in the stubs allows to distinguish them.
3430 enc_class enc_java_static_call(method meth) %{
3431 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3433 MacroAssembler _masm(&cbuf);
3434 address entry_point = (address)$meth$$method;
3436 if (!_method) {
3437 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3438 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3439 } else {
3440 // Remember the offset not the address.
3441 const int start_offset = __ offset();
3442 // The trampoline stub.
3443 if (!Compile::current()->in_scratch_emit_size()) {
3444 // No entry point given, use the current pc.
3445 // Make sure branch fits into
3446 if (entry_point == 0) entry_point = __ pc();
3448 // Put the entry point as a constant into the constant pool.
3449 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3450 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3452 // Emit the trampoline stub which will be related to the branch-and-link below.
3453 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3454 __ relocate(_optimized_virtual ?
3455 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3456 }
3458 // The real call.
3459 // Note: At this point we do not have the address of the trampoline
3460 // stub, and the entry point might be too far away for bl, so __ pc()
3461 // serves as dummy and the bl will be patched later.
3462 cbuf.set_insts_mark();
3463 __ bl(__ pc()); // Emits a relocation.
3465 // The stub for call to interpreter.
3466 CompiledStaticCall::emit_to_interp_stub(cbuf);
3467 }
3468 %}
3470 // Emit a method handle call.
3471 //
3472 // Method handle calls from compiled to compiled are going thru a
3473 // c2i -> i2c adapter, extending the frame for their arguments. The
3474 // caller however, returns directly to the compiled callee, that has
3475 // to cope with the extended frame. We restore the original frame by
3476 // loading the callers sp and adding the calculated framesize.
3477 enc_class enc_java_handle_call(method meth) %{
3478 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3480 MacroAssembler _masm(&cbuf);
3481 address entry_point = (address)$meth$$method;
3483 // Remember the offset not the address.
3484 const int start_offset = __ offset();
3485 // The trampoline stub.
3486 if (!ra_->C->in_scratch_emit_size()) {
3487 // No entry point given, use the current pc.
3488 // Make sure branch fits into
3489 if (entry_point == 0) entry_point = __ pc();
3491 // Put the entry point as a constant into the constant pool.
3492 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3493 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3495 // Emit the trampoline stub which will be related to the branch-and-link below.
3496 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3497 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3498 __ relocate(relocInfo::opt_virtual_call_type);
3499 }
3501 // The real call.
3502 // Note: At this point we do not have the address of the trampoline
3503 // stub, and the entry point might be too far away for bl, so __ pc()
3504 // serves as dummy and the bl will be patched later.
3505 cbuf.set_insts_mark();
3506 __ bl(__ pc()); // Emits a relocation.
3508 assert(_method, "execute next statement conditionally");
3509 // The stub for call to interpreter.
3510 CompiledStaticCall::emit_to_interp_stub(cbuf);
3512 // Restore original sp.
3513 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3514 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3515 unsigned int bytes = (unsigned int)framesize;
3516 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3517 if (Assembler::is_simm(-offset, 16)) {
3518 __ addi(R1_SP, R11_scratch1, -offset);
3519 } else {
3520 __ load_const_optimized(R12_scratch2, -offset);
3521 __ add(R1_SP, R11_scratch1, R12_scratch2);
3522 }
3523 #ifdef ASSERT
3524 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3525 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3526 __ asm_assert_eq("backlink changed", 0x8000);
3527 #endif
3528 // If fails should store backlink before unextending.
3530 if (ra_->C->env()->failing()) {
3531 return;
3532 }
3533 %}
3535 // Second node of expanded dynamic call - the call.
3536 enc_class enc_java_dynamic_call_sched(method meth) %{
3537 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3539 MacroAssembler _masm(&cbuf);
3541 if (!ra_->C->in_scratch_emit_size()) {
3542 // Create a call trampoline stub for the given method.
3543 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3544 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3545 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3546 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3548 if (ra_->C->env()->failing())
3549 return;
3551 // Build relocation at call site with ic position as data.
3552 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3553 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3554 "must have one, but can't have both");
3555 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3556 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3557 "must contain instruction offset");
3558 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3559 ? _load_ic_hi_node->_cbuf_insts_offset
3560 : _load_ic_node->_cbuf_insts_offset;
3561 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3562 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3563 "should be load from TOC");
3565 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3566 }
3568 // At this point I do not have the address of the trampoline stub,
3569 // and the entry point might be too far away for bl. Pc() serves
3570 // as dummy and bl will be patched later.
3571 __ bl((address) __ pc());
3572 %}
3574 // postalloc expand emitter for virtual calls.
3575 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3577 // Create the nodes for loading the IC from the TOC.
3578 loadConLNodesTuple loadConLNodes_IC =
3579 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3580 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3582 // Create the call node.
3583 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3584 call->_method_handle_invoke = _method_handle_invoke;
3585 call->_vtable_index = _vtable_index;
3586 call->_method = _method;
3587 call->_bci = _bci;
3588 call->_optimized_virtual = _optimized_virtual;
3589 call->_tf = _tf;
3590 call->_entry_point = _entry_point;
3591 call->_cnt = _cnt;
3592 call->_argsize = _argsize;
3593 call->_oop_map = _oop_map;
3594 call->_jvms = _jvms;
3595 call->_jvmadj = _jvmadj;
3596 call->_in_rms = _in_rms;
3597 call->_nesting = _nesting;
3599 // New call needs all inputs of old call.
3600 // Req...
3601 for (uint i = 0; i < req(); ++i) {
3602 // The expanded node does not need toc any more.
3603 // Add the inline cache constant here instead. This expresses the
3604 // register of the inline cache must be live at the call.
3605 // Else we would have to adapt JVMState by -1.
3606 if (i == mach_constant_base_node_input()) {
3607 call->add_req(loadConLNodes_IC._last);
3608 } else {
3609 call->add_req(in(i));
3610 }
3611 }
3612 // ...as well as prec
3613 for (uint i = req(); i < len(); ++i) {
3614 call->add_prec(in(i));
3615 }
3617 // Remember nodes loading the inline cache into r19.
3618 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3619 call->_load_ic_node = loadConLNodes_IC._small;
3621 // Operands for new nodes.
3622 call->_opnds[0] = _opnds[0];
3623 call->_opnds[1] = _opnds[1];
3625 // Only the inline cache is associated with a register.
3626 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3628 // Push new nodes.
3629 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3630 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3631 nodes->push(call);
3632 %}
3634 // Compound version of call dynamic
3635 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3636 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3637 MacroAssembler _masm(&cbuf);
3638 int start_offset = __ offset();
3640 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3641 #if 0
3642 if (_vtable_index < 0) {
3643 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3644 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3645 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3646 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3648 address virtual_call_meta_addr = __ pc();
3649 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3650 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3651 // to determine who we intended to call.
3652 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3653 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3654 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3655 "Fix constant in ret_addr_offset()");
3656 } else {
3657 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3658 // Go thru the vtable. Get receiver klass. Receiver already
3659 // checked for non-null. If we'll go thru a C2I adapter, the
3660 // interpreter expects method in R19_method.
3662 __ load_klass(R11_scratch1, R3);
3664 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3665 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3666 __ li(R19_method, v_off);
3667 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3668 // NOTE: for vtable dispatches, the vtable entry will never be
3669 // null. However it may very well end up in handle_wrong_method
3670 // if the method is abstract for the particular class.
3671 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3672 // Call target. Either compiled code or C2I adapter.
3673 __ mtctr(R11_scratch1);
3674 __ bctrl();
3675 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3676 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3677 }
3678 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3679 "Fix constant in ret_addr_offset()");
3680 }
3681 #endif
3682 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3683 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3684 %}
3686 // a runtime call
3687 enc_class enc_java_to_runtime_call (method meth) %{
3688 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3690 MacroAssembler _masm(&cbuf);
3691 const address start_pc = __ pc();
3693 #if defined(ABI_ELFv2)
3694 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3695 __ call_c(entry, relocInfo::runtime_call_type);
3696 #else
3697 // The function we're going to call.
3698 FunctionDescriptor fdtemp;
3699 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3701 Register Rtoc = R12_scratch2;
3702 // Calculate the method's TOC.
3703 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3704 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3705 // pool entries; call_c_using_toc will optimize the call.
3706 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3707 #endif
3709 // Check the ret_addr_offset.
3710 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3711 "Fix constant in ret_addr_offset()");
3712 %}
3714 // Move to ctr for leaf call.
3715 // This enc_class is needed so that scheduler gets proper
3716 // input mapping for latency computation.
3717 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3718 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3719 MacroAssembler _masm(&cbuf);
3720 __ mtctr($src$$Register);
3721 %}
3723 // Postalloc expand emitter for runtime leaf calls.
3724 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3725 loadConLNodesTuple loadConLNodes_Entry;
3726 #if defined(ABI_ELFv2)
3727 jlong entry_address = (jlong) this->entry_point();
3728 assert(entry_address, "need address here");
3729 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3730 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3731 #else
3732 // Get the struct that describes the function we are about to call.
3733 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3734 assert(fd, "need fd here");
3735 jlong entry_address = (jlong) fd->entry();
3736 // new nodes
3737 loadConLNodesTuple loadConLNodes_Env;
3738 loadConLNodesTuple loadConLNodes_Toc;
3740 // Create nodes and operands for loading the entry point.
3741 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3742 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3745 // Create nodes and operands for loading the env pointer.
3746 if (fd->env() != NULL) {
3747 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3748 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3749 } else {
3750 loadConLNodes_Env._large_hi = NULL;
3751 loadConLNodes_Env._large_lo = NULL;
3752 loadConLNodes_Env._small = NULL;
3753 loadConLNodes_Env._last = new (C) loadConL16Node();
3754 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3755 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3756 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3757 }
3759 // Create nodes and operands for loading the Toc point.
3760 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3761 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3762 #endif // ABI_ELFv2
3763 // mtctr node
3764 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3766 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3767 mtctr->add_req(0, loadConLNodes_Entry._last);
3769 mtctr->_opnds[0] = new (C) iRegLdstOper();
3770 mtctr->_opnds[1] = new (C) iRegLdstOper();
3772 // call node
3773 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3775 call->_opnds[0] = _opnds[0];
3776 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3778 // Make the new call node look like the old one.
3779 call->_name = _name;
3780 call->_tf = _tf;
3781 call->_entry_point = _entry_point;
3782 call->_cnt = _cnt;
3783 call->_argsize = _argsize;
3784 call->_oop_map = _oop_map;
3785 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3786 call->_jvms = NULL;
3787 call->_jvmadj = _jvmadj;
3788 call->_in_rms = _in_rms;
3789 call->_nesting = _nesting;
3792 // New call needs all inputs of old call.
3793 // Req...
3794 for (uint i = 0; i < req(); ++i) {
3795 if (i != mach_constant_base_node_input()) {
3796 call->add_req(in(i));
3797 }
3798 }
3800 // These must be reqired edges, as the registers are live up to
3801 // the call. Else the constants are handled as kills.
3802 call->add_req(mtctr);
3803 #if !defined(ABI_ELFv2)
3804 call->add_req(loadConLNodes_Env._last);
3805 call->add_req(loadConLNodes_Toc._last);
3806 #endif
3808 // ...as well as prec
3809 for (uint i = req(); i < len(); ++i) {
3810 call->add_prec(in(i));
3811 }
3813 // registers
3814 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3816 // Insert the new nodes.
3817 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3818 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3819 #if !defined(ABI_ELFv2)
3820 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3821 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3822 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3823 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3824 #endif
3825 nodes->push(mtctr);
3826 nodes->push(call);
3827 %}
3828 %}
3830 //----------FRAME--------------------------------------------------------------
3831 // Definition of frame structure and management information.
3833 frame %{
3834 // What direction does stack grow in (assumed to be same for native & Java).
3835 stack_direction(TOWARDS_LOW);
3837 // These two registers define part of the calling convention between
3838 // compiled code and the interpreter.
3840 // Inline Cache Register or method for I2C.
3841 inline_cache_reg(R19); // R19_method
3843 // Method Oop Register when calling interpreter.
3844 interpreter_method_oop_reg(R19); // R19_method
3846 // Optional: name the operand used by cisc-spilling to access
3847 // [stack_pointer + offset].
3848 cisc_spilling_operand_name(indOffset);
3850 // Number of stack slots consumed by a Monitor enter.
3851 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3853 // Compiled code's Frame Pointer.
3854 frame_pointer(R1); // R1_SP
3856 // Interpreter stores its frame pointer in a register which is
3857 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3858 // interpreted java to compiled java.
3859 //
3860 // R14_state holds pointer to caller's cInterpreter.
3861 interpreter_frame_pointer(R14); // R14_state
3863 stack_alignment(frame::alignment_in_bytes);
3865 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3867 // Number of outgoing stack slots killed above the
3868 // out_preserve_stack_slots for calls to C. Supports the var-args
3869 // backing area for register parms.
3870 //
3871 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3873 // The after-PROLOG location of the return address. Location of
3874 // return address specifies a type (REG or STACK) and a number
3875 // representing the register number (i.e. - use a register name) or
3876 // stack slot.
3877 //
3878 // A: Link register is stored in stack slot ...
3879 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3880 // J: Therefore, we make sure that the link register is also in R11_scratch1
3881 // at the end of the prolog.
3882 // B: We use R20, now.
3883 //return_addr(REG R20);
3885 // G: After reading the comments made by all the luminaries on their
3886 // failure to tell the compiler where the return address really is,
3887 // I hardly dare to try myself. However, I'm convinced it's in slot
3888 // 4 what apparently works and saves us some spills.
3889 return_addr(STACK 4);
3891 // This is the body of the function
3892 //
3893 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3894 // uint length, // length of array
3895 // bool is_outgoing)
3896 //
3897 // The `sig' array is to be updated. sig[j] represents the location
3898 // of the j-th argument, either a register or a stack slot.
3900 // Comment taken from i486.ad:
3901 // Body of function which returns an integer array locating
3902 // arguments either in registers or in stack slots. Passed an array
3903 // of ideal registers called "sig" and a "length" count. Stack-slot
3904 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3905 // arguments for a CALLEE. Incoming stack arguments are
3906 // automatically biased by the preserve_stack_slots field above.
3907 calling_convention %{
3908 // No difference between ingoing/outgoing. Just pass false.
3909 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3910 %}
3912 // Comment taken from i486.ad:
3913 // Body of function which returns an integer array locating
3914 // arguments either in registers or in stack slots. Passed an array
3915 // of ideal registers called "sig" and a "length" count. Stack-slot
3916 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3917 // arguments for a CALLEE. Incoming stack arguments are
3918 // automatically biased by the preserve_stack_slots field above.
3919 c_calling_convention %{
3920 // This is obviously always outgoing.
3921 // C argument in register AND stack slot.
3922 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3923 %}
3925 // Location of native (C/C++) and interpreter return values. This
3926 // is specified to be the same as Java. In the 32-bit VM, long
3927 // values are actually returned from native calls in O0:O1 and
3928 // returned to the interpreter in I0:I1. The copying to and from
3929 // the register pairs is done by the appropriate call and epilog
3930 // opcodes. This simplifies the register allocator.
3931 c_return_value %{
3932 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3933 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3934 "only return normal values");
3935 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3936 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3937 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3938 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3939 %}
3941 // Location of compiled Java return values. Same as C
3942 return_value %{
3943 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3944 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3945 "only return normal values");
3946 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3947 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3948 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3949 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3950 %}
3951 %}
3954 //----------ATTRIBUTES---------------------------------------------------------
3956 //----------Operand Attributes-------------------------------------------------
3957 op_attrib op_cost(1); // Required cost attribute.
3959 //----------Instruction Attributes---------------------------------------------
3961 // Cost attribute. required.
3962 ins_attrib ins_cost(DEFAULT_COST);
3964 // Is this instruction a non-matching short branch variant of some
3965 // long branch? Not required.
3966 ins_attrib ins_short_branch(0);
3968 ins_attrib ins_is_TrapBasedCheckNode(true);
3970 // Number of constants.
3971 // This instruction uses the given number of constants
3972 // (optional attribute).
3973 // This is needed to determine in time whether the constant pool will
3974 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3975 // is determined. It's also used to compute the constant pool size
3976 // in Output().
3977 ins_attrib ins_num_consts(0);
3979 // Required alignment attribute (must be a power of 2) specifies the
3980 // alignment that some part of the instruction (not necessarily the
3981 // start) requires. If > 1, a compute_padding() function must be
3982 // provided for the instruction.
3983 ins_attrib ins_alignment(1);
3985 // Enforce/prohibit rematerializations.
3986 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3987 // then rematerialization of that instruction is prohibited and the
3988 // instruction's value will be spilled if necessary.
3989 // Causes that MachNode::rematerialize() returns false.
3990 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3991 // then rematerialization should be enforced and a copy of the instruction
3992 // should be inserted if possible; rematerialization is not guaranteed.
3993 // Note: this may result in rematerializations in front of every use.
3994 // Causes that MachNode::rematerialize() can return true.
3995 // (optional attribute)
3996 ins_attrib ins_cannot_rematerialize(false);
3997 ins_attrib ins_should_rematerialize(false);
3999 // Instruction has variable size depending on alignment.
4000 ins_attrib ins_variable_size_depending_on_alignment(false);
4002 // Instruction is a nop.
4003 ins_attrib ins_is_nop(false);
4005 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4006 ins_attrib ins_use_mach_if_fast_lock_node(false);
4008 // Field for the toc offset of a constant.
4009 //
4010 // This is needed if the toc offset is not encodable as an immediate in
4011 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4012 // added to the toc, and from this a load with immediate is performed.
4013 // With postalloc expand, we get two nodes that require the same offset
4014 // but which don't know about each other. The offset is only known
4015 // when the constant is added to the constant pool during emitting.
4016 // It is generated in the 'hi'-node adding the upper bits, and saved
4017 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4018 // the offset from there when it gets encoded.
4019 ins_attrib ins_field_const_toc_offset(0);
4020 ins_attrib ins_field_const_toc_offset_hi_node(0);
4022 // A field that can hold the instructions offset in the code buffer.
4023 // Set in the nodes emitter.
4024 ins_attrib ins_field_cbuf_insts_offset(-1);
4026 // Fields for referencing a call's load-IC-node.
4027 // If the toc offset can not be encoded as an immediate in a load, we
4028 // use two nodes.
4029 ins_attrib ins_field_load_ic_hi_node(0);
4030 ins_attrib ins_field_load_ic_node(0);
4032 //----------OPERANDS-----------------------------------------------------------
4033 // Operand definitions must precede instruction definitions for correct
4034 // parsing in the ADLC because operands constitute user defined types
4035 // which are used in instruction definitions.
4036 //
4037 // Formats are generated automatically for constants and base registers.
4039 //----------Simple Operands----------------------------------------------------
4040 // Immediate Operands
4042 // Integer Immediate: 32-bit
4043 operand immI() %{
4044 match(ConI);
4045 op_cost(40);
4046 format %{ %}
4047 interface(CONST_INTER);
4048 %}
4050 operand immI8() %{
4051 predicate(Assembler::is_simm(n->get_int(), 8));
4052 op_cost(0);
4053 match(ConI);
4054 format %{ %}
4055 interface(CONST_INTER);
4056 %}
4058 // Integer Immediate: 16-bit
4059 operand immI16() %{
4060 predicate(Assembler::is_simm(n->get_int(), 16));
4061 op_cost(0);
4062 match(ConI);
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4067 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4068 operand immIhi16() %{
4069 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4070 match(ConI);
4071 op_cost(0);
4072 format %{ %}
4073 interface(CONST_INTER);
4074 %}
4076 operand immInegpow2() %{
4077 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4078 match(ConI);
4079 op_cost(0);
4080 format %{ %}
4081 interface(CONST_INTER);
4082 %}
4084 operand immIpow2minus1() %{
4085 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4086 match(ConI);
4087 op_cost(0);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4092 operand immIpowerOf2() %{
4093 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4094 match(ConI);
4095 op_cost(0);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4100 // Unsigned Integer Immediate: the values 0-31
4101 operand uimmI5() %{
4102 predicate(Assembler::is_uimm(n->get_int(), 5));
4103 match(ConI);
4104 op_cost(0);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4109 // Unsigned Integer Immediate: 6-bit
4110 operand uimmI6() %{
4111 predicate(Assembler::is_uimm(n->get_int(), 6));
4112 match(ConI);
4113 op_cost(0);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4118 // Unsigned Integer Immediate: 6-bit int, greater than 32
4119 operand uimmI6_ge32() %{
4120 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4121 match(ConI);
4122 op_cost(0);
4123 format %{ %}
4124 interface(CONST_INTER);
4125 %}
4127 // Unsigned Integer Immediate: 15-bit
4128 operand uimmI15() %{
4129 predicate(Assembler::is_uimm(n->get_int(), 15));
4130 match(ConI);
4131 op_cost(0);
4132 format %{ %}
4133 interface(CONST_INTER);
4134 %}
4136 // Unsigned Integer Immediate: 16-bit
4137 operand uimmI16() %{
4138 predicate(Assembler::is_uimm(n->get_int(), 16));
4139 match(ConI);
4140 op_cost(0);
4141 format %{ %}
4142 interface(CONST_INTER);
4143 %}
4145 // constant 'int 0'.
4146 operand immI_0() %{
4147 predicate(n->get_int() == 0);
4148 match(ConI);
4149 op_cost(0);
4150 format %{ %}
4151 interface(CONST_INTER);
4152 %}
4154 // constant 'int 1'.
4155 operand immI_1() %{
4156 predicate(n->get_int() == 1);
4157 match(ConI);
4158 op_cost(0);
4159 format %{ %}
4160 interface(CONST_INTER);
4161 %}
4163 // constant 'int -1'.
4164 operand immI_minus1() %{
4165 predicate(n->get_int() == -1);
4166 match(ConI);
4167 op_cost(0);
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4172 // int value 16.
4173 operand immI_16() %{
4174 predicate(n->get_int() == 16);
4175 match(ConI);
4176 op_cost(0);
4177 format %{ %}
4178 interface(CONST_INTER);
4179 %}
4181 // int value 24.
4182 operand immI_24() %{
4183 predicate(n->get_int() == 24);
4184 match(ConI);
4185 op_cost(0);
4186 format %{ %}
4187 interface(CONST_INTER);
4188 %}
4190 // Compressed oops constants
4191 // Pointer Immediate
4192 operand immN() %{
4193 match(ConN);
4195 op_cost(10);
4196 format %{ %}
4197 interface(CONST_INTER);
4198 %}
4200 // NULL Pointer Immediate
4201 operand immN_0() %{
4202 predicate(n->get_narrowcon() == 0);
4203 match(ConN);
4205 op_cost(0);
4206 format %{ %}
4207 interface(CONST_INTER);
4208 %}
4210 // Compressed klass constants
4211 operand immNKlass() %{
4212 match(ConNKlass);
4214 op_cost(0);
4215 format %{ %}
4216 interface(CONST_INTER);
4217 %}
4219 // This operand can be used to avoid matching of an instruct
4220 // with chain rule.
4221 operand immNKlass_NM() %{
4222 match(ConNKlass);
4223 predicate(false);
4224 op_cost(0);
4225 format %{ %}
4226 interface(CONST_INTER);
4227 %}
4229 // Pointer Immediate: 64-bit
4230 operand immP() %{
4231 match(ConP);
4232 op_cost(0);
4233 format %{ %}
4234 interface(CONST_INTER);
4235 %}
4237 // Operand to avoid match of loadConP.
4238 // This operand can be used to avoid matching of an instruct
4239 // with chain rule.
4240 operand immP_NM() %{
4241 match(ConP);
4242 predicate(false);
4243 op_cost(0);
4244 format %{ %}
4245 interface(CONST_INTER);
4246 %}
4248 // costant 'pointer 0'.
4249 operand immP_0() %{
4250 predicate(n->get_ptr() == 0);
4251 match(ConP);
4252 op_cost(0);
4253 format %{ %}
4254 interface(CONST_INTER);
4255 %}
4257 // pointer 0x0 or 0x1
4258 operand immP_0or1() %{
4259 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4260 match(ConP);
4261 op_cost(0);
4262 format %{ %}
4263 interface(CONST_INTER);
4264 %}
4266 operand immL() %{
4267 match(ConL);
4268 op_cost(40);
4269 format %{ %}
4270 interface(CONST_INTER);
4271 %}
4273 // Long Immediate: 16-bit
4274 operand immL16() %{
4275 predicate(Assembler::is_simm(n->get_long(), 16));
4276 match(ConL);
4277 op_cost(0);
4278 format %{ %}
4279 interface(CONST_INTER);
4280 %}
4282 // Long Immediate: 16-bit, 4-aligned
4283 operand immL16Alg4() %{
4284 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4285 match(ConL);
4286 op_cost(0);
4287 format %{ %}
4288 interface(CONST_INTER);
4289 %}
4291 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4292 operand immL32hi16() %{
4293 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4294 match(ConL);
4295 op_cost(0);
4296 format %{ %}
4297 interface(CONST_INTER);
4298 %}
4300 // Long Immediate: 32-bit
4301 operand immL32() %{
4302 predicate(Assembler::is_simm(n->get_long(), 32));
4303 match(ConL);
4304 op_cost(0);
4305 format %{ %}
4306 interface(CONST_INTER);
4307 %}
4309 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4310 operand immLhighest16() %{
4311 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4312 match(ConL);
4313 op_cost(0);
4314 format %{ %}
4315 interface(CONST_INTER);
4316 %}
4318 operand immLnegpow2() %{
4319 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4320 match(ConL);
4321 op_cost(0);
4322 format %{ %}
4323 interface(CONST_INTER);
4324 %}
4326 operand immLpow2minus1() %{
4327 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4328 (n->get_long() != (jlong)0xffffffffffffffffL));
4329 match(ConL);
4330 op_cost(0);
4331 format %{ %}
4332 interface(CONST_INTER);
4333 %}
4335 // constant 'long 0'.
4336 operand immL_0() %{
4337 predicate(n->get_long() == 0L);
4338 match(ConL);
4339 op_cost(0);
4340 format %{ %}
4341 interface(CONST_INTER);
4342 %}
4344 // constat ' long -1'.
4345 operand immL_minus1() %{
4346 predicate(n->get_long() == -1L);
4347 match(ConL);
4348 op_cost(0);
4349 format %{ %}
4350 interface(CONST_INTER);
4351 %}
4353 // Long Immediate: low 32-bit mask
4354 operand immL_32bits() %{
4355 predicate(n->get_long() == 0xFFFFFFFFL);
4356 match(ConL);
4357 op_cost(0);
4358 format %{ %}
4359 interface(CONST_INTER);
4360 %}
4362 // Unsigned Long Immediate: 16-bit
4363 operand uimmL16() %{
4364 predicate(Assembler::is_uimm(n->get_long(), 16));
4365 match(ConL);
4366 op_cost(0);
4367 format %{ %}
4368 interface(CONST_INTER);
4369 %}
4371 // Float Immediate
4372 operand immF() %{
4373 match(ConF);
4374 op_cost(40);
4375 format %{ %}
4376 interface(CONST_INTER);
4377 %}
4379 // constant 'float +0.0'.
4380 operand immF_0() %{
4381 predicate((n->getf() == 0) &&
4382 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4383 match(ConF);
4384 op_cost(0);
4385 format %{ %}
4386 interface(CONST_INTER);
4387 %}
4389 // Double Immediate
4390 operand immD() %{
4391 match(ConD);
4392 op_cost(40);
4393 format %{ %}
4394 interface(CONST_INTER);
4395 %}
4397 // Integer Register Operands
4398 // Integer Destination Register
4399 // See definition of reg_class bits32_reg_rw.
4400 operand iRegIdst() %{
4401 constraint(ALLOC_IN_RC(bits32_reg_rw));
4402 match(RegI);
4403 match(rscratch1RegI);
4404 match(rscratch2RegI);
4405 match(rarg1RegI);
4406 match(rarg2RegI);
4407 match(rarg3RegI);
4408 match(rarg4RegI);
4409 format %{ %}
4410 interface(REG_INTER);
4411 %}
4413 // Integer Source Register
4414 // See definition of reg_class bits32_reg_ro.
4415 operand iRegIsrc() %{
4416 constraint(ALLOC_IN_RC(bits32_reg_ro));
4417 match(RegI);
4418 match(rscratch1RegI);
4419 match(rscratch2RegI);
4420 match(rarg1RegI);
4421 match(rarg2RegI);
4422 match(rarg3RegI);
4423 match(rarg4RegI);
4424 format %{ %}
4425 interface(REG_INTER);
4426 %}
4428 operand rscratch1RegI() %{
4429 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4430 match(iRegIdst);
4431 format %{ %}
4432 interface(REG_INTER);
4433 %}
4435 operand rscratch2RegI() %{
4436 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4437 match(iRegIdst);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4442 operand rarg1RegI() %{
4443 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4444 match(iRegIdst);
4445 format %{ %}
4446 interface(REG_INTER);
4447 %}
4449 operand rarg2RegI() %{
4450 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4451 match(iRegIdst);
4452 format %{ %}
4453 interface(REG_INTER);
4454 %}
4456 operand rarg3RegI() %{
4457 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4458 match(iRegIdst);
4459 format %{ %}
4460 interface(REG_INTER);
4461 %}
4463 operand rarg4RegI() %{
4464 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4465 match(iRegIdst);
4466 format %{ %}
4467 interface(REG_INTER);
4468 %}
4470 operand rarg1RegL() %{
4471 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4472 match(iRegLdst);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4477 operand rarg2RegL() %{
4478 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4479 match(iRegLdst);
4480 format %{ %}
4481 interface(REG_INTER);
4482 %}
4484 operand rarg3RegL() %{
4485 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4486 match(iRegLdst);
4487 format %{ %}
4488 interface(REG_INTER);
4489 %}
4491 operand rarg4RegL() %{
4492 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4493 match(iRegLdst);
4494 format %{ %}
4495 interface(REG_INTER);
4496 %}
4498 // Pointer Destination Register
4499 // See definition of reg_class bits64_reg_rw.
4500 operand iRegPdst() %{
4501 constraint(ALLOC_IN_RC(bits64_reg_rw));
4502 match(RegP);
4503 match(rscratch1RegP);
4504 match(rscratch2RegP);
4505 match(rarg1RegP);
4506 match(rarg2RegP);
4507 match(rarg3RegP);
4508 match(rarg4RegP);
4509 format %{ %}
4510 interface(REG_INTER);
4511 %}
4513 // Pointer Destination Register
4514 // Operand not using r11 and r12 (killed in epilog).
4515 operand iRegPdstNoScratch() %{
4516 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4517 match(RegP);
4518 match(rarg1RegP);
4519 match(rarg2RegP);
4520 match(rarg3RegP);
4521 match(rarg4RegP);
4522 format %{ %}
4523 interface(REG_INTER);
4524 %}
4526 // Pointer Source Register
4527 // See definition of reg_class bits64_reg_ro.
4528 operand iRegPsrc() %{
4529 constraint(ALLOC_IN_RC(bits64_reg_ro));
4530 match(RegP);
4531 match(iRegPdst);
4532 match(rscratch1RegP);
4533 match(rscratch2RegP);
4534 match(rarg1RegP);
4535 match(rarg2RegP);
4536 match(rarg3RegP);
4537 match(rarg4RegP);
4538 match(threadRegP);
4539 format %{ %}
4540 interface(REG_INTER);
4541 %}
4543 // Thread operand.
4544 operand threadRegP() %{
4545 constraint(ALLOC_IN_RC(thread_bits64_reg));
4546 match(iRegPdst);
4547 format %{ "R16" %}
4548 interface(REG_INTER);
4549 %}
4551 operand rscratch1RegP() %{
4552 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4553 match(iRegPdst);
4554 format %{ "R11" %}
4555 interface(REG_INTER);
4556 %}
4558 operand rscratch2RegP() %{
4559 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4560 match(iRegPdst);
4561 format %{ %}
4562 interface(REG_INTER);
4563 %}
4565 operand rarg1RegP() %{
4566 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4567 match(iRegPdst);
4568 format %{ %}
4569 interface(REG_INTER);
4570 %}
4572 operand rarg2RegP() %{
4573 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4574 match(iRegPdst);
4575 format %{ %}
4576 interface(REG_INTER);
4577 %}
4579 operand rarg3RegP() %{
4580 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4581 match(iRegPdst);
4582 format %{ %}
4583 interface(REG_INTER);
4584 %}
4586 operand rarg4RegP() %{
4587 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4588 match(iRegPdst);
4589 format %{ %}
4590 interface(REG_INTER);
4591 %}
4593 operand iRegNsrc() %{
4594 constraint(ALLOC_IN_RC(bits32_reg_ro));
4595 match(RegN);
4596 match(iRegNdst);
4598 format %{ %}
4599 interface(REG_INTER);
4600 %}
4602 operand iRegNdst() %{
4603 constraint(ALLOC_IN_RC(bits32_reg_rw));
4604 match(RegN);
4606 format %{ %}
4607 interface(REG_INTER);
4608 %}
4610 // Long Destination Register
4611 // See definition of reg_class bits64_reg_rw.
4612 operand iRegLdst() %{
4613 constraint(ALLOC_IN_RC(bits64_reg_rw));
4614 match(RegL);
4615 match(rscratch1RegL);
4616 match(rscratch2RegL);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4621 // Long Source Register
4622 // See definition of reg_class bits64_reg_ro.
4623 operand iRegLsrc() %{
4624 constraint(ALLOC_IN_RC(bits64_reg_ro));
4625 match(RegL);
4626 match(iRegLdst);
4627 match(rscratch1RegL);
4628 match(rscratch2RegL);
4629 format %{ %}
4630 interface(REG_INTER);
4631 %}
4633 // Special operand for ConvL2I.
4634 operand iRegL2Isrc(iRegLsrc reg) %{
4635 constraint(ALLOC_IN_RC(bits64_reg_ro));
4636 match(ConvL2I reg);
4637 format %{ "ConvL2I($reg)" %}
4638 interface(REG_INTER)
4639 %}
4641 operand rscratch1RegL() %{
4642 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4643 match(RegL);
4644 format %{ %}
4645 interface(REG_INTER);
4646 %}
4648 operand rscratch2RegL() %{
4649 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4650 match(RegL);
4651 format %{ %}
4652 interface(REG_INTER);
4653 %}
4655 // Condition Code Flag Registers
4656 operand flagsReg() %{
4657 constraint(ALLOC_IN_RC(int_flags));
4658 match(RegFlags);
4659 format %{ %}
4660 interface(REG_INTER);
4661 %}
4663 // Condition Code Flag Register CR0
4664 operand flagsRegCR0() %{
4665 constraint(ALLOC_IN_RC(int_flags_CR0));
4666 match(RegFlags);
4667 format %{ "CR0" %}
4668 interface(REG_INTER);
4669 %}
4671 operand flagsRegCR1() %{
4672 constraint(ALLOC_IN_RC(int_flags_CR1));
4673 match(RegFlags);
4674 format %{ "CR1" %}
4675 interface(REG_INTER);
4676 %}
4678 operand flagsRegCR6() %{
4679 constraint(ALLOC_IN_RC(int_flags_CR6));
4680 match(RegFlags);
4681 format %{ "CR6" %}
4682 interface(REG_INTER);
4683 %}
4685 operand regCTR() %{
4686 constraint(ALLOC_IN_RC(ctr_reg));
4687 // RegFlags should work. Introducing a RegSpecial type would cause a
4688 // lot of changes.
4689 match(RegFlags);
4690 format %{"SR_CTR" %}
4691 interface(REG_INTER);
4692 %}
4694 operand regD() %{
4695 constraint(ALLOC_IN_RC(dbl_reg));
4696 match(RegD);
4697 format %{ %}
4698 interface(REG_INTER);
4699 %}
4701 operand regF() %{
4702 constraint(ALLOC_IN_RC(flt_reg));
4703 match(RegF);
4704 format %{ %}
4705 interface(REG_INTER);
4706 %}
4708 // Special Registers
4710 // Method Register
4711 operand inline_cache_regP(iRegPdst reg) %{
4712 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4713 match(reg);
4714 format %{ %}
4715 interface(REG_INTER);
4716 %}
4718 operand compiler_method_oop_regP(iRegPdst reg) %{
4719 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4720 match(reg);
4721 format %{ %}
4722 interface(REG_INTER);
4723 %}
4725 operand interpreter_method_oop_regP(iRegPdst reg) %{
4726 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4727 match(reg);
4728 format %{ %}
4729 interface(REG_INTER);
4730 %}
4732 // Operands to remove register moves in unscaled mode.
4733 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4734 operand iRegP2N(iRegPsrc reg) %{
4735 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4736 constraint(ALLOC_IN_RC(bits64_reg_ro));
4737 match(EncodeP reg);
4738 format %{ "$reg" %}
4739 interface(REG_INTER)
4740 %}
4742 operand iRegN2P(iRegNsrc reg) %{
4743 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4744 constraint(ALLOC_IN_RC(bits32_reg_ro));
4745 match(DecodeN reg);
4746 match(DecodeNKlass reg);
4747 format %{ "$reg" %}
4748 interface(REG_INTER)
4749 %}
4751 //----------Complex Operands---------------------------------------------------
4752 // Indirect Memory Reference
4753 operand indirect(iRegPsrc reg) %{
4754 constraint(ALLOC_IN_RC(bits64_reg_ro));
4755 match(reg);
4756 op_cost(100);
4757 format %{ "[$reg]" %}
4758 interface(MEMORY_INTER) %{
4759 base($reg);
4760 index(0x0);
4761 scale(0x0);
4762 disp(0x0);
4763 %}
4764 %}
4766 // Indirect with Offset
4767 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4768 constraint(ALLOC_IN_RC(bits64_reg_ro));
4769 match(AddP reg offset);
4770 op_cost(100);
4771 format %{ "[$reg + $offset]" %}
4772 interface(MEMORY_INTER) %{
4773 base($reg);
4774 index(0x0);
4775 scale(0x0);
4776 disp($offset);
4777 %}
4778 %}
4780 // Indirect with 4-aligned Offset
4781 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4782 constraint(ALLOC_IN_RC(bits64_reg_ro));
4783 match(AddP reg offset);
4784 op_cost(100);
4785 format %{ "[$reg + $offset]" %}
4786 interface(MEMORY_INTER) %{
4787 base($reg);
4788 index(0x0);
4789 scale(0x0);
4790 disp($offset);
4791 %}
4792 %}
4794 //----------Complex Operands for Compressed OOPs-------------------------------
4795 // Compressed OOPs with narrow_oop_shift == 0.
4797 // Indirect Memory Reference, compressed OOP
4798 operand indirectNarrow(iRegNsrc reg) %{
4799 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4800 constraint(ALLOC_IN_RC(bits64_reg_ro));
4801 match(DecodeN reg);
4802 match(DecodeNKlass reg);
4803 op_cost(100);
4804 format %{ "[$reg]" %}
4805 interface(MEMORY_INTER) %{
4806 base($reg);
4807 index(0x0);
4808 scale(0x0);
4809 disp(0x0);
4810 %}
4811 %}
4813 // Indirect with Offset, compressed OOP
4814 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4815 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4816 constraint(ALLOC_IN_RC(bits64_reg_ro));
4817 match(AddP (DecodeN reg) offset);
4818 match(AddP (DecodeNKlass reg) offset);
4819 op_cost(100);
4820 format %{ "[$reg + $offset]" %}
4821 interface(MEMORY_INTER) %{
4822 base($reg);
4823 index(0x0);
4824 scale(0x0);
4825 disp($offset);
4826 %}
4827 %}
4829 // Indirect with 4-aligned Offset, compressed OOP
4830 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4831 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4832 constraint(ALLOC_IN_RC(bits64_reg_ro));
4833 match(AddP (DecodeN reg) offset);
4834 match(AddP (DecodeNKlass reg) offset);
4835 op_cost(100);
4836 format %{ "[$reg + $offset]" %}
4837 interface(MEMORY_INTER) %{
4838 base($reg);
4839 index(0x0);
4840 scale(0x0);
4841 disp($offset);
4842 %}
4843 %}
4845 //----------Special Memory Operands--------------------------------------------
4846 // Stack Slot Operand
4847 //
4848 // This operand is used for loading and storing temporary values on
4849 // the stack where a match requires a value to flow through memory.
4850 operand stackSlotI(sRegI reg) %{
4851 constraint(ALLOC_IN_RC(stack_slots));
4852 op_cost(100);
4853 //match(RegI);
4854 format %{ "[sp+$reg]" %}
4855 interface(MEMORY_INTER) %{
4856 base(0x1); // R1_SP
4857 index(0x0);
4858 scale(0x0);
4859 disp($reg); // Stack Offset
4860 %}
4861 %}
4863 operand stackSlotL(sRegL reg) %{
4864 constraint(ALLOC_IN_RC(stack_slots));
4865 op_cost(100);
4866 //match(RegL);
4867 format %{ "[sp+$reg]" %}
4868 interface(MEMORY_INTER) %{
4869 base(0x1); // R1_SP
4870 index(0x0);
4871 scale(0x0);
4872 disp($reg); // Stack Offset
4873 %}
4874 %}
4876 operand stackSlotP(sRegP reg) %{
4877 constraint(ALLOC_IN_RC(stack_slots));
4878 op_cost(100);
4879 //match(RegP);
4880 format %{ "[sp+$reg]" %}
4881 interface(MEMORY_INTER) %{
4882 base(0x1); // R1_SP
4883 index(0x0);
4884 scale(0x0);
4885 disp($reg); // Stack Offset
4886 %}
4887 %}
4889 operand stackSlotF(sRegF reg) %{
4890 constraint(ALLOC_IN_RC(stack_slots));
4891 op_cost(100);
4892 //match(RegF);
4893 format %{ "[sp+$reg]" %}
4894 interface(MEMORY_INTER) %{
4895 base(0x1); // R1_SP
4896 index(0x0);
4897 scale(0x0);
4898 disp($reg); // Stack Offset
4899 %}
4900 %}
4902 operand stackSlotD(sRegD reg) %{
4903 constraint(ALLOC_IN_RC(stack_slots));
4904 op_cost(100);
4905 //match(RegD);
4906 format %{ "[sp+$reg]" %}
4907 interface(MEMORY_INTER) %{
4908 base(0x1); // R1_SP
4909 index(0x0);
4910 scale(0x0);
4911 disp($reg); // Stack Offset
4912 %}
4913 %}
4915 // Operands for expressing Control Flow
4916 // NOTE: Label is a predefined operand which should not be redefined in
4917 // the AD file. It is generically handled within the ADLC.
4919 //----------Conditional Branch Operands----------------------------------------
4920 // Comparison Op
4921 //
4922 // This is the operation of the comparison, and is limited to the
4923 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4924 // (!=).
4925 //
4926 // Other attributes of the comparison, such as unsignedness, are specified
4927 // by the comparison instruction that sets a condition code flags register.
4928 // That result is represented by a flags operand whose subtype is appropriate
4929 // to the unsignedness (etc.) of the comparison.
4930 //
4931 // Later, the instruction which matches both the Comparison Op (a Bool) and
4932 // the flags (produced by the Cmp) specifies the coding of the comparison op
4933 // by matching a specific subtype of Bool operand below.
4935 // When used for floating point comparisons: unordered same as less.
4936 operand cmpOp() %{
4937 match(Bool);
4938 format %{ "" %}
4939 interface(COND_INTER) %{
4940 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4941 // BO & BI
4942 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4943 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4944 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4945 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4946 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4947 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4948 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4949 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4950 %}
4951 %}
4953 //----------OPERAND CLASSES----------------------------------------------------
4954 // Operand Classes are groups of operands that are used to simplify
4955 // instruction definitions by not requiring the AD writer to specify
4956 // seperate instructions for every form of operand when the
4957 // instruction accepts multiple operand types with the same basic
4958 // encoding and format. The classic case of this is memory operands.
4959 // Indirect is not included since its use is limited to Compare & Swap.
4961 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4962 // Memory operand where offsets are 4-aligned. Required for ld, std.
4963 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4964 opclass indirectMemory(indirect, indirectNarrow);
4966 // Special opclass for I and ConvL2I.
4967 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4969 // Operand classes to match encode and decode. iRegN_P2N is only used
4970 // for storeN. I have never seen an encode node elsewhere.
4971 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4972 opclass iRegP_N2P(iRegPsrc, iRegN2P);
4974 //----------PIPELINE-----------------------------------------------------------
4976 pipeline %{
4978 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4979 // J. Res. & Dev., No. 1, Jan. 2002.
4981 //----------ATTRIBUTES---------------------------------------------------------
4982 attributes %{
4984 // Power4 instructions are of fixed length.
4985 fixed_size_instructions;
4987 // TODO: if `bundle' means number of instructions fetched
4988 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4989 // max instructions issued per cycle, this is 5.
4990 max_instructions_per_bundle = 8;
4992 // A Power4 instruction is 4 bytes long.
4993 instruction_unit_size = 4;
4995 // The Power4 processor fetches 64 bytes...
4996 instruction_fetch_unit_size = 64;
4998 // ...in one line
4999 instruction_fetch_units = 1
5001 // Unused, list one so that array generated by adlc is not empty.
5002 // Aix compiler chokes if _nop_count = 0.
5003 nops(fxNop);
5004 %}
5006 //----------RESOURCES----------------------------------------------------------
5007 // Resources are the functional units available to the machine
5008 resources(
5009 PPC_BR, // branch unit
5010 PPC_CR, // condition unit
5011 PPC_FX1, // integer arithmetic unit 1
5012 PPC_FX2, // integer arithmetic unit 2
5013 PPC_LDST1, // load/store unit 1
5014 PPC_LDST2, // load/store unit 2
5015 PPC_FP1, // float arithmetic unit 1
5016 PPC_FP2, // float arithmetic unit 2
5017 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5018 PPC_FX = PPC_FX1 | PPC_FX2,
5019 PPC_FP = PPC_FP1 | PPC_FP2
5020 );
5022 //----------PIPELINE DESCRIPTION-----------------------------------------------
5023 // Pipeline Description specifies the stages in the machine's pipeline
5024 pipe_desc(
5025 // Power4 longest pipeline path
5026 PPC_IF, // instruction fetch
5027 PPC_IC,
5028 //PPC_BP, // branch prediction
5029 PPC_D0, // decode
5030 PPC_D1, // decode
5031 PPC_D2, // decode
5032 PPC_D3, // decode
5033 PPC_Xfer1,
5034 PPC_GD, // group definition
5035 PPC_MP, // map
5036 PPC_ISS, // issue
5037 PPC_RF, // resource fetch
5038 PPC_EX1, // execute (all units)
5039 PPC_EX2, // execute (FP, LDST)
5040 PPC_EX3, // execute (FP, LDST)
5041 PPC_EX4, // execute (FP)
5042 PPC_EX5, // execute (FP)
5043 PPC_EX6, // execute (FP)
5044 PPC_WB, // write back
5045 PPC_Xfer2,
5046 PPC_CP
5047 );
5049 //----------PIPELINE CLASSES---------------------------------------------------
5050 // Pipeline Classes describe the stages in which input and output are
5051 // referenced by the hardware pipeline.
5053 // Simple pipeline classes.
5055 // Default pipeline class.
5056 pipe_class pipe_class_default() %{
5057 single_instruction;
5058 fixed_latency(2);
5059 %}
5061 // Pipeline class for empty instructions.
5062 pipe_class pipe_class_empty() %{
5063 single_instruction;
5064 fixed_latency(0);
5065 %}
5067 // Pipeline class for compares.
5068 pipe_class pipe_class_compare() %{
5069 single_instruction;
5070 fixed_latency(16);
5071 %}
5073 // Pipeline class for traps.
5074 pipe_class pipe_class_trap() %{
5075 single_instruction;
5076 fixed_latency(100);
5077 %}
5079 // Pipeline class for memory operations.
5080 pipe_class pipe_class_memory() %{
5081 single_instruction;
5082 fixed_latency(16);
5083 %}
5085 // Pipeline class for call.
5086 pipe_class pipe_class_call() %{
5087 single_instruction;
5088 fixed_latency(100);
5089 %}
5091 // Define the class for the Nop node.
5092 define %{
5093 MachNop = pipe_class_default;
5094 %}
5096 %}
5098 //----------INSTRUCTIONS-------------------------------------------------------
5100 // Naming of instructions:
5101 // opA_operB / opA_operB_operC:
5102 // Operation 'op' with one or two source operands 'oper'. Result
5103 // type is A, source operand types are B and C.
5104 // Iff A == B == C, B and C are left out.
5105 //
5106 // The instructions are ordered according to the following scheme:
5107 // - loads
5108 // - load constants
5109 // - prefetch
5110 // - store
5111 // - encode/decode
5112 // - membar
5113 // - conditional moves
5114 // - compare & swap
5115 // - arithmetic and logic operations
5116 // * int: Add, Sub, Mul, Div, Mod
5117 // * int: lShift, arShift, urShift, rot
5118 // * float: Add, Sub, Mul, Div
5119 // * and, or, xor ...
5120 // - register moves: float <-> int, reg <-> stack, repl
5121 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5122 // - conv (low level type cast requiring bit changes (sign extend etc)
5123 // - compares, range & zero checks.
5124 // - branches
5125 // - complex operations, intrinsics, min, max, replicate
5126 // - lock
5127 // - Calls
5128 //
5129 // If there are similar instructions with different types they are sorted:
5130 // int before float
5131 // small before big
5132 // signed before unsigned
5133 // e.g., loadS before loadUS before loadI before loadF.
5136 //----------Load/Store Instructions--------------------------------------------
5138 //----------Load Instructions--------------------------------------------------
5140 // Converts byte to int.
5141 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5142 // reuses the 'amount' operand, but adlc expects that operand specification
5143 // and operands in match rule are equivalent.
5144 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5145 effect(DEF dst, USE src);
5146 format %{ "EXTSB $dst, $src \t// byte->int" %}
5147 size(4);
5148 ins_encode %{
5149 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5150 __ extsb($dst$$Register, $src$$Register);
5151 %}
5152 ins_pipe(pipe_class_default);
5153 %}
5155 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5156 // match-rule, false predicate
5157 match(Set dst (LoadB mem));
5158 predicate(false);
5160 format %{ "LBZ $dst, $mem" %}
5161 size(4);
5162 ins_encode( enc_lbz(dst, mem) );
5163 ins_pipe(pipe_class_memory);
5164 %}
5166 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5167 // match-rule, false predicate
5168 match(Set dst (LoadB mem));
5169 predicate(false);
5171 format %{ "LBZ $dst, $mem\n\t"
5172 "TWI $dst\n\t"
5173 "ISYNC" %}
5174 size(12);
5175 ins_encode( enc_lbz_ac(dst, mem) );
5176 ins_pipe(pipe_class_memory);
5177 %}
5179 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5180 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5181 match(Set dst (LoadB mem));
5182 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5183 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5184 expand %{
5185 iRegIdst tmp;
5186 loadUB_indirect(tmp, mem);
5187 convB2I_reg_2(dst, tmp);
5188 %}
5189 %}
5191 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5192 match(Set dst (LoadB mem));
5193 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5194 expand %{
5195 iRegIdst tmp;
5196 loadUB_indirect_ac(tmp, mem);
5197 convB2I_reg_2(dst, tmp);
5198 %}
5199 %}
5201 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5202 // match-rule, false predicate
5203 match(Set dst (LoadB mem));
5204 predicate(false);
5206 format %{ "LBZ $dst, $mem" %}
5207 size(4);
5208 ins_encode( enc_lbz(dst, mem) );
5209 ins_pipe(pipe_class_memory);
5210 %}
5212 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5213 // match-rule, false predicate
5214 match(Set dst (LoadB mem));
5215 predicate(false);
5217 format %{ "LBZ $dst, $mem\n\t"
5218 "TWI $dst\n\t"
5219 "ISYNC" %}
5220 size(12);
5221 ins_encode( enc_lbz_ac(dst, mem) );
5222 ins_pipe(pipe_class_memory);
5223 %}
5225 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5226 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5227 match(Set dst (LoadB mem));
5228 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5229 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5231 expand %{
5232 iRegIdst tmp;
5233 loadUB_indOffset16(tmp, mem);
5234 convB2I_reg_2(dst, tmp);
5235 %}
5236 %}
5238 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5239 match(Set dst (LoadB mem));
5240 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5242 expand %{
5243 iRegIdst tmp;
5244 loadUB_indOffset16_ac(tmp, mem);
5245 convB2I_reg_2(dst, tmp);
5246 %}
5247 %}
5249 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5250 instruct loadUB(iRegIdst dst, memory mem) %{
5251 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5252 match(Set dst (LoadUB mem));
5253 ins_cost(MEMORY_REF_COST);
5255 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5256 size(4);
5257 ins_encode( enc_lbz(dst, mem) );
5258 ins_pipe(pipe_class_memory);
5259 %}
5261 // Load Unsigned Byte (8bit UNsigned) acquire.
5262 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5263 match(Set dst (LoadUB mem));
5264 ins_cost(3*MEMORY_REF_COST);
5266 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5267 "TWI $dst\n\t"
5268 "ISYNC" %}
5269 size(12);
5270 ins_encode( enc_lbz_ac(dst, mem) );
5271 ins_pipe(pipe_class_memory);
5272 %}
5274 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5275 instruct loadUB2L(iRegLdst dst, memory mem) %{
5276 match(Set dst (ConvI2L (LoadUB mem)));
5277 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5278 ins_cost(MEMORY_REF_COST);
5280 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5281 size(4);
5282 ins_encode( enc_lbz(dst, mem) );
5283 ins_pipe(pipe_class_memory);
5284 %}
5286 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5287 match(Set dst (ConvI2L (LoadUB mem)));
5288 ins_cost(3*MEMORY_REF_COST);
5290 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5291 "TWI $dst\n\t"
5292 "ISYNC" %}
5293 size(12);
5294 ins_encode( enc_lbz_ac(dst, mem) );
5295 ins_pipe(pipe_class_memory);
5296 %}
5298 // Load Short (16bit signed)
5299 instruct loadS(iRegIdst dst, memory mem) %{
5300 match(Set dst (LoadS mem));
5301 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5302 ins_cost(MEMORY_REF_COST);
5304 format %{ "LHA $dst, $mem" %}
5305 size(4);
5306 ins_encode %{
5307 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5308 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5309 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5310 %}
5311 ins_pipe(pipe_class_memory);
5312 %}
5314 // Load Short (16bit signed) acquire.
5315 instruct loadS_ac(iRegIdst dst, memory mem) %{
5316 match(Set dst (LoadS mem));
5317 ins_cost(3*MEMORY_REF_COST);
5319 format %{ "LHA $dst, $mem\t acquire\n\t"
5320 "TWI $dst\n\t"
5321 "ISYNC" %}
5322 size(12);
5323 ins_encode %{
5324 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5325 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5326 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5327 __ twi_0($dst$$Register);
5328 __ isync();
5329 %}
5330 ins_pipe(pipe_class_memory);
5331 %}
5333 // Load Char (16bit unsigned)
5334 instruct loadUS(iRegIdst dst, memory mem) %{
5335 match(Set dst (LoadUS mem));
5336 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5337 ins_cost(MEMORY_REF_COST);
5339 format %{ "LHZ $dst, $mem" %}
5340 size(4);
5341 ins_encode( enc_lhz(dst, mem) );
5342 ins_pipe(pipe_class_memory);
5343 %}
5345 // Load Char (16bit unsigned) acquire.
5346 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5347 match(Set dst (LoadUS mem));
5348 ins_cost(3*MEMORY_REF_COST);
5350 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5351 "TWI $dst\n\t"
5352 "ISYNC" %}
5353 size(12);
5354 ins_encode( enc_lhz_ac(dst, mem) );
5355 ins_pipe(pipe_class_memory);
5356 %}
5358 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5359 instruct loadUS2L(iRegLdst dst, memory mem) %{
5360 match(Set dst (ConvI2L (LoadUS mem)));
5361 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5362 ins_cost(MEMORY_REF_COST);
5364 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5365 size(4);
5366 ins_encode( enc_lhz(dst, mem) );
5367 ins_pipe(pipe_class_memory);
5368 %}
5370 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5371 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5372 match(Set dst (ConvI2L (LoadUS mem)));
5373 ins_cost(3*MEMORY_REF_COST);
5375 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5376 "TWI $dst\n\t"
5377 "ISYNC" %}
5378 size(12);
5379 ins_encode( enc_lhz_ac(dst, mem) );
5380 ins_pipe(pipe_class_memory);
5381 %}
5383 // Load Integer.
5384 instruct loadI(iRegIdst dst, memory mem) %{
5385 match(Set dst (LoadI mem));
5386 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5387 ins_cost(MEMORY_REF_COST);
5389 format %{ "LWZ $dst, $mem" %}
5390 size(4);
5391 ins_encode( enc_lwz(dst, mem) );
5392 ins_pipe(pipe_class_memory);
5393 %}
5395 // Load Integer acquire.
5396 instruct loadI_ac(iRegIdst dst, memory mem) %{
5397 match(Set dst (LoadI mem));
5398 ins_cost(3*MEMORY_REF_COST);
5400 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5401 "TWI $dst\n\t"
5402 "ISYNC" %}
5403 size(12);
5404 ins_encode( enc_lwz_ac(dst, mem) );
5405 ins_pipe(pipe_class_memory);
5406 %}
5408 // Match loading integer and casting it to unsigned int in
5409 // long register.
5410 // LoadI + ConvI2L + AndL 0xffffffff.
5411 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5412 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5413 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5414 ins_cost(MEMORY_REF_COST);
5416 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5417 size(4);
5418 ins_encode( enc_lwz(dst, mem) );
5419 ins_pipe(pipe_class_memory);
5420 %}
5422 // Match loading integer and casting it to long.
5423 instruct loadI2L(iRegLdst dst, memory mem) %{
5424 match(Set dst (ConvI2L (LoadI mem)));
5425 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5426 ins_cost(MEMORY_REF_COST);
5428 format %{ "LWA $dst, $mem \t// loadI2L" %}
5429 size(4);
5430 ins_encode %{
5431 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5432 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5433 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5434 %}
5435 ins_pipe(pipe_class_memory);
5436 %}
5438 // Match loading integer and casting it to long - acquire.
5439 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5440 match(Set dst (ConvI2L (LoadI mem)));
5441 ins_cost(3*MEMORY_REF_COST);
5443 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5444 "TWI $dst\n\t"
5445 "ISYNC" %}
5446 size(12);
5447 ins_encode %{
5448 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5449 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5450 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5451 __ twi_0($dst$$Register);
5452 __ isync();
5453 %}
5454 ins_pipe(pipe_class_memory);
5455 %}
5457 // Load Long - aligned
5458 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5459 match(Set dst (LoadL mem));
5460 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5461 ins_cost(MEMORY_REF_COST);
5463 format %{ "LD $dst, $mem \t// long" %}
5464 size(4);
5465 ins_encode( enc_ld(dst, mem) );
5466 ins_pipe(pipe_class_memory);
5467 %}
5469 // Load Long - aligned acquire.
5470 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5471 match(Set dst (LoadL mem));
5472 ins_cost(3*MEMORY_REF_COST);
5474 format %{ "LD $dst, $mem \t// long acquire\n\t"
5475 "TWI $dst\n\t"
5476 "ISYNC" %}
5477 size(12);
5478 ins_encode( enc_ld_ac(dst, mem) );
5479 ins_pipe(pipe_class_memory);
5480 %}
5482 // Load Long - UNaligned
5483 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5484 match(Set dst (LoadL_unaligned mem));
5485 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5486 ins_cost(MEMORY_REF_COST);
5488 format %{ "LD $dst, $mem \t// unaligned long" %}
5489 size(4);
5490 ins_encode( enc_ld(dst, mem) );
5491 ins_pipe(pipe_class_memory);
5492 %}
5494 // Load nodes for superwords
5496 // Load Aligned Packed Byte
5497 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5498 predicate(n->as_LoadVector()->memory_size() == 8);
5499 match(Set dst (LoadVector mem));
5500 ins_cost(MEMORY_REF_COST);
5502 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5503 size(4);
5504 ins_encode( enc_ld(dst, mem) );
5505 ins_pipe(pipe_class_memory);
5506 %}
5508 // Load Range, range = array length (=jint)
5509 instruct loadRange(iRegIdst dst, memory mem) %{
5510 match(Set dst (LoadRange mem));
5511 ins_cost(MEMORY_REF_COST);
5513 format %{ "LWZ $dst, $mem \t// range" %}
5514 size(4);
5515 ins_encode( enc_lwz(dst, mem) );
5516 ins_pipe(pipe_class_memory);
5517 %}
5519 // Load Compressed Pointer
5520 instruct loadN(iRegNdst dst, memory mem) %{
5521 match(Set dst (LoadN mem));
5522 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5523 ins_cost(MEMORY_REF_COST);
5525 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5526 size(4);
5527 ins_encode( enc_lwz(dst, mem) );
5528 ins_pipe(pipe_class_memory);
5529 %}
5531 // Load Compressed Pointer acquire.
5532 instruct loadN_ac(iRegNdst dst, memory mem) %{
5533 match(Set dst (LoadN mem));
5534 ins_cost(3*MEMORY_REF_COST);
5536 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5537 "TWI $dst\n\t"
5538 "ISYNC" %}
5539 size(12);
5540 ins_encode( enc_lwz_ac(dst, mem) );
5541 ins_pipe(pipe_class_memory);
5542 %}
5544 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5545 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5546 match(Set dst (DecodeN (LoadN mem)));
5547 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5548 ins_cost(MEMORY_REF_COST);
5550 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5551 size(4);
5552 ins_encode( enc_lwz(dst, mem) );
5553 ins_pipe(pipe_class_memory);
5554 %}
5556 // Load Pointer
5557 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5558 match(Set dst (LoadP mem));
5559 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5560 ins_cost(MEMORY_REF_COST);
5562 format %{ "LD $dst, $mem \t// ptr" %}
5563 size(4);
5564 ins_encode( enc_ld(dst, mem) );
5565 ins_pipe(pipe_class_memory);
5566 %}
5568 // Load Pointer acquire.
5569 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5570 match(Set dst (LoadP mem));
5571 ins_cost(3*MEMORY_REF_COST);
5573 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5574 "TWI $dst\n\t"
5575 "ISYNC" %}
5576 size(12);
5577 ins_encode( enc_ld_ac(dst, mem) );
5578 ins_pipe(pipe_class_memory);
5579 %}
5581 // LoadP + CastP2L
5582 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5583 match(Set dst (CastP2X (LoadP mem)));
5584 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5585 ins_cost(MEMORY_REF_COST);
5587 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5588 size(4);
5589 ins_encode( enc_ld(dst, mem) );
5590 ins_pipe(pipe_class_memory);
5591 %}
5593 // Load compressed klass pointer.
5594 instruct loadNKlass(iRegNdst dst, memory mem) %{
5595 match(Set dst (LoadNKlass mem));
5596 ins_cost(MEMORY_REF_COST);
5598 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5599 size(4);
5600 ins_encode( enc_lwz(dst, mem) );
5601 ins_pipe(pipe_class_memory);
5602 %}
5604 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5605 //// TODO: will narrow_klass_shift ever be 0?
5606 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5607 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5608 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5609 // ins_cost(MEMORY_REF_COST);
5610 //
5611 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5612 // size(4);
5613 // ins_encode( enc_lwz(dst, mem) );
5614 // ins_pipe(pipe_class_memory);
5615 //%}
5617 // Load Klass Pointer
5618 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5619 match(Set dst (LoadKlass mem));
5620 ins_cost(MEMORY_REF_COST);
5622 format %{ "LD $dst, $mem \t// klass ptr" %}
5623 size(4);
5624 ins_encode( enc_ld(dst, mem) );
5625 ins_pipe(pipe_class_memory);
5626 %}
5628 // Load Float
5629 instruct loadF(regF dst, memory mem) %{
5630 match(Set dst (LoadF mem));
5631 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5632 ins_cost(MEMORY_REF_COST);
5634 format %{ "LFS $dst, $mem" %}
5635 size(4);
5636 ins_encode %{
5637 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5638 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5639 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5640 %}
5641 ins_pipe(pipe_class_memory);
5642 %}
5644 // Load Float acquire.
5645 instruct loadF_ac(regF dst, memory mem) %{
5646 match(Set dst (LoadF mem));
5647 ins_cost(3*MEMORY_REF_COST);
5649 format %{ "LFS $dst, $mem \t// acquire\n\t"
5650 "FCMPU cr0, $dst, $dst\n\t"
5651 "BNE cr0, next\n"
5652 "next:\n\t"
5653 "ISYNC" %}
5654 size(16);
5655 ins_encode %{
5656 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5657 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5658 Label next;
5659 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5660 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5661 __ bne(CCR0, next);
5662 __ bind(next);
5663 __ isync();
5664 %}
5665 ins_pipe(pipe_class_memory);
5666 %}
5668 // Load Double - aligned
5669 instruct loadD(regD dst, memory mem) %{
5670 match(Set dst (LoadD mem));
5671 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5672 ins_cost(MEMORY_REF_COST);
5674 format %{ "LFD $dst, $mem" %}
5675 size(4);
5676 ins_encode( enc_lfd(dst, mem) );
5677 ins_pipe(pipe_class_memory);
5678 %}
5680 // Load Double - aligned acquire.
5681 instruct loadD_ac(regD dst, memory mem) %{
5682 match(Set dst (LoadD mem));
5683 ins_cost(3*MEMORY_REF_COST);
5685 format %{ "LFD $dst, $mem \t// acquire\n\t"
5686 "FCMPU cr0, $dst, $dst\n\t"
5687 "BNE cr0, next\n"
5688 "next:\n\t"
5689 "ISYNC" %}
5690 size(16);
5691 ins_encode %{
5692 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5693 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5694 Label next;
5695 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5696 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5697 __ bne(CCR0, next);
5698 __ bind(next);
5699 __ isync();
5700 %}
5701 ins_pipe(pipe_class_memory);
5702 %}
5704 // Load Double - UNaligned
5705 instruct loadD_unaligned(regD dst, memory mem) %{
5706 match(Set dst (LoadD_unaligned mem));
5707 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5708 ins_cost(MEMORY_REF_COST);
5710 format %{ "LFD $dst, $mem" %}
5711 size(4);
5712 ins_encode( enc_lfd(dst, mem) );
5713 ins_pipe(pipe_class_memory);
5714 %}
5716 //----------Constants--------------------------------------------------------
5718 // Load MachConstantTableBase: add hi offset to global toc.
5719 // TODO: Handle hidden register r29 in bundler!
5720 instruct loadToc_hi(iRegLdst dst) %{
5721 effect(DEF dst);
5722 ins_cost(DEFAULT_COST);
5724 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5725 size(4);
5726 ins_encode %{
5727 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5728 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5729 %}
5730 ins_pipe(pipe_class_default);
5731 %}
5733 // Load MachConstantTableBase: add lo offset to global toc.
5734 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5735 effect(DEF dst, USE src);
5736 ins_cost(DEFAULT_COST);
5738 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5739 size(4);
5740 ins_encode %{
5741 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5742 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5743 %}
5744 ins_pipe(pipe_class_default);
5745 %}
5747 // Load 16-bit integer constant 0xssss????
5748 instruct loadConI16(iRegIdst dst, immI16 src) %{
5749 match(Set dst src);
5751 format %{ "LI $dst, $src" %}
5752 size(4);
5753 ins_encode %{
5754 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5755 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5756 %}
5757 ins_pipe(pipe_class_default);
5758 %}
5760 // Load integer constant 0x????0000
5761 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5762 match(Set dst src);
5763 ins_cost(DEFAULT_COST);
5765 format %{ "LIS $dst, $src.hi" %}
5766 size(4);
5767 ins_encode %{
5768 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5769 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5770 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5771 %}
5772 ins_pipe(pipe_class_default);
5773 %}
5775 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5776 // and sign extended), this adds the low 16 bits.
5777 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5778 // no match-rule, false predicate
5779 effect(DEF dst, USE src1, USE src2);
5780 predicate(false);
5782 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5783 size(4);
5784 ins_encode %{
5785 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5786 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5787 %}
5788 ins_pipe(pipe_class_default);
5789 %}
5791 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5792 match(Set dst src);
5793 ins_cost(DEFAULT_COST*2);
5795 expand %{
5796 // Would like to use $src$$constant.
5797 immI16 srcLo %{ _opnds[1]->constant() %}
5798 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5799 immIhi16 srcHi %{ _opnds[1]->constant() %}
5800 iRegIdst tmpI;
5801 loadConIhi16(tmpI, srcHi);
5802 loadConI32_lo16(dst, tmpI, srcLo);
5803 %}
5804 %}
5806 // No constant pool entries required.
5807 instruct loadConL16(iRegLdst dst, immL16 src) %{
5808 match(Set dst src);
5810 format %{ "LI $dst, $src \t// long" %}
5811 size(4);
5812 ins_encode %{
5813 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5814 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5815 %}
5816 ins_pipe(pipe_class_default);
5817 %}
5819 // Load long constant 0xssssssss????0000
5820 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5821 match(Set dst src);
5822 ins_cost(DEFAULT_COST);
5824 format %{ "LIS $dst, $src.hi \t// long" %}
5825 size(4);
5826 ins_encode %{
5827 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5828 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5829 %}
5830 ins_pipe(pipe_class_default);
5831 %}
5833 // To load a 32 bit constant: merge lower 16 bits into already loaded
5834 // high 16 bits.
5835 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5836 // no match-rule, false predicate
5837 effect(DEF dst, USE src1, USE src2);
5838 predicate(false);
5840 format %{ "ORI $dst, $src1, $src2.lo" %}
5841 size(4);
5842 ins_encode %{
5843 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5844 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5845 %}
5846 ins_pipe(pipe_class_default);
5847 %}
5849 // Load 32-bit long constant
5850 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5851 match(Set dst src);
5852 ins_cost(DEFAULT_COST*2);
5854 expand %{
5855 // Would like to use $src$$constant.
5856 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5857 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5858 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5859 iRegLdst tmpL;
5860 loadConL32hi16(tmpL, srcHi);
5861 loadConL32_lo16(dst, tmpL, srcLo);
5862 %}
5863 %}
5865 // Load long constant 0x????000000000000.
5866 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5867 match(Set dst src);
5868 ins_cost(DEFAULT_COST);
5870 expand %{
5871 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5872 immI shift32 %{ 32 %}
5873 iRegLdst tmpL;
5874 loadConL32hi16(tmpL, srcHi);
5875 lshiftL_regL_immI(dst, tmpL, shift32);
5876 %}
5877 %}
5879 // Expand node for constant pool load: small offset.
5880 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5881 effect(DEF dst, USE src, USE toc);
5882 ins_cost(MEMORY_REF_COST);
5884 ins_num_consts(1);
5885 // Needed so that CallDynamicJavaDirect can compute the address of this
5886 // instruction for relocation.
5887 ins_field_cbuf_insts_offset(int);
5889 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5890 size(4);
5891 ins_encode( enc_load_long_constL(dst, src, toc) );
5892 ins_pipe(pipe_class_memory);
5893 %}
5895 // Expand node for constant pool load: large offset.
5896 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5897 effect(DEF dst, USE src, USE toc);
5898 predicate(false);
5900 ins_num_consts(1);
5901 ins_field_const_toc_offset(int);
5902 // Needed so that CallDynamicJavaDirect can compute the address of this
5903 // instruction for relocation.
5904 ins_field_cbuf_insts_offset(int);
5906 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5907 size(4);
5908 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5909 ins_pipe(pipe_class_default);
5910 %}
5912 // Expand node for constant pool load: large offset.
5913 // No constant pool entries required.
5914 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5915 effect(DEF dst, USE src, USE base);
5916 predicate(false);
5918 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5920 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5921 size(4);
5922 ins_encode %{
5923 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5924 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5925 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5926 %}
5927 ins_pipe(pipe_class_memory);
5928 %}
5930 // Load long constant from constant table. Expand in case of
5931 // offset > 16 bit is needed.
5932 // Adlc adds toc node MachConstantTableBase.
5933 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5934 match(Set dst src);
5935 ins_cost(MEMORY_REF_COST);
5937 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5938 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5939 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5940 %}
5942 // Load NULL as compressed oop.
5943 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5944 match(Set dst src);
5945 ins_cost(DEFAULT_COST);
5947 format %{ "LI $dst, $src \t// compressed ptr" %}
5948 size(4);
5949 ins_encode %{
5950 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5951 __ li($dst$$Register, 0);
5952 %}
5953 ins_pipe(pipe_class_default);
5954 %}
5956 // Load hi part of compressed oop constant.
5957 instruct loadConN_hi(iRegNdst dst, immN src) %{
5958 effect(DEF dst, USE src);
5959 ins_cost(DEFAULT_COST);
5961 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5962 size(4);
5963 ins_encode %{
5964 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5965 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5966 %}
5967 ins_pipe(pipe_class_default);
5968 %}
5970 // Add lo part of compressed oop constant to already loaded hi part.
5971 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5972 effect(DEF dst, USE src1, USE src2);
5973 ins_cost(DEFAULT_COST);
5975 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5976 size(4);
5977 ins_encode %{
5978 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5979 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5980 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5981 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5982 __ relocate(rspec, 1);
5983 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5984 %}
5985 ins_pipe(pipe_class_default);
5986 %}
5988 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5989 // leaving the upper 32 bits with sign-extension bits.
5990 // This clears these bits: dst = src & 0xFFFFFFFF.
5991 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5992 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5993 effect(DEF dst, USE src);
5994 predicate(false);
5996 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5997 size(4);
5998 ins_encode %{
5999 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6000 __ clrldi($dst$$Register, $src$$Register, 0x20);
6001 %}
6002 ins_pipe(pipe_class_default);
6003 %}
6005 // Loading ConN must be postalloc expanded so that edges between
6006 // the nodes are safe. They may not interfere with a safepoint.
6007 // GL TODO: This needs three instructions: better put this into the constant pool.
6008 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6009 match(Set dst src);
6010 ins_cost(DEFAULT_COST*2);
6012 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6013 postalloc_expand %{
6014 MachNode *m1 = new (C) loadConN_hiNode();
6015 MachNode *m2 = new (C) loadConN_loNode();
6016 MachNode *m3 = new (C) clearMs32bNode();
6017 m1->add_req(NULL);
6018 m2->add_req(NULL, m1);
6019 m3->add_req(NULL, m2);
6020 m1->_opnds[0] = op_dst;
6021 m1->_opnds[1] = op_src;
6022 m2->_opnds[0] = op_dst;
6023 m2->_opnds[1] = op_dst;
6024 m2->_opnds[2] = op_src;
6025 m3->_opnds[0] = op_dst;
6026 m3->_opnds[1] = op_dst;
6027 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6028 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6029 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6030 nodes->push(m1);
6031 nodes->push(m2);
6032 nodes->push(m3);
6033 %}
6034 %}
6036 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6037 effect(DEF dst, USE src);
6038 ins_cost(DEFAULT_COST);
6040 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6041 size(4);
6042 ins_encode %{
6043 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6044 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6045 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6046 %}
6047 ins_pipe(pipe_class_default);
6048 %}
6050 // This needs a match rule so that build_oop_map knows this is
6051 // not a narrow oop.
6052 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6053 match(Set dst src1);
6054 effect(TEMP src2);
6055 ins_cost(DEFAULT_COST);
6057 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6058 size(4);
6059 ins_encode %{
6060 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6061 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6062 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6063 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6064 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6066 __ relocate(rspec, 1);
6067 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6068 %}
6069 ins_pipe(pipe_class_default);
6070 %}
6072 // Loading ConNKlass must be postalloc expanded so that edges between
6073 // the nodes are safe. They may not interfere with a safepoint.
6074 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6075 match(Set dst src);
6076 ins_cost(DEFAULT_COST*2);
6078 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6079 postalloc_expand %{
6080 // Load high bits into register. Sign extended.
6081 MachNode *m1 = new (C) loadConNKlass_hiNode();
6082 m1->add_req(NULL);
6083 m1->_opnds[0] = op_dst;
6084 m1->_opnds[1] = op_src;
6085 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6086 nodes->push(m1);
6088 MachNode *m2 = m1;
6089 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6090 // Value might be 1-extended. Mask out these bits.
6091 m2 = new (C) clearMs32bNode();
6092 m2->add_req(NULL, m1);
6093 m2->_opnds[0] = op_dst;
6094 m2->_opnds[1] = op_dst;
6095 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6096 nodes->push(m2);
6097 }
6099 MachNode *m3 = new (C) loadConNKlass_loNode();
6100 m3->add_req(NULL, m2);
6101 m3->_opnds[0] = op_dst;
6102 m3->_opnds[1] = op_src;
6103 m3->_opnds[2] = op_dst;
6104 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6105 nodes->push(m3);
6106 %}
6107 %}
6109 // 0x1 is used in object initialization (initial object header).
6110 // No constant pool entries required.
6111 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6112 match(Set dst src);
6114 format %{ "LI $dst, $src \t// ptr" %}
6115 size(4);
6116 ins_encode %{
6117 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6118 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6119 %}
6120 ins_pipe(pipe_class_default);
6121 %}
6123 // Expand node for constant pool load: small offset.
6124 // The match rule is needed to generate the correct bottom_type(),
6125 // however this node should never match. The use of predicate is not
6126 // possible since ADLC forbids predicates for chain rules. The higher
6127 // costs do not prevent matching in this case. For that reason the
6128 // operand immP_NM with predicate(false) is used.
6129 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6130 match(Set dst src);
6131 effect(TEMP toc);
6133 ins_num_consts(1);
6135 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6136 size(4);
6137 ins_encode( enc_load_long_constP(dst, src, toc) );
6138 ins_pipe(pipe_class_memory);
6139 %}
6141 // Expand node for constant pool load: large offset.
6142 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6143 effect(DEF dst, USE src, USE toc);
6144 predicate(false);
6146 ins_num_consts(1);
6147 ins_field_const_toc_offset(int);
6149 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6150 size(4);
6151 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6152 ins_pipe(pipe_class_default);
6153 %}
6155 // Expand node for constant pool load: large offset.
6156 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6157 match(Set dst src);
6158 effect(TEMP base);
6160 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6162 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6163 size(4);
6164 ins_encode %{
6165 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6166 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6167 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6168 %}
6169 ins_pipe(pipe_class_memory);
6170 %}
6172 // Load pointer constant from constant table. Expand in case an
6173 // offset > 16 bit is needed.
6174 // Adlc adds toc node MachConstantTableBase.
6175 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6176 match(Set dst src);
6177 ins_cost(MEMORY_REF_COST);
6179 // This rule does not use "expand" because then
6180 // the result type is not known to be an Oop. An ADLC
6181 // enhancement will be needed to make that work - not worth it!
6183 // If this instruction rematerializes, it prolongs the live range
6184 // of the toc node, causing illegal graphs.
6185 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6186 ins_cannot_rematerialize(true);
6188 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6189 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6190 %}
6192 // Expand node for constant pool load: small offset.
6193 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6194 effect(DEF dst, USE src, USE toc);
6195 ins_cost(MEMORY_REF_COST);
6197 ins_num_consts(1);
6199 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6200 size(4);
6201 ins_encode %{
6202 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6203 address float_address = __ float_constant($src$$constant);
6204 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6205 %}
6206 ins_pipe(pipe_class_memory);
6207 %}
6209 // Expand node for constant pool load: large offset.
6210 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6211 effect(DEF dst, USE src, USE toc);
6212 ins_cost(MEMORY_REF_COST);
6214 ins_num_consts(1);
6216 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6217 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6218 "ADDIS $toc, $toc, -offset_hi"%}
6219 size(12);
6220 ins_encode %{
6221 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6222 FloatRegister Rdst = $dst$$FloatRegister;
6223 Register Rtoc = $toc$$Register;
6224 address float_address = __ float_constant($src$$constant);
6225 int offset = __ offset_to_method_toc(float_address);
6226 int hi = (offset + (1<<15))>>16;
6227 int lo = offset - hi * (1<<16);
6229 __ addis(Rtoc, Rtoc, hi);
6230 __ lfs(Rdst, lo, Rtoc);
6231 __ addis(Rtoc, Rtoc, -hi);
6232 %}
6233 ins_pipe(pipe_class_memory);
6234 %}
6236 // Adlc adds toc node MachConstantTableBase.
6237 instruct loadConF_Ex(regF dst, immF src) %{
6238 match(Set dst src);
6239 ins_cost(MEMORY_REF_COST);
6241 // See loadConP.
6242 ins_cannot_rematerialize(true);
6244 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6245 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6246 %}
6248 // Expand node for constant pool load: small offset.
6249 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6250 effect(DEF dst, USE src, USE toc);
6251 ins_cost(MEMORY_REF_COST);
6253 ins_num_consts(1);
6255 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6256 size(4);
6257 ins_encode %{
6258 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6259 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6260 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6261 %}
6262 ins_pipe(pipe_class_memory);
6263 %}
6265 // Expand node for constant pool load: large offset.
6266 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6267 effect(DEF dst, USE src, USE toc);
6268 ins_cost(MEMORY_REF_COST);
6270 ins_num_consts(1);
6272 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6273 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6274 "ADDIS $toc, $toc, -offset_hi" %}
6275 size(12);
6276 ins_encode %{
6277 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6278 FloatRegister Rdst = $dst$$FloatRegister;
6279 Register Rtoc = $toc$$Register;
6280 address float_address = __ double_constant($src$$constant);
6281 int offset = __ offset_to_method_toc(float_address);
6282 int hi = (offset + (1<<15))>>16;
6283 int lo = offset - hi * (1<<16);
6285 __ addis(Rtoc, Rtoc, hi);
6286 __ lfd(Rdst, lo, Rtoc);
6287 __ addis(Rtoc, Rtoc, -hi);
6288 %}
6289 ins_pipe(pipe_class_memory);
6290 %}
6292 // Adlc adds toc node MachConstantTableBase.
6293 instruct loadConD_Ex(regD dst, immD src) %{
6294 match(Set dst src);
6295 ins_cost(MEMORY_REF_COST);
6297 // See loadConP.
6298 ins_cannot_rematerialize(true);
6300 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6301 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6302 %}
6304 // Prefetch instructions.
6305 // Must be safe to execute with invalid address (cannot fault).
6307 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6308 match(PrefetchRead (AddP mem src));
6309 ins_cost(MEMORY_REF_COST);
6311 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6312 size(4);
6313 ins_encode %{
6314 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6315 __ dcbt($src$$Register, $mem$$base$$Register);
6316 %}
6317 ins_pipe(pipe_class_memory);
6318 %}
6320 instruct prefetchr_no_offset(indirectMemory mem) %{
6321 match(PrefetchRead mem);
6322 ins_cost(MEMORY_REF_COST);
6324 format %{ "PREFETCH $mem" %}
6325 size(4);
6326 ins_encode %{
6327 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6328 __ dcbt($mem$$base$$Register);
6329 %}
6330 ins_pipe(pipe_class_memory);
6331 %}
6333 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6334 match(PrefetchWrite (AddP mem src));
6335 ins_cost(MEMORY_REF_COST);
6337 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6338 size(4);
6339 ins_encode %{
6340 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6341 __ dcbtst($src$$Register, $mem$$base$$Register);
6342 %}
6343 ins_pipe(pipe_class_memory);
6344 %}
6346 instruct prefetchw_no_offset(indirectMemory mem) %{
6347 match(PrefetchWrite mem);
6348 ins_cost(MEMORY_REF_COST);
6350 format %{ "PREFETCH $mem" %}
6351 size(4);
6352 ins_encode %{
6353 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6354 __ dcbtst($mem$$base$$Register);
6355 %}
6356 ins_pipe(pipe_class_memory);
6357 %}
6359 // Special prefetch versions which use the dcbz instruction.
6360 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6361 match(PrefetchAllocation (AddP mem src));
6362 predicate(AllocatePrefetchStyle == 3);
6363 ins_cost(MEMORY_REF_COST);
6365 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6366 size(4);
6367 ins_encode %{
6368 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6369 __ dcbz($src$$Register, $mem$$base$$Register);
6370 %}
6371 ins_pipe(pipe_class_memory);
6372 %}
6374 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6375 match(PrefetchAllocation mem);
6376 predicate(AllocatePrefetchStyle == 3);
6377 ins_cost(MEMORY_REF_COST);
6379 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6380 size(4);
6381 ins_encode %{
6382 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6383 __ dcbz($mem$$base$$Register);
6384 %}
6385 ins_pipe(pipe_class_memory);
6386 %}
6388 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6389 match(PrefetchAllocation (AddP mem src));
6390 predicate(AllocatePrefetchStyle != 3);
6391 ins_cost(MEMORY_REF_COST);
6393 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6394 size(4);
6395 ins_encode %{
6396 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6397 __ dcbtst($src$$Register, $mem$$base$$Register);
6398 %}
6399 ins_pipe(pipe_class_memory);
6400 %}
6402 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6403 match(PrefetchAllocation mem);
6404 predicate(AllocatePrefetchStyle != 3);
6405 ins_cost(MEMORY_REF_COST);
6407 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6408 size(4);
6409 ins_encode %{
6410 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6411 __ dcbtst($mem$$base$$Register);
6412 %}
6413 ins_pipe(pipe_class_memory);
6414 %}
6416 //----------Store Instructions-------------------------------------------------
6418 // Store Byte
6419 instruct storeB(memory mem, iRegIsrc src) %{
6420 match(Set mem (StoreB mem src));
6421 ins_cost(MEMORY_REF_COST);
6423 format %{ "STB $src, $mem \t// byte" %}
6424 size(4);
6425 ins_encode %{
6426 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6427 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6428 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6429 %}
6430 ins_pipe(pipe_class_memory);
6431 %}
6433 // Store Char/Short
6434 instruct storeC(memory mem, iRegIsrc src) %{
6435 match(Set mem (StoreC mem src));
6436 ins_cost(MEMORY_REF_COST);
6438 format %{ "STH $src, $mem \t// short" %}
6439 size(4);
6440 ins_encode %{
6441 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6442 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6443 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6444 %}
6445 ins_pipe(pipe_class_memory);
6446 %}
6448 // Store Integer
6449 instruct storeI(memory mem, iRegIsrc src) %{
6450 match(Set mem (StoreI mem src));
6451 ins_cost(MEMORY_REF_COST);
6453 format %{ "STW $src, $mem" %}
6454 size(4);
6455 ins_encode( enc_stw(src, mem) );
6456 ins_pipe(pipe_class_memory);
6457 %}
6459 // ConvL2I + StoreI.
6460 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6461 match(Set mem (StoreI mem (ConvL2I src)));
6462 ins_cost(MEMORY_REF_COST);
6464 format %{ "STW l2i($src), $mem" %}
6465 size(4);
6466 ins_encode( enc_stw(src, mem) );
6467 ins_pipe(pipe_class_memory);
6468 %}
6470 // Store Long
6471 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6472 match(Set mem (StoreL mem src));
6473 ins_cost(MEMORY_REF_COST);
6475 format %{ "STD $src, $mem \t// long" %}
6476 size(4);
6477 ins_encode( enc_std(src, mem) );
6478 ins_pipe(pipe_class_memory);
6479 %}
6481 // Store super word nodes.
6483 // Store Aligned Packed Byte long register to memory
6484 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6485 predicate(n->as_StoreVector()->memory_size() == 8);
6486 match(Set mem (StoreVector mem src));
6487 ins_cost(MEMORY_REF_COST);
6489 format %{ "STD $mem, $src \t// packed8B" %}
6490 size(4);
6491 ins_encode( enc_std(src, mem) );
6492 ins_pipe(pipe_class_memory);
6493 %}
6495 // Store Compressed Oop
6496 instruct storeN(memory dst, iRegN_P2N src) %{
6497 match(Set dst (StoreN dst src));
6498 ins_cost(MEMORY_REF_COST);
6500 format %{ "STW $src, $dst \t// compressed oop" %}
6501 size(4);
6502 ins_encode( enc_stw(src, dst) );
6503 ins_pipe(pipe_class_memory);
6504 %}
6506 // Store Compressed KLass
6507 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6508 match(Set dst (StoreNKlass dst src));
6509 ins_cost(MEMORY_REF_COST);
6511 format %{ "STW $src, $dst \t// compressed klass" %}
6512 size(4);
6513 ins_encode( enc_stw(src, dst) );
6514 ins_pipe(pipe_class_memory);
6515 %}
6517 // Store Pointer
6518 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6519 match(Set dst (StoreP dst src));
6520 ins_cost(MEMORY_REF_COST);
6522 format %{ "STD $src, $dst \t// ptr" %}
6523 size(4);
6524 ins_encode( enc_std(src, dst) );
6525 ins_pipe(pipe_class_memory);
6526 %}
6528 // Store Float
6529 instruct storeF(memory mem, regF src) %{
6530 match(Set mem (StoreF mem src));
6531 ins_cost(MEMORY_REF_COST);
6533 format %{ "STFS $src, $mem" %}
6534 size(4);
6535 ins_encode( enc_stfs(src, mem) );
6536 ins_pipe(pipe_class_memory);
6537 %}
6539 // Store Double
6540 instruct storeD(memory mem, regD src) %{
6541 match(Set mem (StoreD mem src));
6542 ins_cost(MEMORY_REF_COST);
6544 format %{ "STFD $src, $mem" %}
6545 size(4);
6546 ins_encode( enc_stfd(src, mem) );
6547 ins_pipe(pipe_class_memory);
6548 %}
6550 //----------Store Instructions With Zeros--------------------------------------
6552 // Card-mark for CMS garbage collection.
6553 // This cardmark does an optimization so that it must not always
6554 // do a releasing store. For this, it gets the address of
6555 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6556 // (Using releaseFieldAddr in the match rule is a hack.)
6557 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6558 match(Set mem (StoreCM mem releaseFieldAddr));
6559 predicate(false);
6560 ins_cost(MEMORY_REF_COST);
6562 // See loadConP.
6563 ins_cannot_rematerialize(true);
6565 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6566 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6567 ins_pipe(pipe_class_memory);
6568 %}
6570 // Card-mark for CMS garbage collection.
6571 // This cardmark does an optimization so that it must not always
6572 // do a releasing store. For this, it needs the constant address of
6573 // CMSCollectorCardTableModRefBSExt::_requires_release.
6574 // This constant address is split off here by expand so we can use
6575 // adlc / matcher functionality to load it from the constant section.
6576 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6577 match(Set mem (StoreCM mem zero));
6578 predicate(UseConcMarkSweepGC);
6580 expand %{
6581 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6582 iRegLdst releaseFieldAddress;
6583 loadConL_Ex(releaseFieldAddress, baseImm);
6584 storeCM_CMS(mem, releaseFieldAddress);
6585 %}
6586 %}
6588 instruct storeCM_G1(memory mem, immI_0 zero) %{
6589 match(Set mem (StoreCM mem zero));
6590 predicate(UseG1GC);
6591 ins_cost(MEMORY_REF_COST);
6593 ins_cannot_rematerialize(true);
6595 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6596 size(8);
6597 ins_encode %{
6598 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6599 __ li(R0, 0);
6600 //__ release(); // G1: oops are allowed to get visible after dirty marking
6601 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6602 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6603 %}
6604 ins_pipe(pipe_class_memory);
6605 %}
6607 // Convert oop pointer into compressed form.
6609 // Nodes for postalloc expand.
6611 // Shift node for expand.
6612 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6613 // The match rule is needed to make it a 'MachTypeNode'!
6614 match(Set dst (EncodeP src));
6615 predicate(false);
6617 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6618 size(4);
6619 ins_encode %{
6620 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6621 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6622 %}
6623 ins_pipe(pipe_class_default);
6624 %}
6626 // Add node for expand.
6627 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6628 // The match rule is needed to make it a 'MachTypeNode'!
6629 match(Set dst (EncodeP src));
6630 predicate(false);
6632 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6633 size(4);
6634 ins_encode %{
6635 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6636 __ subf($dst$$Register, R30, $src$$Register);
6637 %}
6638 ins_pipe(pipe_class_default);
6639 %}
6641 // Conditional sub base.
6642 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6643 // The match rule is needed to make it a 'MachTypeNode'!
6644 match(Set dst (EncodeP (Binary crx src1)));
6645 predicate(false);
6647 ins_variable_size_depending_on_alignment(true);
6649 format %{ "BEQ $crx, done\n\t"
6650 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6651 "done:" %}
6652 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6653 ins_encode %{
6654 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6655 Label done;
6656 __ beq($crx$$CondRegister, done);
6657 __ subf($dst$$Register, R30, $src1$$Register);
6658 // TODO PPC port __ endgroup_if_needed(_size == 12);
6659 __ bind(done);
6660 %}
6661 ins_pipe(pipe_class_default);
6662 %}
6664 // Power 7 can use isel instruction
6665 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6666 // The match rule is needed to make it a 'MachTypeNode'!
6667 match(Set dst (EncodeP (Binary crx src1)));
6668 predicate(false);
6670 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6671 size(4);
6672 ins_encode %{
6673 // This is a Power7 instruction for which no machine description exists.
6674 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6675 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6676 %}
6677 ins_pipe(pipe_class_default);
6678 %}
6680 // base != 0
6681 // 32G aligned narrow oop base.
6682 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6683 match(Set dst (EncodeP src));
6684 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6686 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6687 size(4);
6688 ins_encode %{
6689 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6690 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6691 %}
6692 ins_pipe(pipe_class_default);
6693 %}
6695 // shift != 0, base != 0
6696 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6697 match(Set dst (EncodeP src));
6698 effect(TEMP crx);
6699 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6700 Universe::narrow_oop_shift() != 0 &&
6701 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6703 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6704 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6705 %}
6707 // shift != 0, base != 0
6708 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6709 match(Set dst (EncodeP src));
6710 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6711 Universe::narrow_oop_shift() != 0 &&
6712 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6714 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6715 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6716 %}
6718 // shift != 0, base == 0
6719 // TODO: This is the same as encodeP_shift. Merge!
6720 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6721 match(Set dst (EncodeP src));
6722 predicate(Universe::narrow_oop_shift() != 0 &&
6723 Universe::narrow_oop_base() ==0);
6725 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6726 size(4);
6727 ins_encode %{
6728 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6729 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6730 %}
6731 ins_pipe(pipe_class_default);
6732 %}
6734 // Compressed OOPs with narrow_oop_shift == 0.
6735 // shift == 0, base == 0
6736 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6737 match(Set dst (EncodeP src));
6738 predicate(Universe::narrow_oop_shift() == 0);
6740 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6741 // variable size, 0 or 4.
6742 ins_encode %{
6743 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6744 __ mr_if_needed($dst$$Register, $src$$Register);
6745 %}
6746 ins_pipe(pipe_class_default);
6747 %}
6749 // Decode nodes.
6751 // Shift node for expand.
6752 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6753 // The match rule is needed to make it a 'MachTypeNode'!
6754 match(Set dst (DecodeN src));
6755 predicate(false);
6757 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6758 size(4);
6759 ins_encode %{
6760 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6761 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6762 %}
6763 ins_pipe(pipe_class_default);
6764 %}
6766 // Add node for expand.
6767 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6768 // The match rule is needed to make it a 'MachTypeNode'!
6769 match(Set dst (DecodeN src));
6770 predicate(false);
6772 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6773 size(4);
6774 ins_encode %{
6775 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6776 __ add($dst$$Register, $src$$Register, R30);
6777 %}
6778 ins_pipe(pipe_class_default);
6779 %}
6781 // conditianal add base for expand
6782 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6783 // The match rule is needed to make it a 'MachTypeNode'!
6784 // NOTICE that the rule is nonsense - we just have to make sure that:
6785 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6786 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6787 match(Set dst (DecodeN (Binary crx src1)));
6788 predicate(false);
6790 ins_variable_size_depending_on_alignment(true);
6792 format %{ "BEQ $crx, done\n\t"
6793 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6794 "done:" %}
6795 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6796 ins_encode %{
6797 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6798 Label done;
6799 __ beq($crx$$CondRegister, done);
6800 __ add($dst$$Register, $src1$$Register, R30);
6801 // TODO PPC port __ endgroup_if_needed(_size == 12);
6802 __ bind(done);
6803 %}
6804 ins_pipe(pipe_class_default);
6805 %}
6807 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6808 // The match rule is needed to make it a 'MachTypeNode'!
6809 // NOTICE that the rule is nonsense - we just have to make sure that:
6810 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6811 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6812 match(Set dst (DecodeN (Binary crx src1)));
6813 predicate(false);
6815 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6816 size(4);
6817 ins_encode %{
6818 // This is a Power7 instruction for which no machine description exists.
6819 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6820 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6821 %}
6822 ins_pipe(pipe_class_default);
6823 %}
6825 // shift != 0, base != 0
6826 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6827 match(Set dst (DecodeN src));
6828 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6829 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6830 Universe::narrow_oop_shift() != 0 &&
6831 Universe::narrow_oop_base() != 0);
6832 effect(TEMP crx);
6834 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6835 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6836 %}
6838 // shift != 0, base == 0
6839 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6840 match(Set dst (DecodeN src));
6841 predicate(Universe::narrow_oop_shift() != 0 &&
6842 Universe::narrow_oop_base() == 0);
6844 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6845 size(4);
6846 ins_encode %{
6847 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6848 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6849 %}
6850 ins_pipe(pipe_class_default);
6851 %}
6853 // src != 0, shift != 0, base != 0
6854 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6855 match(Set dst (DecodeN src));
6856 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6857 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6858 Universe::narrow_oop_shift() != 0 &&
6859 Universe::narrow_oop_base() != 0);
6861 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6862 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6863 %}
6865 // Compressed OOPs with narrow_oop_shift == 0.
6866 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6867 match(Set dst (DecodeN src));
6868 predicate(Universe::narrow_oop_shift() == 0);
6869 ins_cost(DEFAULT_COST);
6871 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6872 // variable size, 0 or 4.
6873 ins_encode %{
6874 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6875 __ mr_if_needed($dst$$Register, $src$$Register);
6876 %}
6877 ins_pipe(pipe_class_default);
6878 %}
6880 // Convert compressed oop into int for vectors alignment masking.
6881 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6882 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6883 predicate(Universe::narrow_oop_shift() == 0);
6884 ins_cost(DEFAULT_COST);
6886 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6887 // variable size, 0 or 4.
6888 ins_encode %{
6889 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6890 __ mr_if_needed($dst$$Register, $src$$Register);
6891 %}
6892 ins_pipe(pipe_class_default);
6893 %}
6895 // Convert klass pointer into compressed form.
6897 // Nodes for postalloc expand.
6899 // Shift node for expand.
6900 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6901 // The match rule is needed to make it a 'MachTypeNode'!
6902 match(Set dst (EncodePKlass src));
6903 predicate(false);
6905 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6906 size(4);
6907 ins_encode %{
6908 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6909 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6910 %}
6911 ins_pipe(pipe_class_default);
6912 %}
6914 // Add node for expand.
6915 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6916 // The match rule is needed to make it a 'MachTypeNode'!
6917 match(Set dst (EncodePKlass (Binary base src)));
6918 predicate(false);
6920 format %{ "SUB $dst, $base, $src \t// encode" %}
6921 size(4);
6922 ins_encode %{
6923 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6924 __ subf($dst$$Register, $base$$Register, $src$$Register);
6925 %}
6926 ins_pipe(pipe_class_default);
6927 %}
6929 // base != 0
6930 // 32G aligned narrow oop base.
6931 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6932 match(Set dst (EncodePKlass src));
6933 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6935 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6936 size(4);
6937 ins_encode %{
6938 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6939 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6940 %}
6941 ins_pipe(pipe_class_default);
6942 %}
6944 // shift != 0, base != 0
6945 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6946 match(Set dst (EncodePKlass (Binary base src)));
6947 predicate(false);
6949 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6950 postalloc_expand %{
6951 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6952 n1->add_req(n_region, n_base, n_src);
6953 n1->_opnds[0] = op_dst;
6954 n1->_opnds[1] = op_base;
6955 n1->_opnds[2] = op_src;
6956 n1->_bottom_type = _bottom_type;
6958 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6959 n2->add_req(n_region, n1);
6960 n2->_opnds[0] = op_dst;
6961 n2->_opnds[1] = op_dst;
6962 n2->_bottom_type = _bottom_type;
6963 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6964 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6966 nodes->push(n1);
6967 nodes->push(n2);
6968 %}
6969 %}
6971 // shift != 0, base != 0
6972 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6973 match(Set dst (EncodePKlass src));
6974 //predicate(Universe::narrow_klass_shift() != 0 &&
6975 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6977 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6978 ins_cost(DEFAULT_COST*2); // Don't count constant.
6979 expand %{
6980 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6981 iRegLdst base;
6982 loadConL_Ex(base, baseImm);
6983 encodePKlass_not_null_Ex(dst, base, src);
6984 %}
6985 %}
6987 // Decode nodes.
6989 // Shift node for expand.
6990 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6991 // The match rule is needed to make it a 'MachTypeNode'!
6992 match(Set dst (DecodeNKlass src));
6993 predicate(false);
6995 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
6996 size(4);
6997 ins_encode %{
6998 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6999 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7000 %}
7001 ins_pipe(pipe_class_default);
7002 %}
7004 // Add node for expand.
7006 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7007 // The match rule is needed to make it a 'MachTypeNode'!
7008 match(Set dst (DecodeNKlass (Binary base src)));
7009 predicate(false);
7011 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7012 size(4);
7013 ins_encode %{
7014 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7015 __ add($dst$$Register, $base$$Register, $src$$Register);
7016 %}
7017 ins_pipe(pipe_class_default);
7018 %}
7020 // src != 0, shift != 0, base != 0
7021 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7022 match(Set dst (DecodeNKlass (Binary base src)));
7023 //effect(kill src); // We need a register for the immediate result after shifting.
7024 predicate(false);
7026 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7027 postalloc_expand %{
7028 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7029 n1->add_req(n_region, n_base, n_src);
7030 n1->_opnds[0] = op_dst;
7031 n1->_opnds[1] = op_base;
7032 n1->_opnds[2] = op_src;
7033 n1->_bottom_type = _bottom_type;
7035 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7036 n2->add_req(n_region, n2);
7037 n2->_opnds[0] = op_dst;
7038 n2->_opnds[1] = op_dst;
7039 n2->_bottom_type = _bottom_type;
7041 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7042 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7044 nodes->push(n1);
7045 nodes->push(n2);
7046 %}
7047 %}
7049 // src != 0, shift != 0, base != 0
7050 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7051 match(Set dst (DecodeNKlass src));
7052 // predicate(Universe::narrow_klass_shift() != 0 &&
7053 // Universe::narrow_klass_base() != 0);
7055 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7057 ins_cost(DEFAULT_COST*2); // Don't count constant.
7058 expand %{
7059 // We add first, then we shift. Like this, we can get along with one register less.
7060 // But we have to load the base pre-shifted.
7061 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7062 iRegLdst base;
7063 loadConL_Ex(base, baseImm);
7064 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7065 %}
7066 %}
7068 //----------MemBar Instructions-----------------------------------------------
7069 // Memory barrier flavors
7071 instruct membar_acquire() %{
7072 match(LoadFence);
7073 ins_cost(4*MEMORY_REF_COST);
7075 format %{ "MEMBAR-acquire" %}
7076 size(4);
7077 ins_encode %{
7078 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7079 __ acquire();
7080 %}
7081 ins_pipe(pipe_class_default);
7082 %}
7084 instruct unnecessary_membar_acquire() %{
7085 match(MemBarAcquire);
7086 ins_cost(0);
7088 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7089 size(0);
7090 ins_encode( /*empty*/ );
7091 ins_pipe(pipe_class_default);
7092 %}
7094 instruct membar_acquire_lock() %{
7095 match(MemBarAcquireLock);
7096 ins_cost(0);
7098 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7099 size(0);
7100 ins_encode( /*empty*/ );
7101 ins_pipe(pipe_class_default);
7102 %}
7104 instruct membar_release() %{
7105 match(MemBarRelease);
7106 match(StoreFence);
7107 ins_cost(4*MEMORY_REF_COST);
7109 format %{ "MEMBAR-release" %}
7110 size(4);
7111 ins_encode %{
7112 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7113 __ release();
7114 %}
7115 ins_pipe(pipe_class_default);
7116 %}
7118 instruct membar_storestore() %{
7119 match(MemBarStoreStore);
7120 ins_cost(4*MEMORY_REF_COST);
7122 format %{ "MEMBAR-store-store" %}
7123 size(4);
7124 ins_encode %{
7125 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7126 __ membar(Assembler::StoreStore);
7127 %}
7128 ins_pipe(pipe_class_default);
7129 %}
7131 instruct membar_release_lock() %{
7132 match(MemBarReleaseLock);
7133 ins_cost(0);
7135 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7136 size(0);
7137 ins_encode( /*empty*/ );
7138 ins_pipe(pipe_class_default);
7139 %}
7141 instruct membar_volatile() %{
7142 match(MemBarVolatile);
7143 ins_cost(4*MEMORY_REF_COST);
7145 format %{ "MEMBAR-volatile" %}
7146 size(4);
7147 ins_encode %{
7148 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7149 __ fence();
7150 %}
7151 ins_pipe(pipe_class_default);
7152 %}
7154 // This optimization is wrong on PPC. The following pattern is not supported:
7155 // MemBarVolatile
7156 // ^ ^
7157 // | |
7158 // CtrlProj MemProj
7159 // ^ ^
7160 // | |
7161 // | Load
7162 // |
7163 // MemBarVolatile
7164 //
7165 // The first MemBarVolatile could get optimized out! According to
7166 // Vladimir, this pattern can not occur on Oracle platforms.
7167 // However, it does occur on PPC64 (because of membars in
7168 // inline_unsafe_load_store).
7169 //
7170 // Add this node again if we found a good solution for inline_unsafe_load_store().
7171 // Don't forget to look at the implementation of post_store_load_barrier again,
7172 // we did other fixes in that method.
7173 //instruct unnecessary_membar_volatile() %{
7174 // match(MemBarVolatile);
7175 // predicate(Matcher::post_store_load_barrier(n));
7176 // ins_cost(0);
7177 //
7178 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7179 // size(0);
7180 // ins_encode( /*empty*/ );
7181 // ins_pipe(pipe_class_default);
7182 //%}
7184 instruct membar_CPUOrder() %{
7185 match(MemBarCPUOrder);
7186 ins_cost(0);
7188 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7189 size(0);
7190 ins_encode( /*empty*/ );
7191 ins_pipe(pipe_class_default);
7192 %}
7194 //----------Conditional Move---------------------------------------------------
7196 // Cmove using isel.
7197 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7198 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7199 predicate(VM_Version::has_isel());
7200 ins_cost(DEFAULT_COST);
7202 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7203 size(4);
7204 ins_encode %{
7205 // This is a Power7 instruction for which no machine description
7206 // exists. Anyways, the scheduler should be off on Power7.
7207 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7208 int cc = $cmp$$cmpcode;
7209 __ isel($dst$$Register, $crx$$CondRegister,
7210 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7211 %}
7212 ins_pipe(pipe_class_default);
7213 %}
7215 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7216 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7217 predicate(!VM_Version::has_isel());
7218 ins_cost(DEFAULT_COST+BRANCH_COST);
7220 ins_variable_size_depending_on_alignment(true);
7222 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7223 // Worst case is branch + move + stop, no stop without scheduler
7224 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7225 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7226 ins_pipe(pipe_class_default);
7227 %}
7229 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7230 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7231 ins_cost(DEFAULT_COST+BRANCH_COST);
7233 ins_variable_size_depending_on_alignment(true);
7235 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7236 // Worst case is branch + move + stop, no stop without scheduler
7237 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7238 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7239 ins_pipe(pipe_class_default);
7240 %}
7242 // Cmove using isel.
7243 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7244 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7245 predicate(VM_Version::has_isel());
7246 ins_cost(DEFAULT_COST);
7248 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7249 size(4);
7250 ins_encode %{
7251 // This is a Power7 instruction for which no machine description
7252 // exists. Anyways, the scheduler should be off on Power7.
7253 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7254 int cc = $cmp$$cmpcode;
7255 __ isel($dst$$Register, $crx$$CondRegister,
7256 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7257 %}
7258 ins_pipe(pipe_class_default);
7259 %}
7261 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7262 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7263 predicate(!VM_Version::has_isel());
7264 ins_cost(DEFAULT_COST+BRANCH_COST);
7266 ins_variable_size_depending_on_alignment(true);
7268 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7269 // Worst case is branch + move + stop, no stop without scheduler.
7270 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7271 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7272 ins_pipe(pipe_class_default);
7273 %}
7275 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7276 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7277 ins_cost(DEFAULT_COST+BRANCH_COST);
7279 ins_variable_size_depending_on_alignment(true);
7281 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7282 // Worst case is branch + move + stop, no stop without scheduler.
7283 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7284 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7285 ins_pipe(pipe_class_default);
7286 %}
7288 // Cmove using isel.
7289 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7290 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7291 predicate(VM_Version::has_isel());
7292 ins_cost(DEFAULT_COST);
7294 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7295 size(4);
7296 ins_encode %{
7297 // This is a Power7 instruction for which no machine description
7298 // exists. Anyways, the scheduler should be off on Power7.
7299 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7300 int cc = $cmp$$cmpcode;
7301 __ isel($dst$$Register, $crx$$CondRegister,
7302 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7303 %}
7304 ins_pipe(pipe_class_default);
7305 %}
7307 // Conditional move for RegN. Only cmov(reg, reg).
7308 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7309 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7310 predicate(!VM_Version::has_isel());
7311 ins_cost(DEFAULT_COST+BRANCH_COST);
7313 ins_variable_size_depending_on_alignment(true);
7315 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7316 // Worst case is branch + move + stop, no stop without scheduler.
7317 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7318 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7319 ins_pipe(pipe_class_default);
7320 %}
7322 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7323 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7324 ins_cost(DEFAULT_COST+BRANCH_COST);
7326 ins_variable_size_depending_on_alignment(true);
7328 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7329 // Worst case is branch + move + stop, no stop without scheduler.
7330 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7331 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7332 ins_pipe(pipe_class_default);
7333 %}
7335 // Cmove using isel.
7336 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7337 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7338 predicate(VM_Version::has_isel());
7339 ins_cost(DEFAULT_COST);
7341 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7342 size(4);
7343 ins_encode %{
7344 // This is a Power7 instruction for which no machine description
7345 // exists. Anyways, the scheduler should be off on Power7.
7346 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7347 int cc = $cmp$$cmpcode;
7348 __ isel($dst$$Register, $crx$$CondRegister,
7349 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7350 %}
7351 ins_pipe(pipe_class_default);
7352 %}
7354 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7355 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7356 predicate(!VM_Version::has_isel());
7357 ins_cost(DEFAULT_COST+BRANCH_COST);
7359 ins_variable_size_depending_on_alignment(true);
7361 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7362 // Worst case is branch + move + stop, no stop without scheduler.
7363 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7364 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7365 ins_pipe(pipe_class_default);
7366 %}
7368 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7369 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7370 ins_cost(DEFAULT_COST+BRANCH_COST);
7372 ins_variable_size_depending_on_alignment(true);
7374 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7375 // Worst case is branch + move + stop, no stop without scheduler.
7376 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7377 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7378 ins_pipe(pipe_class_default);
7379 %}
7381 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7382 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7383 ins_cost(DEFAULT_COST+BRANCH_COST);
7385 ins_variable_size_depending_on_alignment(true);
7387 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7388 // Worst case is branch + move + stop, no stop without scheduler.
7389 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7390 ins_encode %{
7391 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7392 Label done;
7393 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7394 // Branch if not (cmp crx).
7395 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7396 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7397 // TODO PPC port __ endgroup_if_needed(_size == 12);
7398 __ bind(done);
7399 %}
7400 ins_pipe(pipe_class_default);
7401 %}
7403 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7404 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7405 ins_cost(DEFAULT_COST+BRANCH_COST);
7407 ins_variable_size_depending_on_alignment(true);
7409 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7410 // Worst case is branch + move + stop, no stop without scheduler.
7411 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7412 ins_encode %{
7413 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7414 Label done;
7415 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7416 // Branch if not (cmp crx).
7417 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7418 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7419 // TODO PPC port __ endgroup_if_needed(_size == 12);
7420 __ bind(done);
7421 %}
7422 ins_pipe(pipe_class_default);
7423 %}
7425 //----------Conditional_store--------------------------------------------------
7426 // Conditional-store of the updated heap-top.
7427 // Used during allocation of the shared heap.
7428 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7430 // As compareAndSwapL, but return flag register instead of boolean value in
7431 // int register.
7432 // Used by sun/misc/AtomicLongCSImpl.java.
7433 // Mem_ptr must be a memory operand, else this node does not get
7434 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7435 // can be rematerialized which leads to errors.
7436 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7437 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7438 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7439 ins_encode %{
7440 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7441 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7442 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7443 noreg, NULL, true);
7444 %}
7445 ins_pipe(pipe_class_default);
7446 %}
7448 // As compareAndSwapP, but return flag register instead of boolean value in
7449 // int register.
7450 // This instruction is matched if UseTLAB is off.
7451 // Mem_ptr must be a memory operand, else this node does not get
7452 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7453 // can be rematerialized which leads to errors.
7454 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7455 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7456 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7457 ins_encode %{
7458 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7459 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7460 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7461 noreg, NULL, true);
7462 %}
7463 ins_pipe(pipe_class_default);
7464 %}
7466 // Implement LoadPLocked. Must be ordered against changes of the memory location
7467 // by storePConditional.
7468 // Don't know whether this is ever used.
7469 instruct loadPLocked(iRegPdst dst, memory mem) %{
7470 match(Set dst (LoadPLocked mem));
7471 ins_cost(MEMORY_REF_COST);
7473 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7474 "TWI $dst\n\t"
7475 "ISYNC" %}
7476 size(12);
7477 ins_encode( enc_ld_ac(dst, mem) );
7478 ins_pipe(pipe_class_memory);
7479 %}
7481 //----------Compare-And-Swap---------------------------------------------------
7483 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7484 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7485 // matched.
7487 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7488 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7489 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7490 // Variable size: instruction count smaller if regs are disjoint.
7491 ins_encode %{
7492 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7493 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7494 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7495 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7496 $res$$Register, true);
7497 %}
7498 ins_pipe(pipe_class_default);
7499 %}
7501 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7502 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7503 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7504 // Variable size: instruction count smaller if regs are disjoint.
7505 ins_encode %{
7506 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7507 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7508 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7509 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7510 $res$$Register, true);
7511 %}
7512 ins_pipe(pipe_class_default);
7513 %}
7515 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7516 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7517 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7518 // Variable size: instruction count smaller if regs are disjoint.
7519 ins_encode %{
7520 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7521 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7522 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7523 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7524 $res$$Register, NULL, true);
7525 %}
7526 ins_pipe(pipe_class_default);
7527 %}
7529 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7530 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7531 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7532 // Variable size: instruction count smaller if regs are disjoint.
7533 ins_encode %{
7534 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7535 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7536 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7537 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7538 $res$$Register, NULL, true);
7539 %}
7540 ins_pipe(pipe_class_default);
7541 %}
7543 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7544 match(Set res (GetAndAddI mem_ptr src));
7545 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7546 // Variable size: instruction count smaller if regs are disjoint.
7547 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7548 ins_pipe(pipe_class_default);
7549 %}
7551 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7552 match(Set res (GetAndAddL mem_ptr src));
7553 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7554 // Variable size: instruction count smaller if regs are disjoint.
7555 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7556 ins_pipe(pipe_class_default);
7557 %}
7559 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7560 match(Set res (GetAndSetI mem_ptr src));
7561 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7562 // Variable size: instruction count smaller if regs are disjoint.
7563 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7564 ins_pipe(pipe_class_default);
7565 %}
7567 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7568 match(Set res (GetAndSetL mem_ptr src));
7569 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7570 // Variable size: instruction count smaller if regs are disjoint.
7571 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7572 ins_pipe(pipe_class_default);
7573 %}
7575 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7576 match(Set res (GetAndSetP mem_ptr src));
7577 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7578 // Variable size: instruction count smaller if regs are disjoint.
7579 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7580 ins_pipe(pipe_class_default);
7581 %}
7583 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7584 match(Set res (GetAndSetN mem_ptr src));
7585 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7586 // Variable size: instruction count smaller if regs are disjoint.
7587 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7588 ins_pipe(pipe_class_default);
7589 %}
7591 //----------Arithmetic Instructions--------------------------------------------
7592 // Addition Instructions
7594 // PPC has no instruction setting overflow of 32-bit integer.
7595 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{
7596 // match(AddExactI dst src);
7597 // effect(DEF cr);
7598 //
7599 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %}
7600 // ins_encode( enc_add(dst, dst, src) );
7601 // ins_pipe(pipe_class_default);
7602 //%}
7604 // Register Addition
7605 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7606 match(Set dst (AddI src1 src2));
7607 format %{ "ADD $dst, $src1, $src2" %}
7608 size(4);
7609 ins_encode %{
7610 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7611 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7612 %}
7613 ins_pipe(pipe_class_default);
7614 %}
7616 // Expand does not work with above instruct. (??)
7617 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7618 // no match-rule
7619 effect(DEF dst, USE src1, USE src2);
7620 format %{ "ADD $dst, $src1, $src2" %}
7621 size(4);
7622 ins_encode %{
7623 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7624 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7625 %}
7626 ins_pipe(pipe_class_default);
7627 %}
7629 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7630 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7631 ins_cost(DEFAULT_COST*3);
7633 expand %{
7634 // FIXME: we should do this in the ideal world.
7635 iRegIdst tmp1;
7636 iRegIdst tmp2;
7637 addI_reg_reg(tmp1, src1, src2);
7638 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7639 addI_reg_reg(dst, tmp1, tmp2);
7640 %}
7641 %}
7643 // Immediate Addition
7644 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7645 match(Set dst (AddI src1 src2));
7646 format %{ "ADDI $dst, $src1, $src2" %}
7647 size(4);
7648 ins_encode %{
7649 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7650 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7651 %}
7652 ins_pipe(pipe_class_default);
7653 %}
7655 // Immediate Addition with 16-bit shifted operand
7656 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7657 match(Set dst (AddI src1 src2));
7658 format %{ "ADDIS $dst, $src1, $src2" %}
7659 size(4);
7660 ins_encode %{
7661 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7662 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7663 %}
7664 ins_pipe(pipe_class_default);
7665 %}
7667 // Long Addition
7668 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7669 match(Set dst (AddL src1 src2));
7670 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7671 size(4);
7672 ins_encode %{
7673 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7674 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7675 %}
7676 ins_pipe(pipe_class_default);
7677 %}
7679 // Expand does not work with above instruct. (??)
7680 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7681 // no match-rule
7682 effect(DEF dst, USE src1, USE src2);
7683 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7684 size(4);
7685 ins_encode %{
7686 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7687 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7688 %}
7689 ins_pipe(pipe_class_default);
7690 %}
7692 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7693 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7694 ins_cost(DEFAULT_COST*3);
7696 expand %{
7697 // FIXME: we should do this in the ideal world.
7698 iRegLdst tmp1;
7699 iRegLdst tmp2;
7700 addL_reg_reg(tmp1, src1, src2);
7701 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7702 addL_reg_reg(dst, tmp1, tmp2);
7703 %}
7704 %}
7706 // AddL + ConvL2I.
7707 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7708 match(Set dst (ConvL2I (AddL src1 src2)));
7710 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7711 size(4);
7712 ins_encode %{
7713 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7714 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7715 %}
7716 ins_pipe(pipe_class_default);
7717 %}
7719 // No constant pool entries required.
7720 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7721 match(Set dst (AddL src1 src2));
7723 format %{ "ADDI $dst, $src1, $src2" %}
7724 size(4);
7725 ins_encode %{
7726 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7727 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7728 %}
7729 ins_pipe(pipe_class_default);
7730 %}
7732 // Long Immediate Addition with 16-bit shifted operand.
7733 // No constant pool entries required.
7734 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7735 match(Set dst (AddL src1 src2));
7737 format %{ "ADDIS $dst, $src1, $src2" %}
7738 size(4);
7739 ins_encode %{
7740 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7741 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7742 %}
7743 ins_pipe(pipe_class_default);
7744 %}
7746 // Pointer Register Addition
7747 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7748 match(Set dst (AddP src1 src2));
7749 format %{ "ADD $dst, $src1, $src2" %}
7750 size(4);
7751 ins_encode %{
7752 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7753 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7754 %}
7755 ins_pipe(pipe_class_default);
7756 %}
7758 // Pointer Immediate Addition
7759 // No constant pool entries required.
7760 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7761 match(Set dst (AddP src1 src2));
7763 format %{ "ADDI $dst, $src1, $src2" %}
7764 size(4);
7765 ins_encode %{
7766 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7767 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7768 %}
7769 ins_pipe(pipe_class_default);
7770 %}
7772 // Pointer Immediate Addition with 16-bit shifted operand.
7773 // No constant pool entries required.
7774 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7775 match(Set dst (AddP src1 src2));
7777 format %{ "ADDIS $dst, $src1, $src2" %}
7778 size(4);
7779 ins_encode %{
7780 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7781 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7782 %}
7783 ins_pipe(pipe_class_default);
7784 %}
7786 //---------------------
7787 // Subtraction Instructions
7789 // Register Subtraction
7790 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7791 match(Set dst (SubI src1 src2));
7792 format %{ "SUBF $dst, $src2, $src1" %}
7793 size(4);
7794 ins_encode %{
7795 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7796 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7797 %}
7798 ins_pipe(pipe_class_default);
7799 %}
7801 // Immediate Subtraction
7802 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7803 // so this rule seems to be unused.
7804 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7805 match(Set dst (SubI src1 src2));
7806 format %{ "SUBI $dst, $src1, $src2" %}
7807 size(4);
7808 ins_encode %{
7809 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7810 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7811 %}
7812 ins_pipe(pipe_class_default);
7813 %}
7815 // SubI from constant (using subfic).
7816 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7817 match(Set dst (SubI src1 src2));
7818 format %{ "SUBI $dst, $src1, $src2" %}
7820 size(4);
7821 ins_encode %{
7822 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7823 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7824 %}
7825 ins_pipe(pipe_class_default);
7826 %}
7828 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7829 // positive integers and 0xF...F for negative ones.
7830 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7831 // no match-rule, false predicate
7832 effect(DEF dst, USE src);
7833 predicate(false);
7835 format %{ "SRAWI $dst, $src, #31" %}
7836 size(4);
7837 ins_encode %{
7838 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7839 __ srawi($dst$$Register, $src$$Register, 0x1f);
7840 %}
7841 ins_pipe(pipe_class_default);
7842 %}
7844 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7845 match(Set dst (AbsI src));
7846 ins_cost(DEFAULT_COST*3);
7848 expand %{
7849 iRegIdst tmp1;
7850 iRegIdst tmp2;
7851 signmask32I_regI(tmp1, src);
7852 xorI_reg_reg(tmp2, tmp1, src);
7853 subI_reg_reg(dst, tmp2, tmp1);
7854 %}
7855 %}
7857 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7858 match(Set dst (SubI zero src2));
7859 format %{ "NEG $dst, $src2" %}
7860 size(4);
7861 ins_encode %{
7862 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7863 __ neg($dst$$Register, $src2$$Register);
7864 %}
7865 ins_pipe(pipe_class_default);
7866 %}
7868 // Long subtraction
7869 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7870 match(Set dst (SubL src1 src2));
7871 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7872 size(4);
7873 ins_encode %{
7874 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7875 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7876 %}
7877 ins_pipe(pipe_class_default);
7878 %}
7880 // SubL + convL2I.
7881 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7882 match(Set dst (ConvL2I (SubL src1 src2)));
7884 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7885 size(4);
7886 ins_encode %{
7887 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7888 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7889 %}
7890 ins_pipe(pipe_class_default);
7891 %}
7893 // Immediate Subtraction
7894 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7895 // so this rule seems to be unused.
7896 // No constant pool entries required.
7897 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7898 match(Set dst (SubL src1 src2));
7900 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7901 size(4);
7902 ins_encode %{
7903 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7904 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7905 %}
7906 ins_pipe(pipe_class_default);
7907 %}
7909 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7910 // positive longs and 0xF...F for negative ones.
7911 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7912 // no match-rule, false predicate
7913 effect(DEF dst, USE src);
7914 predicate(false);
7916 format %{ "SRADI $dst, $src, #63" %}
7917 size(4);
7918 ins_encode %{
7919 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7920 __ sradi($dst$$Register, $src$$Register, 0x3f);
7921 %}
7922 ins_pipe(pipe_class_default);
7923 %}
7925 // Long negation
7926 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7927 match(Set dst (SubL zero src2));
7928 format %{ "NEG $dst, $src2 \t// long" %}
7929 size(4);
7930 ins_encode %{
7931 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7932 __ neg($dst$$Register, $src2$$Register);
7933 %}
7934 ins_pipe(pipe_class_default);
7935 %}
7937 // NegL + ConvL2I.
7938 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7939 match(Set dst (ConvL2I (SubL zero src2)));
7941 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7942 size(4);
7943 ins_encode %{
7944 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7945 __ neg($dst$$Register, $src2$$Register);
7946 %}
7947 ins_pipe(pipe_class_default);
7948 %}
7950 // Multiplication Instructions
7951 // Integer Multiplication
7953 // Register Multiplication
7954 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7955 match(Set dst (MulI src1 src2));
7956 ins_cost(DEFAULT_COST);
7958 format %{ "MULLW $dst, $src1, $src2" %}
7959 size(4);
7960 ins_encode %{
7961 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7962 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7963 %}
7964 ins_pipe(pipe_class_default);
7965 %}
7967 // Immediate Multiplication
7968 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7969 match(Set dst (MulI src1 src2));
7970 ins_cost(DEFAULT_COST);
7972 format %{ "MULLI $dst, $src1, $src2" %}
7973 size(4);
7974 ins_encode %{
7975 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7976 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7977 %}
7978 ins_pipe(pipe_class_default);
7979 %}
7981 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7982 match(Set dst (MulL src1 src2));
7983 ins_cost(DEFAULT_COST);
7985 format %{ "MULLD $dst $src1, $src2 \t// long" %}
7986 size(4);
7987 ins_encode %{
7988 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
7989 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
7990 %}
7991 ins_pipe(pipe_class_default);
7992 %}
7994 // Multiply high for optimized long division by constant.
7995 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7996 match(Set dst (MulHiL src1 src2));
7997 ins_cost(DEFAULT_COST);
7999 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8000 size(4);
8001 ins_encode %{
8002 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8003 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8004 %}
8005 ins_pipe(pipe_class_default);
8006 %}
8008 // Immediate Multiplication
8009 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8010 match(Set dst (MulL src1 src2));
8011 ins_cost(DEFAULT_COST);
8013 format %{ "MULLI $dst, $src1, $src2" %}
8014 size(4);
8015 ins_encode %{
8016 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8017 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8018 %}
8019 ins_pipe(pipe_class_default);
8020 %}
8022 // Integer Division with Immediate -1: Negate.
8023 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8024 match(Set dst (DivI src1 src2));
8025 ins_cost(DEFAULT_COST);
8027 format %{ "NEG $dst, $src1 \t// /-1" %}
8028 size(4);
8029 ins_encode %{
8030 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8031 __ neg($dst$$Register, $src1$$Register);
8032 %}
8033 ins_pipe(pipe_class_default);
8034 %}
8036 // Integer Division with constant, but not -1.
8037 // We should be able to improve this by checking the type of src2.
8038 // It might well be that src2 is known to be positive.
8039 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8040 match(Set dst (DivI src1 src2));
8041 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8042 ins_cost(2*DEFAULT_COST);
8044 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8045 size(4);
8046 ins_encode %{
8047 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8048 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8049 %}
8050 ins_pipe(pipe_class_default);
8051 %}
8053 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8054 effect(USE_DEF dst, USE src1, USE crx);
8055 predicate(false);
8057 ins_variable_size_depending_on_alignment(true);
8059 format %{ "CMOVE $dst, neg($src1), $crx" %}
8060 // Worst case is branch + move + stop, no stop without scheduler.
8061 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8062 ins_encode %{
8063 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8064 Label done;
8065 __ bne($crx$$CondRegister, done);
8066 __ neg($dst$$Register, $src1$$Register);
8067 // TODO PPC port __ endgroup_if_needed(_size == 12);
8068 __ bind(done);
8069 %}
8070 ins_pipe(pipe_class_default);
8071 %}
8073 // Integer Division with Registers not containing constants.
8074 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8075 match(Set dst (DivI src1 src2));
8076 ins_cost(10*DEFAULT_COST);
8078 expand %{
8079 immI16 imm %{ (int)-1 %}
8080 flagsReg tmp1;
8081 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8082 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8083 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8084 %}
8085 %}
8087 // Long Division with Immediate -1: Negate.
8088 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8089 match(Set dst (DivL src1 src2));
8090 ins_cost(DEFAULT_COST);
8092 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8093 size(4);
8094 ins_encode %{
8095 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8096 __ neg($dst$$Register, $src1$$Register);
8097 %}
8098 ins_pipe(pipe_class_default);
8099 %}
8101 // Long Division with constant, but not -1.
8102 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8103 match(Set dst (DivL src1 src2));
8104 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8105 ins_cost(2*DEFAULT_COST);
8107 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8108 size(4);
8109 ins_encode %{
8110 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8111 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8112 %}
8113 ins_pipe(pipe_class_default);
8114 %}
8116 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8117 effect(USE_DEF dst, USE src1, USE crx);
8118 predicate(false);
8120 ins_variable_size_depending_on_alignment(true);
8122 format %{ "CMOVE $dst, neg($src1), $crx" %}
8123 // Worst case is branch + move + stop, no stop without scheduler.
8124 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8125 ins_encode %{
8126 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8127 Label done;
8128 __ bne($crx$$CondRegister, done);
8129 __ neg($dst$$Register, $src1$$Register);
8130 // TODO PPC port __ endgroup_if_needed(_size == 12);
8131 __ bind(done);
8132 %}
8133 ins_pipe(pipe_class_default);
8134 %}
8136 // Long Division with Registers not containing constants.
8137 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8138 match(Set dst (DivL src1 src2));
8139 ins_cost(10*DEFAULT_COST);
8141 expand %{
8142 immL16 imm %{ (int)-1 %}
8143 flagsReg tmp1;
8144 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8145 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8146 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8147 %}
8148 %}
8150 // Integer Remainder with registers.
8151 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8152 match(Set dst (ModI src1 src2));
8153 ins_cost(10*DEFAULT_COST);
8155 expand %{
8156 immI16 imm %{ (int)-1 %}
8157 flagsReg tmp1;
8158 iRegIdst tmp2;
8159 iRegIdst tmp3;
8160 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8161 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8162 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8163 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8164 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8165 %}
8166 %}
8168 // Long Remainder with registers
8169 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8170 match(Set dst (ModL src1 src2));
8171 ins_cost(10*DEFAULT_COST);
8173 expand %{
8174 immL16 imm %{ (int)-1 %}
8175 flagsReg tmp1;
8176 iRegLdst tmp2;
8177 iRegLdst tmp3;
8178 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8179 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8180 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8181 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8182 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8183 %}
8184 %}
8186 // Integer Shift Instructions
8188 // Register Shift Left
8190 // Clear all but the lowest #mask bits.
8191 // Used to normalize shift amounts in registers.
8192 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8193 // no match-rule, false predicate
8194 effect(DEF dst, USE src, USE mask);
8195 predicate(false);
8197 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8198 size(4);
8199 ins_encode %{
8200 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8201 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8202 %}
8203 ins_pipe(pipe_class_default);
8204 %}
8206 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8207 // no match-rule, false predicate
8208 effect(DEF dst, USE src1, USE src2);
8209 predicate(false);
8211 format %{ "SLW $dst, $src1, $src2" %}
8212 size(4);
8213 ins_encode %{
8214 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8215 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8216 %}
8217 ins_pipe(pipe_class_default);
8218 %}
8220 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8221 match(Set dst (LShiftI src1 src2));
8222 ins_cost(DEFAULT_COST*2);
8223 expand %{
8224 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8225 iRegIdst tmpI;
8226 maskI_reg_imm(tmpI, src2, mask);
8227 lShiftI_reg_reg(dst, src1, tmpI);
8228 %}
8229 %}
8231 // Register Shift Left Immediate
8232 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8233 match(Set dst (LShiftI src1 src2));
8235 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8236 size(4);
8237 ins_encode %{
8238 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8239 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8240 %}
8241 ins_pipe(pipe_class_default);
8242 %}
8244 // AndI with negpow2-constant + LShiftI
8245 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8246 match(Set dst (LShiftI (AndI src1 src2) src3));
8247 predicate(UseRotateAndMaskInstructionsPPC64);
8249 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8250 size(4);
8251 ins_encode %{
8252 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8253 long src2 = $src2$$constant;
8254 long src3 = $src3$$constant;
8255 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8256 if (maskbits >= 32) {
8257 __ li($dst$$Register, 0); // addi
8258 } else {
8259 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8260 }
8261 %}
8262 ins_pipe(pipe_class_default);
8263 %}
8265 // RShiftI + AndI with negpow2-constant + LShiftI
8266 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8267 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8268 predicate(UseRotateAndMaskInstructionsPPC64);
8270 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8271 size(4);
8272 ins_encode %{
8273 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8274 long src2 = $src2$$constant;
8275 long src3 = $src3$$constant;
8276 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8277 if (maskbits >= 32) {
8278 __ li($dst$$Register, 0); // addi
8279 } else {
8280 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8281 }
8282 %}
8283 ins_pipe(pipe_class_default);
8284 %}
8286 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8287 // no match-rule, false predicate
8288 effect(DEF dst, USE src1, USE src2);
8289 predicate(false);
8291 format %{ "SLD $dst, $src1, $src2" %}
8292 size(4);
8293 ins_encode %{
8294 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8295 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8296 %}
8297 ins_pipe(pipe_class_default);
8298 %}
8300 // Register Shift Left
8301 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8302 match(Set dst (LShiftL src1 src2));
8303 ins_cost(DEFAULT_COST*2);
8304 expand %{
8305 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8306 iRegIdst tmpI;
8307 maskI_reg_imm(tmpI, src2, mask);
8308 lShiftL_regL_regI(dst, src1, tmpI);
8309 %}
8310 %}
8312 // Register Shift Left Immediate
8313 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8314 match(Set dst (LShiftL src1 src2));
8315 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8316 size(4);
8317 ins_encode %{
8318 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8319 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8320 %}
8321 ins_pipe(pipe_class_default);
8322 %}
8324 // If we shift more than 32 bits, we need not convert I2L.
8325 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8326 match(Set dst (LShiftL (ConvI2L src1) src2));
8327 ins_cost(DEFAULT_COST);
8329 size(4);
8330 format %{ "SLDI $dst, i2l($src1), $src2" %}
8331 ins_encode %{
8332 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8333 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8334 %}
8335 ins_pipe(pipe_class_default);
8336 %}
8338 // Shift a postivie int to the left.
8339 // Clrlsldi clears the upper 32 bits and shifts.
8340 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8341 match(Set dst (LShiftL (ConvI2L src1) src2));
8342 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8344 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8345 size(4);
8346 ins_encode %{
8347 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8348 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8349 %}
8350 ins_pipe(pipe_class_default);
8351 %}
8353 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8354 // no match-rule, false predicate
8355 effect(DEF dst, USE src1, USE src2);
8356 predicate(false);
8358 format %{ "SRAW $dst, $src1, $src2" %}
8359 size(4);
8360 ins_encode %{
8361 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8362 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8363 %}
8364 ins_pipe(pipe_class_default);
8365 %}
8367 // Register Arithmetic Shift Right
8368 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8369 match(Set dst (RShiftI src1 src2));
8370 ins_cost(DEFAULT_COST*2);
8371 expand %{
8372 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8373 iRegIdst tmpI;
8374 maskI_reg_imm(tmpI, src2, mask);
8375 arShiftI_reg_reg(dst, src1, tmpI);
8376 %}
8377 %}
8379 // Register Arithmetic Shift Right Immediate
8380 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8381 match(Set dst (RShiftI src1 src2));
8383 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8384 size(4);
8385 ins_encode %{
8386 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8387 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8388 %}
8389 ins_pipe(pipe_class_default);
8390 %}
8392 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8393 // no match-rule, false predicate
8394 effect(DEF dst, USE src1, USE src2);
8395 predicate(false);
8397 format %{ "SRAD $dst, $src1, $src2" %}
8398 size(4);
8399 ins_encode %{
8400 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8401 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8402 %}
8403 ins_pipe(pipe_class_default);
8404 %}
8406 // Register Shift Right Arithmetic Long
8407 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8408 match(Set dst (RShiftL src1 src2));
8409 ins_cost(DEFAULT_COST*2);
8411 expand %{
8412 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8413 iRegIdst tmpI;
8414 maskI_reg_imm(tmpI, src2, mask);
8415 arShiftL_regL_regI(dst, src1, tmpI);
8416 %}
8417 %}
8419 // Register Shift Right Immediate
8420 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8421 match(Set dst (RShiftL src1 src2));
8423 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8424 size(4);
8425 ins_encode %{
8426 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8427 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8428 %}
8429 ins_pipe(pipe_class_default);
8430 %}
8432 // RShiftL + ConvL2I
8433 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8434 match(Set dst (ConvL2I (RShiftL src1 src2)));
8436 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8437 size(4);
8438 ins_encode %{
8439 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8440 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8441 %}
8442 ins_pipe(pipe_class_default);
8443 %}
8445 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8446 // no match-rule, false predicate
8447 effect(DEF dst, USE src1, USE src2);
8448 predicate(false);
8450 format %{ "SRW $dst, $src1, $src2" %}
8451 size(4);
8452 ins_encode %{
8453 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8454 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8455 %}
8456 ins_pipe(pipe_class_default);
8457 %}
8459 // Register Shift Right
8460 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8461 match(Set dst (URShiftI src1 src2));
8462 ins_cost(DEFAULT_COST*2);
8464 expand %{
8465 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8466 iRegIdst tmpI;
8467 maskI_reg_imm(tmpI, src2, mask);
8468 urShiftI_reg_reg(dst, src1, tmpI);
8469 %}
8470 %}
8472 // Register Shift Right Immediate
8473 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8474 match(Set dst (URShiftI src1 src2));
8476 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8477 size(4);
8478 ins_encode %{
8479 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8480 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8481 %}
8482 ins_pipe(pipe_class_default);
8483 %}
8485 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8486 // no match-rule, false predicate
8487 effect(DEF dst, USE src1, USE src2);
8488 predicate(false);
8490 format %{ "SRD $dst, $src1, $src2" %}
8491 size(4);
8492 ins_encode %{
8493 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8494 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8495 %}
8496 ins_pipe(pipe_class_default);
8497 %}
8499 // Register Shift Right
8500 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8501 match(Set dst (URShiftL src1 src2));
8502 ins_cost(DEFAULT_COST*2);
8504 expand %{
8505 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8506 iRegIdst tmpI;
8507 maskI_reg_imm(tmpI, src2, mask);
8508 urShiftL_regL_regI(dst, src1, tmpI);
8509 %}
8510 %}
8512 // Register Shift Right Immediate
8513 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8514 match(Set dst (URShiftL src1 src2));
8516 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8517 size(4);
8518 ins_encode %{
8519 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8520 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8521 %}
8522 ins_pipe(pipe_class_default);
8523 %}
8525 // URShiftL + ConvL2I.
8526 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8527 match(Set dst (ConvL2I (URShiftL src1 src2)));
8529 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8530 size(4);
8531 ins_encode %{
8532 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8533 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8534 %}
8535 ins_pipe(pipe_class_default);
8536 %}
8538 // Register Shift Right Immediate with a CastP2X
8539 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8540 match(Set dst (URShiftL (CastP2X src1) src2));
8542 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8543 size(4);
8544 ins_encode %{
8545 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8546 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8547 %}
8548 ins_pipe(pipe_class_default);
8549 %}
8551 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8552 match(Set dst (ConvL2I (ConvI2L src)));
8554 format %{ "EXTSW $dst, $src \t// int->int" %}
8555 size(4);
8556 ins_encode %{
8557 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8558 __ extsw($dst$$Register, $src$$Register);
8559 %}
8560 ins_pipe(pipe_class_default);
8561 %}
8563 //----------Rotate Instructions------------------------------------------------
8565 // Rotate Left by 8-bit immediate
8566 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8567 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8568 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8570 format %{ "ROTLWI $dst, $src, $lshift" %}
8571 size(4);
8572 ins_encode %{
8573 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8574 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8575 %}
8576 ins_pipe(pipe_class_default);
8577 %}
8579 // Rotate Right by 8-bit immediate
8580 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8581 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8582 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8584 format %{ "ROTRWI $dst, $rshift" %}
8585 size(4);
8586 ins_encode %{
8587 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8588 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8589 %}
8590 ins_pipe(pipe_class_default);
8591 %}
8593 //----------Floating Point Arithmetic Instructions-----------------------------
8595 // Add float single precision
8596 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8597 match(Set dst (AddF src1 src2));
8599 format %{ "FADDS $dst, $src1, $src2" %}
8600 size(4);
8601 ins_encode %{
8602 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8603 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8604 %}
8605 ins_pipe(pipe_class_default);
8606 %}
8608 // Add float double precision
8609 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8610 match(Set dst (AddD src1 src2));
8612 format %{ "FADD $dst, $src1, $src2" %}
8613 size(4);
8614 ins_encode %{
8615 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8616 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8617 %}
8618 ins_pipe(pipe_class_default);
8619 %}
8621 // Sub float single precision
8622 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8623 match(Set dst (SubF src1 src2));
8625 format %{ "FSUBS $dst, $src1, $src2" %}
8626 size(4);
8627 ins_encode %{
8628 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8629 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8630 %}
8631 ins_pipe(pipe_class_default);
8632 %}
8634 // Sub float double precision
8635 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8636 match(Set dst (SubD src1 src2));
8637 format %{ "FSUB $dst, $src1, $src2" %}
8638 size(4);
8639 ins_encode %{
8640 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8641 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8642 %}
8643 ins_pipe(pipe_class_default);
8644 %}
8646 // Mul float single precision
8647 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8648 match(Set dst (MulF src1 src2));
8649 format %{ "FMULS $dst, $src1, $src2" %}
8650 size(4);
8651 ins_encode %{
8652 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8653 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8654 %}
8655 ins_pipe(pipe_class_default);
8656 %}
8658 // Mul float double precision
8659 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8660 match(Set dst (MulD src1 src2));
8661 format %{ "FMUL $dst, $src1, $src2" %}
8662 size(4);
8663 ins_encode %{
8664 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8665 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8666 %}
8667 ins_pipe(pipe_class_default);
8668 %}
8670 // Div float single precision
8671 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8672 match(Set dst (DivF src1 src2));
8673 format %{ "FDIVS $dst, $src1, $src2" %}
8674 size(4);
8675 ins_encode %{
8676 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8677 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8678 %}
8679 ins_pipe(pipe_class_default);
8680 %}
8682 // Div float double precision
8683 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8684 match(Set dst (DivD src1 src2));
8685 format %{ "FDIV $dst, $src1, $src2" %}
8686 size(4);
8687 ins_encode %{
8688 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8689 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8690 %}
8691 ins_pipe(pipe_class_default);
8692 %}
8694 // Absolute float single precision
8695 instruct absF_reg(regF dst, regF src) %{
8696 match(Set dst (AbsF src));
8697 format %{ "FABS $dst, $src \t// float" %}
8698 size(4);
8699 ins_encode %{
8700 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8701 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8702 %}
8703 ins_pipe(pipe_class_default);
8704 %}
8706 // Absolute float double precision
8707 instruct absD_reg(regD dst, regD src) %{
8708 match(Set dst (AbsD src));
8709 format %{ "FABS $dst, $src \t// double" %}
8710 size(4);
8711 ins_encode %{
8712 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8713 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8714 %}
8715 ins_pipe(pipe_class_default);
8716 %}
8718 instruct negF_reg(regF dst, regF src) %{
8719 match(Set dst (NegF src));
8720 format %{ "FNEG $dst, $src \t// float" %}
8721 size(4);
8722 ins_encode %{
8723 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8724 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8725 %}
8726 ins_pipe(pipe_class_default);
8727 %}
8729 instruct negD_reg(regD dst, regD src) %{
8730 match(Set dst (NegD src));
8731 format %{ "FNEG $dst, $src \t// double" %}
8732 size(4);
8733 ins_encode %{
8734 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8735 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8736 %}
8737 ins_pipe(pipe_class_default);
8738 %}
8740 // AbsF + NegF.
8741 instruct negF_absF_reg(regF dst, regF src) %{
8742 match(Set dst (NegF (AbsF src)));
8743 format %{ "FNABS $dst, $src \t// float" %}
8744 size(4);
8745 ins_encode %{
8746 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8747 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8748 %}
8749 ins_pipe(pipe_class_default);
8750 %}
8752 // AbsD + NegD.
8753 instruct negD_absD_reg(regD dst, regD src) %{
8754 match(Set dst (NegD (AbsD src)));
8755 format %{ "FNABS $dst, $src \t// double" %}
8756 size(4);
8757 ins_encode %{
8758 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8759 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8760 %}
8761 ins_pipe(pipe_class_default);
8762 %}
8764 // VM_Version::has_fsqrt() decides if this node will be used.
8765 // Sqrt float double precision
8766 instruct sqrtD_reg(regD dst, regD src) %{
8767 match(Set dst (SqrtD src));
8768 format %{ "FSQRT $dst, $src" %}
8769 size(4);
8770 ins_encode %{
8771 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8772 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8773 %}
8774 ins_pipe(pipe_class_default);
8775 %}
8777 // Single-precision sqrt.
8778 instruct sqrtF_reg(regF dst, regF src) %{
8779 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8780 predicate(VM_Version::has_fsqrts());
8781 ins_cost(DEFAULT_COST);
8783 format %{ "FSQRTS $dst, $src" %}
8784 size(4);
8785 ins_encode %{
8786 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8787 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8788 %}
8789 ins_pipe(pipe_class_default);
8790 %}
8792 instruct roundDouble_nop(regD dst) %{
8793 match(Set dst (RoundDouble dst));
8794 ins_cost(0);
8796 format %{ " -- \t// RoundDouble not needed - empty" %}
8797 size(0);
8798 // PPC results are already "rounded" (i.e., normal-format IEEE).
8799 ins_encode( /*empty*/ );
8800 ins_pipe(pipe_class_default);
8801 %}
8803 instruct roundFloat_nop(regF dst) %{
8804 match(Set dst (RoundFloat dst));
8805 ins_cost(0);
8807 format %{ " -- \t// RoundFloat not needed - empty" %}
8808 size(0);
8809 // PPC results are already "rounded" (i.e., normal-format IEEE).
8810 ins_encode( /*empty*/ );
8811 ins_pipe(pipe_class_default);
8812 %}
8814 //----------Logical Instructions-----------------------------------------------
8816 // And Instructions
8818 // Register And
8819 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8820 match(Set dst (AndI src1 src2));
8821 format %{ "AND $dst, $src1, $src2" %}
8822 size(4);
8823 ins_encode %{
8824 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8825 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8826 %}
8827 ins_pipe(pipe_class_default);
8828 %}
8830 // Immediate And
8831 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8832 match(Set dst (AndI src1 src2));
8833 effect(KILL cr0);
8835 format %{ "ANDI $dst, $src1, $src2" %}
8836 size(4);
8837 ins_encode %{
8838 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8839 // FIXME: avoid andi_ ?
8840 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8841 %}
8842 ins_pipe(pipe_class_default);
8843 %}
8845 // Immediate And where the immediate is a negative power of 2.
8846 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8847 match(Set dst (AndI src1 src2));
8848 format %{ "ANDWI $dst, $src1, $src2" %}
8849 size(4);
8850 ins_encode %{
8851 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8852 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8853 %}
8854 ins_pipe(pipe_class_default);
8855 %}
8857 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8858 match(Set dst (AndI src1 src2));
8859 format %{ "ANDWI $dst, $src1, $src2" %}
8860 size(4);
8861 ins_encode %{
8862 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8863 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8864 %}
8865 ins_pipe(pipe_class_default);
8866 %}
8868 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8869 match(Set dst (AndI src1 src2));
8870 predicate(UseRotateAndMaskInstructionsPPC64);
8871 format %{ "ANDWI $dst, $src1, $src2" %}
8872 size(4);
8873 ins_encode %{
8874 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8875 __ rlwinm($dst$$Register, $src1$$Register, 0,
8876 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8877 %}
8878 ins_pipe(pipe_class_default);
8879 %}
8881 // Register And Long
8882 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8883 match(Set dst (AndL src1 src2));
8884 ins_cost(DEFAULT_COST);
8886 format %{ "AND $dst, $src1, $src2 \t// long" %}
8887 size(4);
8888 ins_encode %{
8889 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8890 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8891 %}
8892 ins_pipe(pipe_class_default);
8893 %}
8895 // Immediate And long
8896 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8897 match(Set dst (AndL src1 src2));
8898 effect(KILL cr0);
8899 ins_cost(DEFAULT_COST);
8901 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8902 size(4);
8903 ins_encode %{
8904 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8905 // FIXME: avoid andi_ ?
8906 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8907 %}
8908 ins_pipe(pipe_class_default);
8909 %}
8911 // Immediate And Long where the immediate is a negative power of 2.
8912 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8913 match(Set dst (AndL src1 src2));
8914 format %{ "ANDDI $dst, $src1, $src2" %}
8915 size(4);
8916 ins_encode %{
8917 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8918 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8919 %}
8920 ins_pipe(pipe_class_default);
8921 %}
8923 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8924 match(Set dst (AndL src1 src2));
8925 format %{ "ANDDI $dst, $src1, $src2" %}
8926 size(4);
8927 ins_encode %{
8928 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8929 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8930 %}
8931 ins_pipe(pipe_class_default);
8932 %}
8934 // AndL + ConvL2I.
8935 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8936 match(Set dst (ConvL2I (AndL src1 src2)));
8937 ins_cost(DEFAULT_COST);
8939 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8940 size(4);
8941 ins_encode %{
8942 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8943 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8944 %}
8945 ins_pipe(pipe_class_default);
8946 %}
8948 // Or Instructions
8950 // Register Or
8951 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8952 match(Set dst (OrI src1 src2));
8953 format %{ "OR $dst, $src1, $src2" %}
8954 size(4);
8955 ins_encode %{
8956 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8957 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8958 %}
8959 ins_pipe(pipe_class_default);
8960 %}
8962 // Expand does not work with above instruct. (??)
8963 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8964 // no match-rule
8965 effect(DEF dst, USE src1, USE src2);
8966 format %{ "OR $dst, $src1, $src2" %}
8967 size(4);
8968 ins_encode %{
8969 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8970 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8971 %}
8972 ins_pipe(pipe_class_default);
8973 %}
8975 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8976 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8977 ins_cost(DEFAULT_COST*3);
8979 expand %{
8980 // FIXME: we should do this in the ideal world.
8981 iRegIdst tmp1;
8982 iRegIdst tmp2;
8983 orI_reg_reg(tmp1, src1, src2);
8984 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8985 orI_reg_reg(dst, tmp1, tmp2);
8986 %}
8987 %}
8989 // Immediate Or
8990 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
8991 match(Set dst (OrI src1 src2));
8992 format %{ "ORI $dst, $src1, $src2" %}
8993 size(4);
8994 ins_encode %{
8995 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
8996 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
8997 %}
8998 ins_pipe(pipe_class_default);
8999 %}
9001 // Register Or Long
9002 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9003 match(Set dst (OrL src1 src2));
9004 ins_cost(DEFAULT_COST);
9006 size(4);
9007 format %{ "OR $dst, $src1, $src2 \t// long" %}
9008 ins_encode %{
9009 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9010 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9011 %}
9012 ins_pipe(pipe_class_default);
9013 %}
9015 // OrL + ConvL2I.
9016 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9017 match(Set dst (ConvL2I (OrL src1 src2)));
9018 ins_cost(DEFAULT_COST);
9020 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9021 size(4);
9022 ins_encode %{
9023 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9024 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9025 %}
9026 ins_pipe(pipe_class_default);
9027 %}
9029 // Immediate Or long
9030 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9031 match(Set dst (OrL src1 con));
9032 ins_cost(DEFAULT_COST);
9034 format %{ "ORI $dst, $src1, $con \t// long" %}
9035 size(4);
9036 ins_encode %{
9037 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9038 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9039 %}
9040 ins_pipe(pipe_class_default);
9041 %}
9043 // Xor Instructions
9045 // Register Xor
9046 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9047 match(Set dst (XorI src1 src2));
9048 format %{ "XOR $dst, $src1, $src2" %}
9049 size(4);
9050 ins_encode %{
9051 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9052 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9053 %}
9054 ins_pipe(pipe_class_default);
9055 %}
9057 // Expand does not work with above instruct. (??)
9058 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9059 // no match-rule
9060 effect(DEF dst, USE src1, USE src2);
9061 format %{ "XOR $dst, $src1, $src2" %}
9062 size(4);
9063 ins_encode %{
9064 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9065 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9066 %}
9067 ins_pipe(pipe_class_default);
9068 %}
9070 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9071 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9072 ins_cost(DEFAULT_COST*3);
9074 expand %{
9075 // FIXME: we should do this in the ideal world.
9076 iRegIdst tmp1;
9077 iRegIdst tmp2;
9078 xorI_reg_reg(tmp1, src1, src2);
9079 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9080 xorI_reg_reg(dst, tmp1, tmp2);
9081 %}
9082 %}
9084 // Immediate Xor
9085 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9086 match(Set dst (XorI src1 src2));
9087 format %{ "XORI $dst, $src1, $src2" %}
9088 size(4);
9089 ins_encode %{
9090 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9091 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9092 %}
9093 ins_pipe(pipe_class_default);
9094 %}
9096 // Register Xor Long
9097 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9098 match(Set dst (XorL src1 src2));
9099 ins_cost(DEFAULT_COST);
9101 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9102 size(4);
9103 ins_encode %{
9104 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9105 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9106 %}
9107 ins_pipe(pipe_class_default);
9108 %}
9110 // XorL + ConvL2I.
9111 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9112 match(Set dst (ConvL2I (XorL src1 src2)));
9113 ins_cost(DEFAULT_COST);
9115 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9116 size(4);
9117 ins_encode %{
9118 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9119 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9120 %}
9121 ins_pipe(pipe_class_default);
9122 %}
9124 // Immediate Xor Long
9125 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9126 match(Set dst (XorL src1 src2));
9127 ins_cost(DEFAULT_COST);
9129 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9130 size(4);
9131 ins_encode %{
9132 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9133 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9134 %}
9135 ins_pipe(pipe_class_default);
9136 %}
9138 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9139 match(Set dst (XorI src1 src2));
9140 ins_cost(DEFAULT_COST);
9142 format %{ "NOT $dst, $src1 ($src2)" %}
9143 size(4);
9144 ins_encode %{
9145 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9146 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9147 %}
9148 ins_pipe(pipe_class_default);
9149 %}
9151 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9152 match(Set dst (XorL src1 src2));
9153 ins_cost(DEFAULT_COST);
9155 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9156 size(4);
9157 ins_encode %{
9158 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9159 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9160 %}
9161 ins_pipe(pipe_class_default);
9162 %}
9164 // And-complement
9165 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9166 match(Set dst (AndI (XorI src1 src2) src3));
9167 ins_cost(DEFAULT_COST);
9169 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9170 size(4);
9171 ins_encode( enc_andc(dst, src3, src1) );
9172 ins_pipe(pipe_class_default);
9173 %}
9175 // And-complement
9176 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9177 // no match-rule, false predicate
9178 effect(DEF dst, USE src1, USE src2);
9179 predicate(false);
9181 format %{ "ANDC $dst, $src1, $src2" %}
9182 size(4);
9183 ins_encode %{
9184 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9185 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9186 %}
9187 ins_pipe(pipe_class_default);
9188 %}
9190 //----------Moves between int/long and float/double----------------------------
9191 //
9192 // The following rules move values from int/long registers/stack-locations
9193 // to float/double registers/stack-locations and vice versa, without doing any
9194 // conversions. These rules are used to implement the bit-conversion methods
9195 // of java.lang.Float etc., e.g.
9196 // int floatToIntBits(float value)
9197 // float intBitsToFloat(int bits)
9198 //
9199 // Notes on the implementation on ppc64:
9200 // We only provide rules which move between a register and a stack-location,
9201 // because we always have to go through memory when moving between a float
9202 // register and an integer register.
9204 //---------- Chain stack slots between similar types --------
9206 // These are needed so that the rules below can match.
9208 // Load integer from stack slot
9209 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9210 match(Set dst src);
9211 ins_cost(MEMORY_REF_COST);
9213 format %{ "LWZ $dst, $src" %}
9214 size(4);
9215 ins_encode( enc_lwz(dst, src) );
9216 ins_pipe(pipe_class_memory);
9217 %}
9219 // Store integer to stack slot
9220 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9221 match(Set dst src);
9222 ins_cost(MEMORY_REF_COST);
9224 format %{ "STW $src, $dst \t// stk" %}
9225 size(4);
9226 ins_encode( enc_stw(src, dst) ); // rs=rt
9227 ins_pipe(pipe_class_memory);
9228 %}
9230 // Load long from stack slot
9231 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9232 match(Set dst src);
9233 ins_cost(MEMORY_REF_COST);
9235 format %{ "LD $dst, $src \t// long" %}
9236 size(4);
9237 ins_encode( enc_ld(dst, src) );
9238 ins_pipe(pipe_class_memory);
9239 %}
9241 // Store long to stack slot
9242 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9243 match(Set dst src);
9244 ins_cost(MEMORY_REF_COST);
9246 format %{ "STD $src, $dst \t// long" %}
9247 size(4);
9248 ins_encode( enc_std(src, dst) ); // rs=rt
9249 ins_pipe(pipe_class_memory);
9250 %}
9252 //----------Moves between int and float
9254 // Move float value from float stack-location to integer register.
9255 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9256 match(Set dst (MoveF2I src));
9257 ins_cost(MEMORY_REF_COST);
9259 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9260 size(4);
9261 ins_encode( enc_lwz(dst, src) );
9262 ins_pipe(pipe_class_memory);
9263 %}
9265 // Move float value from float register to integer stack-location.
9266 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9267 match(Set dst (MoveF2I src));
9268 ins_cost(MEMORY_REF_COST);
9270 format %{ "STFS $src, $dst \t// MoveF2I" %}
9271 size(4);
9272 ins_encode( enc_stfs(src, dst) );
9273 ins_pipe(pipe_class_memory);
9274 %}
9276 // Move integer value from integer stack-location to float register.
9277 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9278 match(Set dst (MoveI2F src));
9279 ins_cost(MEMORY_REF_COST);
9281 format %{ "LFS $dst, $src \t// MoveI2F" %}
9282 size(4);
9283 ins_encode %{
9284 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9285 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9286 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9287 %}
9288 ins_pipe(pipe_class_memory);
9289 %}
9291 // Move integer value from integer register to float stack-location.
9292 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9293 match(Set dst (MoveI2F src));
9294 ins_cost(MEMORY_REF_COST);
9296 format %{ "STW $src, $dst \t// MoveI2F" %}
9297 size(4);
9298 ins_encode( enc_stw(src, dst) );
9299 ins_pipe(pipe_class_memory);
9300 %}
9302 //----------Moves between long and float
9304 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9305 // no match-rule, false predicate
9306 effect(DEF dst, USE src);
9307 predicate(false);
9309 format %{ "storeD $src, $dst \t// STACK" %}
9310 size(4);
9311 ins_encode( enc_stfd(src, dst) );
9312 ins_pipe(pipe_class_default);
9313 %}
9315 //----------Moves between long and double
9317 // Move double value from double stack-location to long register.
9318 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9319 match(Set dst (MoveD2L src));
9320 ins_cost(MEMORY_REF_COST);
9321 size(4);
9322 format %{ "LD $dst, $src \t// MoveD2L" %}
9323 ins_encode( enc_ld(dst, src) );
9324 ins_pipe(pipe_class_memory);
9325 %}
9327 // Move double value from double register to long stack-location.
9328 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9329 match(Set dst (MoveD2L src));
9330 effect(DEF dst, USE src);
9331 ins_cost(MEMORY_REF_COST);
9333 format %{ "STFD $src, $dst \t// MoveD2L" %}
9334 size(4);
9335 ins_encode( enc_stfd(src, dst) );
9336 ins_pipe(pipe_class_memory);
9337 %}
9339 // Move long value from long stack-location to double register.
9340 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9341 match(Set dst (MoveL2D src));
9342 ins_cost(MEMORY_REF_COST);
9344 format %{ "LFD $dst, $src \t// MoveL2D" %}
9345 size(4);
9346 ins_encode( enc_lfd(dst, src) );
9347 ins_pipe(pipe_class_memory);
9348 %}
9350 // Move long value from long register to double stack-location.
9351 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9352 match(Set dst (MoveL2D src));
9353 ins_cost(MEMORY_REF_COST);
9355 format %{ "STD $src, $dst \t// MoveL2D" %}
9356 size(4);
9357 ins_encode( enc_std(src, dst) );
9358 ins_pipe(pipe_class_memory);
9359 %}
9361 //----------Register Move Instructions-----------------------------------------
9363 // Replicate for Superword
9365 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9366 predicate(false);
9367 effect(DEF dst, USE src);
9369 format %{ "MR $dst, $src \t// replicate " %}
9370 // variable size, 0 or 4.
9371 ins_encode %{
9372 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9373 __ mr_if_needed($dst$$Register, $src$$Register);
9374 %}
9375 ins_pipe(pipe_class_default);
9376 %}
9378 //----------Cast instructions (Java-level type cast)---------------------------
9380 // Cast Long to Pointer for unsafe natives.
9381 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9382 match(Set dst (CastX2P src));
9384 format %{ "MR $dst, $src \t// Long->Ptr" %}
9385 // variable size, 0 or 4.
9386 ins_encode %{
9387 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9388 __ mr_if_needed($dst$$Register, $src$$Register);
9389 %}
9390 ins_pipe(pipe_class_default);
9391 %}
9393 // Cast Pointer to Long for unsafe natives.
9394 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9395 match(Set dst (CastP2X src));
9397 format %{ "MR $dst, $src \t// Ptr->Long" %}
9398 // variable size, 0 or 4.
9399 ins_encode %{
9400 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9401 __ mr_if_needed($dst$$Register, $src$$Register);
9402 %}
9403 ins_pipe(pipe_class_default);
9404 %}
9406 instruct castPP(iRegPdst dst) %{
9407 match(Set dst (CastPP dst));
9408 format %{ " -- \t// castPP of $dst" %}
9409 size(0);
9410 ins_encode( /*empty*/ );
9411 ins_pipe(pipe_class_default);
9412 %}
9414 instruct castII(iRegIdst dst) %{
9415 match(Set dst (CastII dst));
9416 format %{ " -- \t// castII of $dst" %}
9417 size(0);
9418 ins_encode( /*empty*/ );
9419 ins_pipe(pipe_class_default);
9420 %}
9422 instruct checkCastPP(iRegPdst dst) %{
9423 match(Set dst (CheckCastPP dst));
9424 format %{ " -- \t// checkcastPP of $dst" %}
9425 size(0);
9426 ins_encode( /*empty*/ );
9427 ins_pipe(pipe_class_default);
9428 %}
9430 //----------Convert instructions-----------------------------------------------
9432 // Convert to boolean.
9434 // int_to_bool(src) : { 1 if src != 0
9435 // { 0 else
9436 //
9437 // strategy:
9438 // 1) Count leading zeros of 32 bit-value src,
9439 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9440 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9441 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9443 // convI2Bool
9444 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9445 match(Set dst (Conv2B src));
9446 predicate(UseCountLeadingZerosInstructionsPPC64);
9447 ins_cost(DEFAULT_COST);
9449 expand %{
9450 immI shiftAmount %{ 0x5 %}
9451 uimmI16 mask %{ 0x1 %}
9452 iRegIdst tmp1;
9453 iRegIdst tmp2;
9454 countLeadingZerosI(tmp1, src);
9455 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9456 xorI_reg_uimm16(dst, tmp2, mask);
9457 %}
9458 %}
9460 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9461 match(Set dst (Conv2B src));
9462 effect(TEMP crx);
9463 predicate(!UseCountLeadingZerosInstructionsPPC64);
9464 ins_cost(DEFAULT_COST);
9466 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9467 "LI $dst, #0\n\t"
9468 "BEQ $crx, done\n\t"
9469 "LI $dst, #1\n"
9470 "done:" %}
9471 size(16);
9472 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9473 ins_pipe(pipe_class_compare);
9474 %}
9476 // ConvI2B + XorI
9477 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9478 match(Set dst (XorI (Conv2B src) mask));
9479 predicate(UseCountLeadingZerosInstructionsPPC64);
9480 ins_cost(DEFAULT_COST);
9482 expand %{
9483 immI shiftAmount %{ 0x5 %}
9484 iRegIdst tmp1;
9485 countLeadingZerosI(tmp1, src);
9486 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9487 %}
9488 %}
9490 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9491 match(Set dst (XorI (Conv2B src) mask));
9492 effect(TEMP crx);
9493 predicate(!UseCountLeadingZerosInstructionsPPC64);
9494 ins_cost(DEFAULT_COST);
9496 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9497 "LI $dst, #1\n\t"
9498 "BEQ $crx, done\n\t"
9499 "LI $dst, #0\n"
9500 "done:" %}
9501 size(16);
9502 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9503 ins_pipe(pipe_class_compare);
9504 %}
9506 // AndI 0b0..010..0 + ConvI2B
9507 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9508 match(Set dst (Conv2B (AndI src mask)));
9509 predicate(UseRotateAndMaskInstructionsPPC64);
9510 ins_cost(DEFAULT_COST);
9512 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9513 size(4);
9514 ins_encode %{
9515 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9516 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9517 %}
9518 ins_pipe(pipe_class_default);
9519 %}
9521 // Convert pointer to boolean.
9522 //
9523 // ptr_to_bool(src) : { 1 if src != 0
9524 // { 0 else
9525 //
9526 // strategy:
9527 // 1) Count leading zeros of 64 bit-value src,
9528 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9529 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9530 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9532 // ConvP2B
9533 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9534 match(Set dst (Conv2B src));
9535 predicate(UseCountLeadingZerosInstructionsPPC64);
9536 ins_cost(DEFAULT_COST);
9538 expand %{
9539 immI shiftAmount %{ 0x6 %}
9540 uimmI16 mask %{ 0x1 %}
9541 iRegIdst tmp1;
9542 iRegIdst tmp2;
9543 countLeadingZerosP(tmp1, src);
9544 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9545 xorI_reg_uimm16(dst, tmp2, mask);
9546 %}
9547 %}
9549 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9550 match(Set dst (Conv2B src));
9551 effect(TEMP crx);
9552 predicate(!UseCountLeadingZerosInstructionsPPC64);
9553 ins_cost(DEFAULT_COST);
9555 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9556 "LI $dst, #0\n\t"
9557 "BEQ $crx, done\n\t"
9558 "LI $dst, #1\n"
9559 "done:" %}
9560 size(16);
9561 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9562 ins_pipe(pipe_class_compare);
9563 %}
9565 // ConvP2B + XorI
9566 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9567 match(Set dst (XorI (Conv2B src) mask));
9568 predicate(UseCountLeadingZerosInstructionsPPC64);
9569 ins_cost(DEFAULT_COST);
9571 expand %{
9572 immI shiftAmount %{ 0x6 %}
9573 iRegIdst tmp1;
9574 countLeadingZerosP(tmp1, src);
9575 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9576 %}
9577 %}
9579 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9580 match(Set dst (XorI (Conv2B src) mask));
9581 effect(TEMP crx);
9582 predicate(!UseCountLeadingZerosInstructionsPPC64);
9583 ins_cost(DEFAULT_COST);
9585 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9586 "LI $dst, #1\n\t"
9587 "BEQ $crx, done\n\t"
9588 "LI $dst, #0\n"
9589 "done:" %}
9590 size(16);
9591 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9592 ins_pipe(pipe_class_compare);
9593 %}
9595 // if src1 < src2, return -1 else return 0
9596 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9597 match(Set dst (CmpLTMask src1 src2));
9598 ins_cost(DEFAULT_COST*4);
9600 expand %{
9601 iRegIdst src1s;
9602 iRegIdst src2s;
9603 iRegIdst diff;
9604 sxtI_reg(src1s, src1); // ensure proper sign extention
9605 sxtI_reg(src2s, src2); // ensure proper sign extention
9606 subI_reg_reg(diff, src1s, src2s);
9607 // Need to consider >=33 bit result, therefore we need signmaskL.
9608 signmask64I_regI(dst, diff);
9609 %}
9610 %}
9612 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9613 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9614 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9615 size(4);
9616 ins_encode %{
9617 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9618 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9619 %}
9620 ins_pipe(pipe_class_default);
9621 %}
9623 //----------Arithmetic Conversion Instructions---------------------------------
9625 // Convert to Byte -- nop
9626 // Convert to Short -- nop
9628 // Convert to Int
9630 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9631 match(Set dst (RShiftI (LShiftI src amount) amount));
9632 format %{ "EXTSB $dst, $src \t// byte->int" %}
9633 size(4);
9634 ins_encode %{
9635 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9636 __ extsb($dst$$Register, $src$$Register);
9637 %}
9638 ins_pipe(pipe_class_default);
9639 %}
9641 // LShiftI 16 + RShiftI 16 converts short to int.
9642 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9643 match(Set dst (RShiftI (LShiftI src amount) amount));
9644 format %{ "EXTSH $dst, $src \t// short->int" %}
9645 size(4);
9646 ins_encode %{
9647 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9648 __ extsh($dst$$Register, $src$$Register);
9649 %}
9650 ins_pipe(pipe_class_default);
9651 %}
9653 // ConvL2I + ConvI2L: Sign extend int in long register.
9654 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9655 match(Set dst (ConvI2L (ConvL2I src)));
9657 format %{ "EXTSW $dst, $src \t// long->long" %}
9658 size(4);
9659 ins_encode %{
9660 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9661 __ extsw($dst$$Register, $src$$Register);
9662 %}
9663 ins_pipe(pipe_class_default);
9664 %}
9666 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9667 match(Set dst (ConvL2I src));
9668 format %{ "MR $dst, $src \t// long->int" %}
9669 // variable size, 0 or 4
9670 ins_encode %{
9671 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9672 __ mr_if_needed($dst$$Register, $src$$Register);
9673 %}
9674 ins_pipe(pipe_class_default);
9675 %}
9677 instruct convD2IRaw_regD(regD dst, regD src) %{
9678 // no match-rule, false predicate
9679 effect(DEF dst, USE src);
9680 predicate(false);
9682 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9683 size(4);
9684 ins_encode %{
9685 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9686 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9687 %}
9688 ins_pipe(pipe_class_default);
9689 %}
9691 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9692 // no match-rule, false predicate
9693 effect(DEF dst, USE crx, USE src);
9694 predicate(false);
9696 ins_variable_size_depending_on_alignment(true);
9698 format %{ "cmovI $crx, $dst, $src" %}
9699 // Worst case is branch + move + stop, no stop without scheduler.
9700 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9701 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9702 ins_pipe(pipe_class_default);
9703 %}
9705 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9706 // no match-rule, false predicate
9707 effect(DEF dst, USE crx, USE mem);
9708 predicate(false);
9710 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9711 postalloc_expand %{
9712 //
9713 // replaces
9714 //
9715 // region dst crx mem
9716 // \ | | /
9717 // dst=cmovI_bso_stackSlotL_conLvalue0
9718 //
9719 // with
9720 //
9721 // region dst
9722 // \ /
9723 // dst=loadConI16(0)
9724 // |
9725 // ^ region dst crx mem
9726 // | \ | | /
9727 // dst=cmovI_bso_stackSlotL
9728 //
9730 // Create new nodes.
9731 MachNode *m1 = new (C) loadConI16Node();
9732 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9734 // inputs for new nodes
9735 m1->add_req(n_region);
9736 m2->add_req(n_region, n_crx, n_mem);
9738 // precedences for new nodes
9739 m2->add_prec(m1);
9741 // operands for new nodes
9742 m1->_opnds[0] = op_dst;
9743 m1->_opnds[1] = new (C) immI16Oper(0);
9745 m2->_opnds[0] = op_dst;
9746 m2->_opnds[1] = op_crx;
9747 m2->_opnds[2] = op_mem;
9749 // registers for new nodes
9750 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9751 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9753 // Insert new nodes.
9754 nodes->push(m1);
9755 nodes->push(m2);
9756 %}
9757 %}
9759 // Double to Int conversion, NaN is mapped to 0.
9760 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9761 match(Set dst (ConvD2I src));
9762 ins_cost(DEFAULT_COST);
9764 expand %{
9765 regD tmpD;
9766 stackSlotL tmpS;
9767 flagsReg crx;
9768 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9769 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9770 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9771 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9772 %}
9773 %}
9775 instruct convF2IRaw_regF(regF dst, regF src) %{
9776 // no match-rule, false predicate
9777 effect(DEF dst, USE src);
9778 predicate(false);
9780 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9781 size(4);
9782 ins_encode %{
9783 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9784 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9785 %}
9786 ins_pipe(pipe_class_default);
9787 %}
9789 // Float to Int conversion, NaN is mapped to 0.
9790 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9791 match(Set dst (ConvF2I src));
9792 ins_cost(DEFAULT_COST);
9794 expand %{
9795 regF tmpF;
9796 stackSlotL tmpS;
9797 flagsReg crx;
9798 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9799 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9800 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9801 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9802 %}
9803 %}
9805 // Convert to Long
9807 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9808 match(Set dst (ConvI2L src));
9809 format %{ "EXTSW $dst, $src \t// int->long" %}
9810 size(4);
9811 ins_encode %{
9812 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9813 __ extsw($dst$$Register, $src$$Register);
9814 %}
9815 ins_pipe(pipe_class_default);
9816 %}
9818 // Zero-extend: convert unsigned int to long (convUI2L).
9819 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9820 match(Set dst (AndL (ConvI2L src) mask));
9821 ins_cost(DEFAULT_COST);
9823 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9824 size(4);
9825 ins_encode %{
9826 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9827 __ clrldi($dst$$Register, $src$$Register, 32);
9828 %}
9829 ins_pipe(pipe_class_default);
9830 %}
9832 // Zero-extend: convert unsigned int to long in long register.
9833 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9834 match(Set dst (AndL src mask));
9835 ins_cost(DEFAULT_COST);
9837 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9838 size(4);
9839 ins_encode %{
9840 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9841 __ clrldi($dst$$Register, $src$$Register, 32);
9842 %}
9843 ins_pipe(pipe_class_default);
9844 %}
9846 instruct convF2LRaw_regF(regF dst, regF src) %{
9847 // no match-rule, false predicate
9848 effect(DEF dst, USE src);
9849 predicate(false);
9851 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9852 size(4);
9853 ins_encode %{
9854 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9855 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9856 %}
9857 ins_pipe(pipe_class_default);
9858 %}
9860 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9861 // no match-rule, false predicate
9862 effect(DEF dst, USE crx, USE src);
9863 predicate(false);
9865 ins_variable_size_depending_on_alignment(true);
9867 format %{ "cmovL $crx, $dst, $src" %}
9868 // Worst case is branch + move + stop, no stop without scheduler.
9869 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9870 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9871 ins_pipe(pipe_class_default);
9872 %}
9874 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9875 // no match-rule, false predicate
9876 effect(DEF dst, USE crx, USE mem);
9877 predicate(false);
9879 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9880 postalloc_expand %{
9881 //
9882 // replaces
9883 //
9884 // region dst crx mem
9885 // \ | | /
9886 // dst=cmovL_bso_stackSlotL_conLvalue0
9887 //
9888 // with
9889 //
9890 // region dst
9891 // \ /
9892 // dst=loadConL16(0)
9893 // |
9894 // ^ region dst crx mem
9895 // | \ | | /
9896 // dst=cmovL_bso_stackSlotL
9897 //
9899 // Create new nodes.
9900 MachNode *m1 = new (C) loadConL16Node();
9901 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9903 // inputs for new nodes
9904 m1->add_req(n_region);
9905 m2->add_req(n_region, n_crx, n_mem);
9906 m2->add_prec(m1);
9908 // operands for new nodes
9909 m1->_opnds[0] = op_dst;
9910 m1->_opnds[1] = new (C) immL16Oper(0);
9911 m2->_opnds[0] = op_dst;
9912 m2->_opnds[1] = op_crx;
9913 m2->_opnds[2] = op_mem;
9915 // registers for new nodes
9916 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9917 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9919 // Insert new nodes.
9920 nodes->push(m1);
9921 nodes->push(m2);
9922 %}
9923 %}
9925 // Float to Long conversion, NaN is mapped to 0.
9926 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9927 match(Set dst (ConvF2L src));
9928 ins_cost(DEFAULT_COST);
9930 expand %{
9931 regF tmpF;
9932 stackSlotL tmpS;
9933 flagsReg crx;
9934 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9935 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9936 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9937 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9938 %}
9939 %}
9941 instruct convD2LRaw_regD(regD dst, regD src) %{
9942 // no match-rule, false predicate
9943 effect(DEF dst, USE src);
9944 predicate(false);
9946 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9947 size(4);
9948 ins_encode %{
9949 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9950 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9951 %}
9952 ins_pipe(pipe_class_default);
9953 %}
9955 // Double to Long conversion, NaN is mapped to 0.
9956 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9957 match(Set dst (ConvD2L src));
9958 ins_cost(DEFAULT_COST);
9960 expand %{
9961 regD tmpD;
9962 stackSlotL tmpS;
9963 flagsReg crx;
9964 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9965 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9966 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9967 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9968 %}
9969 %}
9971 // Convert to Float
9973 // Placed here as needed in expand.
9974 instruct convL2DRaw_regD(regD dst, regD src) %{
9975 // no match-rule, false predicate
9976 effect(DEF dst, USE src);
9977 predicate(false);
9979 format %{ "FCFID $dst, $src \t// convL2D" %}
9980 size(4);
9981 ins_encode %{
9982 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
9983 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
9984 %}
9985 ins_pipe(pipe_class_default);
9986 %}
9988 // Placed here as needed in expand.
9989 instruct convD2F_reg(regF dst, regD src) %{
9990 match(Set dst (ConvD2F src));
9991 format %{ "FRSP $dst, $src \t// convD2F" %}
9992 size(4);
9993 ins_encode %{
9994 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
9995 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
9996 %}
9997 ins_pipe(pipe_class_default);
9998 %}
10000 // Integer to Float conversion.
10001 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10002 match(Set dst (ConvI2F src));
10003 predicate(!VM_Version::has_fcfids());
10004 ins_cost(DEFAULT_COST);
10006 expand %{
10007 iRegLdst tmpL;
10008 stackSlotL tmpS;
10009 regD tmpD;
10010 regD tmpD2;
10011 convI2L_reg(tmpL, src); // Sign-extension int to long.
10012 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10013 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10014 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10015 convD2F_reg(dst, tmpD2); // Convert double to float.
10016 %}
10017 %}
10019 instruct convL2FRaw_regF(regF dst, regD src) %{
10020 // no match-rule, false predicate
10021 effect(DEF dst, USE src);
10022 predicate(false);
10024 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10025 size(4);
10026 ins_encode %{
10027 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10028 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10029 %}
10030 ins_pipe(pipe_class_default);
10031 %}
10033 // Integer to Float conversion. Special version for Power7.
10034 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10035 match(Set dst (ConvI2F src));
10036 predicate(VM_Version::has_fcfids());
10037 ins_cost(DEFAULT_COST);
10039 expand %{
10040 iRegLdst tmpL;
10041 stackSlotL tmpS;
10042 regD tmpD;
10043 convI2L_reg(tmpL, src); // Sign-extension int to long.
10044 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10045 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10046 convL2FRaw_regF(dst, tmpD); // Convert to float.
10047 %}
10048 %}
10050 // L2F to avoid runtime call.
10051 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10052 match(Set dst (ConvL2F src));
10053 predicate(VM_Version::has_fcfids());
10054 ins_cost(DEFAULT_COST);
10056 expand %{
10057 stackSlotL tmpS;
10058 regD tmpD;
10059 regL_to_stkL(tmpS, src); // Store long to stack.
10060 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10061 convL2FRaw_regF(dst, tmpD); // Convert to float.
10062 %}
10063 %}
10065 // Moved up as used in expand.
10066 //instruct convD2F_reg(regF dst, regD src) %{%}
10068 // Convert to Double
10070 // Integer to Double conversion.
10071 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10072 match(Set dst (ConvI2D src));
10073 ins_cost(DEFAULT_COST);
10075 expand %{
10076 iRegLdst tmpL;
10077 stackSlotL tmpS;
10078 regD tmpD;
10079 convI2L_reg(tmpL, src); // Sign-extension int to long.
10080 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10081 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10082 convL2DRaw_regD(dst, tmpD); // Convert to double.
10083 %}
10084 %}
10086 // Long to Double conversion
10087 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10088 match(Set dst (ConvL2D src));
10089 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10091 expand %{
10092 regD tmpD;
10093 moveL2D_stack_reg(tmpD, src);
10094 convL2DRaw_regD(dst, tmpD);
10095 %}
10096 %}
10098 instruct convF2D_reg(regD dst, regF src) %{
10099 match(Set dst (ConvF2D src));
10100 format %{ "FMR $dst, $src \t// float->double" %}
10101 // variable size, 0 or 4
10102 ins_encode %{
10103 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10104 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10105 %}
10106 ins_pipe(pipe_class_default);
10107 %}
10109 //----------Control Flow Instructions------------------------------------------
10110 // Compare Instructions
10112 // Compare Integers
10113 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10114 match(Set crx (CmpI src1 src2));
10115 size(4);
10116 format %{ "CMPW $crx, $src1, $src2" %}
10117 ins_encode %{
10118 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10119 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10120 %}
10121 ins_pipe(pipe_class_compare);
10122 %}
10124 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10125 match(Set crx (CmpI src1 src2));
10126 format %{ "CMPWI $crx, $src1, $src2" %}
10127 size(4);
10128 ins_encode %{
10129 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10130 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10131 %}
10132 ins_pipe(pipe_class_compare);
10133 %}
10135 // (src1 & src2) == 0?
10136 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10137 match(Set cr0 (CmpI (AndI src1 src2) zero));
10138 // r0 is killed
10139 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10140 size(4);
10141 ins_encode %{
10142 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10143 // FIXME: avoid andi_ ?
10144 __ andi_(R0, $src1$$Register, $src2$$constant);
10145 %}
10146 ins_pipe(pipe_class_compare);
10147 %}
10149 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10150 match(Set crx (CmpL src1 src2));
10151 format %{ "CMPD $crx, $src1, $src2" %}
10152 size(4);
10153 ins_encode %{
10154 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10155 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10156 %}
10157 ins_pipe(pipe_class_compare);
10158 %}
10160 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10161 match(Set crx (CmpL src1 src2));
10162 format %{ "CMPDI $crx, $src1, $src2" %}
10163 size(4);
10164 ins_encode %{
10165 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10166 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10167 %}
10168 ins_pipe(pipe_class_compare);
10169 %}
10171 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10172 match(Set cr0 (CmpL (AndL src1 src2) zero));
10173 // r0 is killed
10174 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10175 size(4);
10176 ins_encode %{
10177 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10178 __ and_(R0, $src1$$Register, $src2$$Register);
10179 %}
10180 ins_pipe(pipe_class_compare);
10181 %}
10183 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10184 match(Set cr0 (CmpL (AndL src1 src2) zero));
10185 // r0 is killed
10186 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10187 size(4);
10188 ins_encode %{
10189 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10190 // FIXME: avoid andi_ ?
10191 __ andi_(R0, $src1$$Register, $src2$$constant);
10192 %}
10193 ins_pipe(pipe_class_compare);
10194 %}
10196 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10197 // no match-rule, false predicate
10198 effect(DEF dst, USE crx);
10199 predicate(false);
10201 ins_variable_size_depending_on_alignment(true);
10203 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10204 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10205 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10206 ins_encode %{
10207 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10208 Label done;
10209 // li(Rdst, 0); // equal -> 0
10210 __ beq($crx$$CondRegister, done);
10211 __ li($dst$$Register, 1); // greater -> +1
10212 __ bgt($crx$$CondRegister, done);
10213 __ li($dst$$Register, -1); // unordered or less -> -1
10214 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10215 __ bind(done);
10216 %}
10217 ins_pipe(pipe_class_compare);
10218 %}
10220 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10221 // no match-rule, false predicate
10222 effect(DEF dst, USE crx);
10223 predicate(false);
10225 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10226 postalloc_expand %{
10227 //
10228 // replaces
10229 //
10230 // region crx
10231 // \ |
10232 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10233 //
10234 // with
10235 //
10236 // region
10237 // \
10238 // dst=loadConI16(0)
10239 // |
10240 // ^ region crx
10241 // | \ |
10242 // dst=cmovI_conIvalueMinus1_conIvalue1
10243 //
10245 // Create new nodes.
10246 MachNode *m1 = new (C) loadConI16Node();
10247 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10249 // inputs for new nodes
10250 m1->add_req(n_region);
10251 m2->add_req(n_region, n_crx);
10252 m2->add_prec(m1);
10254 // operands for new nodes
10255 m1->_opnds[0] = op_dst;
10256 m1->_opnds[1] = new (C) immI16Oper(0);
10257 m2->_opnds[0] = op_dst;
10258 m2->_opnds[1] = op_crx;
10260 // registers for new nodes
10261 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10262 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10264 // Insert new nodes.
10265 nodes->push(m1);
10266 nodes->push(m2);
10267 %}
10268 %}
10270 // Manifest a CmpL3 result in an integer register. Very painful.
10271 // This is the test to avoid.
10272 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10273 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10274 match(Set dst (CmpL3 src1 src2));
10275 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10277 expand %{
10278 flagsReg tmp1;
10279 cmpL_reg_reg(tmp1, src1, src2);
10280 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10281 %}
10282 %}
10284 // Implicit range checks.
10285 // A range check in the ideal world has one of the following shapes:
10286 // - (If le (CmpU length index)), (IfTrue throw exception)
10287 // - (If lt (CmpU index length)), (IfFalse throw exception)
10288 //
10289 // Match range check 'If le (CmpU length index)'.
10290 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10291 match(If cmp (CmpU src_length index));
10292 effect(USE labl);
10293 predicate(TrapBasedRangeChecks &&
10294 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10295 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10296 (Matcher::branches_to_uncommon_trap(_leaf)));
10298 ins_is_TrapBasedCheckNode(true);
10300 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10301 size(4);
10302 ins_encode %{
10303 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10304 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10305 __ trap_range_check_le($src_length$$Register, $index$$constant);
10306 } else {
10307 // Both successors are uncommon traps, probability is 0.
10308 // Node got flipped during fixup flow.
10309 assert($cmp$$cmpcode == 0x9, "must be greater");
10310 __ trap_range_check_g($src_length$$Register, $index$$constant);
10311 }
10312 %}
10313 ins_pipe(pipe_class_trap);
10314 %}
10316 // Match range check 'If lt (CmpU index length)'.
10317 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10318 match(If cmp (CmpU src_index src_length));
10319 effect(USE labl);
10320 predicate(TrapBasedRangeChecks &&
10321 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10322 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10323 (Matcher::branches_to_uncommon_trap(_leaf)));
10325 ins_is_TrapBasedCheckNode(true);
10327 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10328 size(4);
10329 ins_encode %{
10330 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10331 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10332 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10333 } else {
10334 // Both successors are uncommon traps, probability is 0.
10335 // Node got flipped during fixup flow.
10336 assert($cmp$$cmpcode == 0x8, "must be less");
10337 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10338 }
10339 %}
10340 ins_pipe(pipe_class_trap);
10341 %}
10343 // Match range check 'If lt (CmpU index length)'.
10344 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10345 match(If cmp (CmpU src_index length));
10346 effect(USE labl);
10347 predicate(TrapBasedRangeChecks &&
10348 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10349 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10350 (Matcher::branches_to_uncommon_trap(_leaf)));
10352 ins_is_TrapBasedCheckNode(true);
10354 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10355 size(4);
10356 ins_encode %{
10357 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10358 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10359 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10360 } else {
10361 // Both successors are uncommon traps, probability is 0.
10362 // Node got flipped during fixup flow.
10363 assert($cmp$$cmpcode == 0x8, "must be less");
10364 __ trap_range_check_l($src_index$$Register, $length$$constant);
10365 }
10366 %}
10367 ins_pipe(pipe_class_trap);
10368 %}
10370 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10371 match(Set crx (CmpU src1 src2));
10372 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10373 size(4);
10374 ins_encode %{
10375 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10376 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10377 %}
10378 ins_pipe(pipe_class_compare);
10379 %}
10381 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10382 match(Set crx (CmpU src1 src2));
10383 size(4);
10384 format %{ "CMPLWI $crx, $src1, $src2" %}
10385 ins_encode %{
10386 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10387 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10388 %}
10389 ins_pipe(pipe_class_compare);
10390 %}
10392 // Implicit zero checks (more implicit null checks).
10393 // No constant pool entries required.
10394 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10395 match(If cmp (CmpN value zero));
10396 effect(USE labl);
10397 predicate(TrapBasedNullChecks &&
10398 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10399 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10400 Matcher::branches_to_uncommon_trap(_leaf));
10401 ins_cost(1);
10403 ins_is_TrapBasedCheckNode(true);
10405 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10406 size(4);
10407 ins_encode %{
10408 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10409 if ($cmp$$cmpcode == 0xA) {
10410 __ trap_null_check($value$$Register);
10411 } else {
10412 // Both successors are uncommon traps, probability is 0.
10413 // Node got flipped during fixup flow.
10414 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10415 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10416 }
10417 %}
10418 ins_pipe(pipe_class_trap);
10419 %}
10421 // Compare narrow oops.
10422 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10423 match(Set crx (CmpN src1 src2));
10425 size(4);
10426 ins_cost(DEFAULT_COST);
10427 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10428 ins_encode %{
10429 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10430 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10431 %}
10432 ins_pipe(pipe_class_compare);
10433 %}
10435 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10436 match(Set crx (CmpN src1 src2));
10437 // Make this more expensive than zeroCheckN_iReg_imm0.
10438 ins_cost(DEFAULT_COST);
10440 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10441 size(4);
10442 ins_encode %{
10443 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10444 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10445 %}
10446 ins_pipe(pipe_class_compare);
10447 %}
10449 // Implicit zero checks (more implicit null checks).
10450 // No constant pool entries required.
10451 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10452 match(If cmp (CmpP value zero));
10453 effect(USE labl);
10454 predicate(TrapBasedNullChecks &&
10455 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10456 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10457 Matcher::branches_to_uncommon_trap(_leaf));
10459 ins_is_TrapBasedCheckNode(true);
10461 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10462 size(4);
10463 ins_encode %{
10464 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10465 if ($cmp$$cmpcode == 0xA) {
10466 __ trap_null_check($value$$Register);
10467 } else {
10468 // Both successors are uncommon traps, probability is 0.
10469 // Node got flipped during fixup flow.
10470 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10471 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10472 }
10473 %}
10474 ins_pipe(pipe_class_trap);
10475 %}
10477 // Compare Pointers
10478 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10479 match(Set crx (CmpP src1 src2));
10480 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10481 size(4);
10482 ins_encode %{
10483 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10484 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10485 %}
10486 ins_pipe(pipe_class_compare);
10487 %}
10489 // Used in postalloc expand.
10490 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10491 // This match rule prevents reordering of node before a safepoint.
10492 // This only makes sense if this instructions is used exclusively
10493 // for the expansion of EncodeP!
10494 match(Set crx (CmpP src1 src2));
10495 predicate(false);
10497 format %{ "CMPDI $crx, $src1, $src2" %}
10498 size(4);
10499 ins_encode %{
10500 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10501 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10502 %}
10503 ins_pipe(pipe_class_compare);
10504 %}
10506 //----------Float Compares----------------------------------------------------
10508 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10509 // no match-rule, false predicate
10510 effect(DEF crx, USE src1, USE src2);
10511 predicate(false);
10513 format %{ "cmpFUrd $crx, $src1, $src2" %}
10514 size(4);
10515 ins_encode %{
10516 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10517 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10518 %}
10519 ins_pipe(pipe_class_default);
10520 %}
10522 instruct cmov_bns_less(flagsReg crx) %{
10523 // no match-rule, false predicate
10524 effect(DEF crx);
10525 predicate(false);
10527 ins_variable_size_depending_on_alignment(true);
10529 format %{ "cmov $crx" %}
10530 // Worst case is branch + move + stop, no stop without scheduler.
10531 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10532 ins_encode %{
10533 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10534 Label done;
10535 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10536 __ li(R0, 0);
10537 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10538 // TODO PPC port __ endgroup_if_needed(_size == 16);
10539 __ bind(done);
10540 %}
10541 ins_pipe(pipe_class_default);
10542 %}
10544 // Compare floating, generate condition code.
10545 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10546 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10547 //
10548 // The following code sequence occurs a lot in mpegaudio:
10549 //
10550 // block BXX:
10551 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10552 // cmpFUrd CCR6, F11, F9
10553 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10554 // cmov CCR6
10555 // 8: instruct branchConSched:
10556 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10557 match(Set crx (CmpF src1 src2));
10558 ins_cost(DEFAULT_COST+BRANCH_COST);
10560 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10561 postalloc_expand %{
10562 //
10563 // replaces
10564 //
10565 // region src1 src2
10566 // \ | |
10567 // crx=cmpF_reg_reg
10568 //
10569 // with
10570 //
10571 // region src1 src2
10572 // \ | |
10573 // crx=cmpFUnordered_reg_reg
10574 // |
10575 // ^ region
10576 // | \
10577 // crx=cmov_bns_less
10578 //
10580 // Create new nodes.
10581 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10582 MachNode *m2 = new (C) cmov_bns_lessNode();
10584 // inputs for new nodes
10585 m1->add_req(n_region, n_src1, n_src2);
10586 m2->add_req(n_region);
10587 m2->add_prec(m1);
10589 // operands for new nodes
10590 m1->_opnds[0] = op_crx;
10591 m1->_opnds[1] = op_src1;
10592 m1->_opnds[2] = op_src2;
10593 m2->_opnds[0] = op_crx;
10595 // registers for new nodes
10596 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10597 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10599 // Insert new nodes.
10600 nodes->push(m1);
10601 nodes->push(m2);
10602 %}
10603 %}
10605 // Compare float, generate -1,0,1
10606 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10607 match(Set dst (CmpF3 src1 src2));
10608 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10610 expand %{
10611 flagsReg tmp1;
10612 cmpFUnordered_reg_reg(tmp1, src1, src2);
10613 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10614 %}
10615 %}
10617 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10618 // no match-rule, false predicate
10619 effect(DEF crx, USE src1, USE src2);
10620 predicate(false);
10622 format %{ "cmpFUrd $crx, $src1, $src2" %}
10623 size(4);
10624 ins_encode %{
10625 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10626 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10627 %}
10628 ins_pipe(pipe_class_default);
10629 %}
10631 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10632 match(Set crx (CmpD src1 src2));
10633 ins_cost(DEFAULT_COST+BRANCH_COST);
10635 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10636 postalloc_expand %{
10637 //
10638 // replaces
10639 //
10640 // region src1 src2
10641 // \ | |
10642 // crx=cmpD_reg_reg
10643 //
10644 // with
10645 //
10646 // region src1 src2
10647 // \ | |
10648 // crx=cmpDUnordered_reg_reg
10649 // |
10650 // ^ region
10651 // | \
10652 // crx=cmov_bns_less
10653 //
10655 // create new nodes
10656 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10657 MachNode *m2 = new (C) cmov_bns_lessNode();
10659 // inputs for new nodes
10660 m1->add_req(n_region, n_src1, n_src2);
10661 m2->add_req(n_region);
10662 m2->add_prec(m1);
10664 // operands for new nodes
10665 m1->_opnds[0] = op_crx;
10666 m1->_opnds[1] = op_src1;
10667 m1->_opnds[2] = op_src2;
10668 m2->_opnds[0] = op_crx;
10670 // registers for new nodes
10671 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10672 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10674 // Insert new nodes.
10675 nodes->push(m1);
10676 nodes->push(m2);
10677 %}
10678 %}
10680 // Compare double, generate -1,0,1
10681 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10682 match(Set dst (CmpD3 src1 src2));
10683 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10685 expand %{
10686 flagsReg tmp1;
10687 cmpDUnordered_reg_reg(tmp1, src1, src2);
10688 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10689 %}
10690 %}
10692 //----------Branches---------------------------------------------------------
10693 // Jump
10695 // Direct Branch.
10696 instruct branch(label labl) %{
10697 match(Goto);
10698 effect(USE labl);
10699 ins_cost(BRANCH_COST);
10701 format %{ "B $labl" %}
10702 size(4);
10703 ins_encode %{
10704 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10705 Label d; // dummy
10706 __ bind(d);
10707 Label* p = $labl$$label;
10708 // `p' is `NULL' when this encoding class is used only to
10709 // determine the size of the encoded instruction.
10710 Label& l = (NULL == p)? d : *(p);
10711 __ b(l);
10712 %}
10713 ins_pipe(pipe_class_default);
10714 %}
10716 // Conditional Near Branch
10717 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10718 // Same match rule as `branchConFar'.
10719 match(If cmp crx);
10720 effect(USE lbl);
10721 ins_cost(BRANCH_COST);
10723 // If set to 1 this indicates that the current instruction is a
10724 // short variant of a long branch. This avoids using this
10725 // instruction in first-pass matching. It will then only be used in
10726 // the `Shorten_branches' pass.
10727 ins_short_branch(1);
10729 format %{ "B$cmp $crx, $lbl" %}
10730 size(4);
10731 ins_encode( enc_bc(crx, cmp, lbl) );
10732 ins_pipe(pipe_class_default);
10733 %}
10735 // This is for cases when the ppc64 `bc' instruction does not
10736 // reach far enough. So we emit a far branch here, which is more
10737 // expensive.
10738 //
10739 // Conditional Far Branch
10740 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10741 // Same match rule as `branchCon'.
10742 match(If cmp crx);
10743 effect(USE crx, USE lbl);
10744 predicate(!false /* TODO: PPC port HB_Schedule*/);
10745 // Higher cost than `branchCon'.
10746 ins_cost(5*BRANCH_COST);
10748 // This is not a short variant of a branch, but the long variant.
10749 ins_short_branch(0);
10751 format %{ "B_FAR$cmp $crx, $lbl" %}
10752 size(8);
10753 ins_encode( enc_bc_far(crx, cmp, lbl) );
10754 ins_pipe(pipe_class_default);
10755 %}
10757 // Conditional Branch used with Power6 scheduler (can be far or short).
10758 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10759 // Same match rule as `branchCon'.
10760 match(If cmp crx);
10761 effect(USE crx, USE lbl);
10762 predicate(false /* TODO: PPC port HB_Schedule*/);
10763 // Higher cost than `branchCon'.
10764 ins_cost(5*BRANCH_COST);
10766 // Actually size doesn't depend on alignment but on shortening.
10767 ins_variable_size_depending_on_alignment(true);
10768 // long variant.
10769 ins_short_branch(0);
10771 format %{ "B_FAR$cmp $crx, $lbl" %}
10772 size(8); // worst case
10773 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10774 ins_pipe(pipe_class_default);
10775 %}
10777 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10778 match(CountedLoopEnd cmp crx);
10779 effect(USE labl);
10780 ins_cost(BRANCH_COST);
10782 // short variant.
10783 ins_short_branch(1);
10785 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10786 size(4);
10787 ins_encode( enc_bc(crx, cmp, labl) );
10788 ins_pipe(pipe_class_default);
10789 %}
10791 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10792 match(CountedLoopEnd cmp crx);
10793 effect(USE labl);
10794 predicate(!false /* TODO: PPC port HB_Schedule */);
10795 ins_cost(BRANCH_COST);
10797 // Long variant.
10798 ins_short_branch(0);
10800 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10801 size(8);
10802 ins_encode( enc_bc_far(crx, cmp, labl) );
10803 ins_pipe(pipe_class_default);
10804 %}
10806 // Conditional Branch used with Power6 scheduler (can be far or short).
10807 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10808 match(CountedLoopEnd cmp crx);
10809 effect(USE labl);
10810 predicate(false /* TODO: PPC port HB_Schedule */);
10811 // Higher cost than `branchCon'.
10812 ins_cost(5*BRANCH_COST);
10814 // Actually size doesn't depend on alignment but on shortening.
10815 ins_variable_size_depending_on_alignment(true);
10816 // Long variant.
10817 ins_short_branch(0);
10819 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10820 size(8); // worst case
10821 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10822 ins_pipe(pipe_class_default);
10823 %}
10825 // ============================================================================
10826 // Java runtime operations, intrinsics and other complex operations.
10828 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10829 // array for an instance of the superklass. Set a hidden internal cache on a
10830 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10831 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10832 //
10833 // GL TODO: Improve this.
10834 // - result should not be a TEMP
10835 // - Add match rule as on sparc avoiding additional Cmp.
10836 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10837 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10838 match(Set result (PartialSubtypeCheck subklass superklass));
10839 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10840 ins_cost(DEFAULT_COST*10);
10842 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10843 ins_encode %{
10844 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10845 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10846 $tmp_klass$$Register, NULL, $result$$Register);
10847 %}
10848 ins_pipe(pipe_class_default);
10849 %}
10851 // inlined locking and unlocking
10853 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10854 match(Set crx (FastLock oop box));
10855 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10856 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10858 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10859 ins_encode %{
10860 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10861 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10862 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10863 // If locking was successfull, crx should indicate 'EQ'.
10864 // The compiler generates a branch to the runtime call to
10865 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10866 %}
10867 ins_pipe(pipe_class_compare);
10868 %}
10870 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10871 match(Set crx (FastUnlock oop box));
10872 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10874 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10875 ins_encode %{
10876 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10877 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10878 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10879 // If unlocking was successfull, crx should indicate 'EQ'.
10880 // The compiler generates a branch to the runtime call to
10881 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10882 %}
10883 ins_pipe(pipe_class_compare);
10884 %}
10886 // Align address.
10887 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10888 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10890 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10891 size(4);
10892 ins_encode %{
10893 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10894 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10895 %}
10896 ins_pipe(pipe_class_default);
10897 %}
10899 // Array size computation.
10900 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10901 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10903 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10904 size(4);
10905 ins_encode %{
10906 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10907 __ subf($dst$$Register, $start$$Register, $end$$Register);
10908 %}
10909 ins_pipe(pipe_class_default);
10910 %}
10912 // Clear-array with dynamic array-size.
10913 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10914 match(Set dummy (ClearArray cnt base));
10915 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10916 ins_cost(MEMORY_REF_COST);
10918 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10920 format %{ "ClearArray $cnt, $base" %}
10921 ins_encode %{
10922 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10923 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10924 %}
10925 ins_pipe(pipe_class_default);
10926 %}
10928 // String_IndexOf for needle of length 1.
10929 //
10930 // Match needle into immediate operands: no loadConP node needed. Saves one
10931 // register and two instructions over string_indexOf_imm1Node.
10932 //
10933 // Assumes register result differs from all input registers.
10934 //
10935 // Preserves registers haystack, haycnt
10936 // Kills registers tmp1, tmp2
10937 // Defines registers result
10938 //
10939 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10940 //
10941 // Unfortunately this does not match too often. In many situations the AddP is used
10942 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10943 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10944 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10945 iRegIdst tmp1, iRegIdst tmp2,
10946 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10947 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10948 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10950 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10952 ins_cost(150);
10953 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10954 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10956 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10957 ins_encode %{
10958 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10959 immPOper *needleOper = (immPOper *)$needleImm;
10960 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10961 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10963 __ string_indexof_1($result$$Register,
10964 $haystack$$Register, $haycnt$$Register,
10965 R0, needle_values->char_at(0),
10966 $tmp1$$Register, $tmp2$$Register);
10967 %}
10968 ins_pipe(pipe_class_compare);
10969 %}
10971 // String_IndexOf for needle of length 1.
10972 //
10973 // Special case requires less registers and emits less instructions.
10974 //
10975 // Assumes register result differs from all input registers.
10976 //
10977 // Preserves registers haystack, haycnt
10978 // Kills registers tmp1, tmp2, needle
10979 // Defines registers result
10980 //
10981 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10982 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10983 rscratch2RegP needle, immI_1 needlecntImm,
10984 iRegIdst tmp1, iRegIdst tmp2,
10985 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10986 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10987 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
10988 TEMP tmp1, TEMP tmp2);
10989 // Required for EA: check if it is still a type_array.
10990 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
10991 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
10992 ins_cost(180);
10994 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10996 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
10997 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
10998 ins_encode %{
10999 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11000 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11001 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11002 guarantee(needle_values, "sanity");
11003 if (needle_values != NULL) {
11004 __ string_indexof_1($result$$Register,
11005 $haystack$$Register, $haycnt$$Register,
11006 R0, needle_values->char_at(0),
11007 $tmp1$$Register, $tmp2$$Register);
11008 } else {
11009 __ string_indexof_1($result$$Register,
11010 $haystack$$Register, $haycnt$$Register,
11011 $needle$$Register, 0,
11012 $tmp1$$Register, $tmp2$$Register);
11013 }
11014 %}
11015 ins_pipe(pipe_class_compare);
11016 %}
11018 // String_IndexOf.
11019 //
11020 // Length of needle as immediate. This saves instruction loading constant needle
11021 // length.
11022 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11023 // completely or do it in vector instruction. This should save registers for
11024 // needlecnt and needle.
11025 //
11026 // Assumes register result differs from all input registers.
11027 // Overwrites haycnt, needlecnt.
11028 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11029 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11030 iRegPsrc needle, uimmI15 needlecntImm,
11031 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11032 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11033 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11034 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11035 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11036 // Required for EA: check if it is still a type_array.
11037 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11038 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11039 ins_cost(250);
11041 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11043 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11044 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11045 ins_encode %{
11046 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11047 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11048 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11050 __ string_indexof($result$$Register,
11051 $haystack$$Register, $haycnt$$Register,
11052 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11053 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11054 %}
11055 ins_pipe(pipe_class_compare);
11056 %}
11058 // StrIndexOf node.
11059 //
11060 // Assumes register result differs from all input registers.
11061 // Overwrites haycnt, needlecnt.
11062 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11063 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11064 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11065 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11066 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11067 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11068 TEMP result,
11069 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11070 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11071 ins_cost(300);
11073 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11075 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11076 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11077 ins_encode %{
11078 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11079 __ string_indexof($result$$Register,
11080 $haystack$$Register, $haycnt$$Register,
11081 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11082 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11083 %}
11084 ins_pipe(pipe_class_compare);
11085 %}
11087 // String equals with immediate.
11088 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11089 iRegPdst tmp1, iRegPdst tmp2,
11090 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11091 match(Set result (StrEquals (Binary str1 str2) cntImm));
11092 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11093 KILL cr0, KILL cr6, KILL ctr);
11094 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11095 ins_cost(250);
11097 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11099 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11100 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11101 ins_encode %{
11102 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11103 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11104 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11105 %}
11106 ins_pipe(pipe_class_compare);
11107 %}
11109 // String equals.
11110 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11111 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11112 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11113 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11114 match(Set result (StrEquals (Binary str1 str2) cnt));
11115 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11116 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11117 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11118 ins_cost(300);
11120 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11122 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11123 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11124 ins_encode %{
11125 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11126 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11127 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11128 %}
11129 ins_pipe(pipe_class_compare);
11130 %}
11132 // String compare.
11133 // Char[] pointers are passed in.
11134 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11135 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11136 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11137 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11138 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11139 ins_cost(300);
11141 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11143 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11144 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11145 ins_encode %{
11146 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11147 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11148 $result$$Register, $tmp$$Register);
11149 %}
11150 ins_pipe(pipe_class_compare);
11151 %}
11153 //---------- Min/Max Instructions ---------------------------------------------
11155 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11156 match(Set dst (MinI src1 src2));
11157 ins_cost(DEFAULT_COST*6);
11159 expand %{
11160 iRegIdst src1s;
11161 iRegIdst src2s;
11162 iRegIdst diff;
11163 iRegIdst sm;
11164 iRegIdst doz; // difference or zero
11165 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11166 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11167 subI_reg_reg(diff, src2s, src1s);
11168 // Need to consider >=33 bit result, therefore we need signmaskL.
11169 signmask64I_regI(sm, diff);
11170 andI_reg_reg(doz, diff, sm); // <=0
11171 addI_reg_reg(dst, doz, src1s);
11172 %}
11173 %}
11175 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11176 match(Set dst (MaxI src1 src2));
11177 ins_cost(DEFAULT_COST*6);
11179 expand %{
11180 immI_minus1 m1 %{ -1 %}
11181 iRegIdst src1s;
11182 iRegIdst src2s;
11183 iRegIdst diff;
11184 iRegIdst sm;
11185 iRegIdst doz; // difference or zero
11186 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11187 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11188 subI_reg_reg(diff, src2s, src1s);
11189 // Need to consider >=33 bit result, therefore we need signmaskL.
11190 signmask64I_regI(sm, diff);
11191 andcI_reg_reg(doz, sm, m1, diff); // >=0
11192 addI_reg_reg(dst, doz, src1s);
11193 %}
11194 %}
11196 //---------- Population Count Instructions ------------------------------------
11198 // Popcnt for Power7.
11199 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11200 match(Set dst (PopCountI src));
11201 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11202 ins_cost(DEFAULT_COST);
11204 format %{ "POPCNTW $dst, $src" %}
11205 size(4);
11206 ins_encode %{
11207 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11208 __ popcntw($dst$$Register, $src$$Register);
11209 %}
11210 ins_pipe(pipe_class_default);
11211 %}
11213 // Popcnt for Power7.
11214 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11215 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11216 match(Set dst (PopCountL src));
11217 ins_cost(DEFAULT_COST);
11219 format %{ "POPCNTD $dst, $src" %}
11220 size(4);
11221 ins_encode %{
11222 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11223 __ popcntd($dst$$Register, $src$$Register);
11224 %}
11225 ins_pipe(pipe_class_default);
11226 %}
11228 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11229 match(Set dst (CountLeadingZerosI src));
11230 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11231 ins_cost(DEFAULT_COST);
11233 format %{ "CNTLZW $dst, $src" %}
11234 size(4);
11235 ins_encode %{
11236 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11237 __ cntlzw($dst$$Register, $src$$Register);
11238 %}
11239 ins_pipe(pipe_class_default);
11240 %}
11242 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11243 match(Set dst (CountLeadingZerosL src));
11244 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11245 ins_cost(DEFAULT_COST);
11247 format %{ "CNTLZD $dst, $src" %}
11248 size(4);
11249 ins_encode %{
11250 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11251 __ cntlzd($dst$$Register, $src$$Register);
11252 %}
11253 ins_pipe(pipe_class_default);
11254 %}
11256 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11257 // no match-rule, false predicate
11258 effect(DEF dst, USE src);
11259 predicate(false);
11261 format %{ "CNTLZD $dst, $src" %}
11262 size(4);
11263 ins_encode %{
11264 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11265 __ cntlzd($dst$$Register, $src$$Register);
11266 %}
11267 ins_pipe(pipe_class_default);
11268 %}
11270 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11271 match(Set dst (CountTrailingZerosI src));
11272 predicate(UseCountLeadingZerosInstructionsPPC64);
11273 ins_cost(DEFAULT_COST);
11275 expand %{
11276 immI16 imm1 %{ (int)-1 %}
11277 immI16 imm2 %{ (int)32 %}
11278 immI_minus1 m1 %{ -1 %}
11279 iRegIdst tmpI1;
11280 iRegIdst tmpI2;
11281 iRegIdst tmpI3;
11282 addI_reg_imm16(tmpI1, src, imm1);
11283 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11284 countLeadingZerosI(tmpI3, tmpI2);
11285 subI_imm16_reg(dst, imm2, tmpI3);
11286 %}
11287 %}
11289 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11290 match(Set dst (CountTrailingZerosL src));
11291 predicate(UseCountLeadingZerosInstructionsPPC64);
11292 ins_cost(DEFAULT_COST);
11294 expand %{
11295 immL16 imm1 %{ (long)-1 %}
11296 immI16 imm2 %{ (int)64 %}
11297 iRegLdst tmpL1;
11298 iRegLdst tmpL2;
11299 iRegIdst tmpL3;
11300 addL_reg_imm16(tmpL1, src, imm1);
11301 andcL_reg_reg(tmpL2, tmpL1, src);
11302 countLeadingZerosL(tmpL3, tmpL2);
11303 subI_imm16_reg(dst, imm2, tmpL3);
11304 %}
11305 %}
11307 // Expand nodes for byte_reverse_int.
11308 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11309 effect(DEF dst, USE src, USE pos, USE shift);
11310 predicate(false);
11312 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11313 size(4);
11314 ins_encode %{
11315 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11316 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11317 %}
11318 ins_pipe(pipe_class_default);
11319 %}
11321 // As insrwi_a, but with USE_DEF.
11322 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11323 effect(USE_DEF dst, USE src, USE pos, USE shift);
11324 predicate(false);
11326 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11327 size(4);
11328 ins_encode %{
11329 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11330 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11331 %}
11332 ins_pipe(pipe_class_default);
11333 %}
11335 // Just slightly faster than java implementation.
11336 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11337 match(Set dst (ReverseBytesI src));
11338 predicate(UseCountLeadingZerosInstructionsPPC64);
11339 ins_cost(DEFAULT_COST);
11341 expand %{
11342 immI16 imm24 %{ (int) 24 %}
11343 immI16 imm16 %{ (int) 16 %}
11344 immI16 imm8 %{ (int) 8 %}
11345 immI16 imm4 %{ (int) 4 %}
11346 immI16 imm0 %{ (int) 0 %}
11347 iRegLdst tmpI1;
11348 iRegLdst tmpI2;
11349 iRegLdst tmpI3;
11351 urShiftI_reg_imm(tmpI1, src, imm24);
11352 insrwi_a(dst, tmpI1, imm24, imm8);
11353 urShiftI_reg_imm(tmpI2, src, imm16);
11354 insrwi(dst, tmpI2, imm8, imm16);
11355 urShiftI_reg_imm(tmpI3, src, imm8);
11356 insrwi(dst, tmpI3, imm8, imm8);
11357 insrwi(dst, src, imm0, imm8);
11358 %}
11359 %}
11361 //---------- Replicate Vector Instructions ------------------------------------
11363 // Insrdi does replicate if src == dst.
11364 instruct repl32(iRegLdst dst) %{
11365 predicate(false);
11366 effect(USE_DEF dst);
11368 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11369 size(4);
11370 ins_encode %{
11371 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11372 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11373 %}
11374 ins_pipe(pipe_class_default);
11375 %}
11377 // Insrdi does replicate if src == dst.
11378 instruct repl48(iRegLdst dst) %{
11379 predicate(false);
11380 effect(USE_DEF dst);
11382 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11383 size(4);
11384 ins_encode %{
11385 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11386 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11387 %}
11388 ins_pipe(pipe_class_default);
11389 %}
11391 // Insrdi does replicate if src == dst.
11392 instruct repl56(iRegLdst dst) %{
11393 predicate(false);
11394 effect(USE_DEF dst);
11396 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11397 size(4);
11398 ins_encode %{
11399 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11400 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11401 %}
11402 ins_pipe(pipe_class_default);
11403 %}
11405 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11406 match(Set dst (ReplicateB src));
11407 predicate(n->as_Vector()->length() == 8);
11408 expand %{
11409 moveReg(dst, src);
11410 repl56(dst);
11411 repl48(dst);
11412 repl32(dst);
11413 %}
11414 %}
11416 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11417 match(Set dst (ReplicateB zero));
11418 predicate(n->as_Vector()->length() == 8);
11419 format %{ "LI $dst, #0 \t// replicate8B" %}
11420 size(4);
11421 ins_encode %{
11422 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11423 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11424 %}
11425 ins_pipe(pipe_class_default);
11426 %}
11428 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11429 match(Set dst (ReplicateB src));
11430 predicate(n->as_Vector()->length() == 8);
11431 format %{ "LI $dst, #-1 \t// replicate8B" %}
11432 size(4);
11433 ins_encode %{
11434 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11435 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11436 %}
11437 ins_pipe(pipe_class_default);
11438 %}
11440 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11441 match(Set dst (ReplicateS src));
11442 predicate(n->as_Vector()->length() == 4);
11443 expand %{
11444 moveReg(dst, src);
11445 repl48(dst);
11446 repl32(dst);
11447 %}
11448 %}
11450 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11451 match(Set dst (ReplicateS zero));
11452 predicate(n->as_Vector()->length() == 4);
11453 format %{ "LI $dst, #0 \t// replicate4C" %}
11454 size(4);
11455 ins_encode %{
11456 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11457 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11458 %}
11459 ins_pipe(pipe_class_default);
11460 %}
11462 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11463 match(Set dst (ReplicateS src));
11464 predicate(n->as_Vector()->length() == 4);
11465 format %{ "LI $dst, -1 \t// replicate4C" %}
11466 size(4);
11467 ins_encode %{
11468 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11469 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11470 %}
11471 ins_pipe(pipe_class_default);
11472 %}
11474 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11475 match(Set dst (ReplicateI src));
11476 predicate(n->as_Vector()->length() == 2);
11477 ins_cost(2 * DEFAULT_COST);
11478 expand %{
11479 moveReg(dst, src);
11480 repl32(dst);
11481 %}
11482 %}
11484 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11485 match(Set dst (ReplicateI zero));
11486 predicate(n->as_Vector()->length() == 2);
11487 format %{ "LI $dst, #0 \t// replicate4C" %}
11488 size(4);
11489 ins_encode %{
11490 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11491 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11492 %}
11493 ins_pipe(pipe_class_default);
11494 %}
11496 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11497 match(Set dst (ReplicateI src));
11498 predicate(n->as_Vector()->length() == 2);
11499 format %{ "LI $dst, -1 \t// replicate4C" %}
11500 size(4);
11501 ins_encode %{
11502 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11503 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11504 %}
11505 ins_pipe(pipe_class_default);
11506 %}
11508 // Move float to int register via stack, replicate.
11509 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11510 match(Set dst (ReplicateF src));
11511 predicate(n->as_Vector()->length() == 2);
11512 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11513 expand %{
11514 stackSlotL tmpS;
11515 iRegIdst tmpI;
11516 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11517 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11518 moveReg(dst, tmpI); // Move int to long reg.
11519 repl32(dst); // Replicate bitpattern.
11520 %}
11521 %}
11523 // Replicate scalar constant to packed float values in Double register
11524 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11525 match(Set dst (ReplicateF src));
11526 predicate(n->as_Vector()->length() == 2);
11527 ins_cost(5 * DEFAULT_COST);
11529 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11530 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11531 %}
11533 // Replicate scalar zero constant to packed float values in Double register
11534 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11535 match(Set dst (ReplicateF zero));
11536 predicate(n->as_Vector()->length() == 2);
11538 format %{ "LI $dst, #0 \t// replicate2F" %}
11539 ins_encode %{
11540 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11541 __ li($dst$$Register, 0x0);
11542 %}
11543 ins_pipe(pipe_class_default);
11544 %}
11546 // ============================================================================
11547 // Safepoint Instruction
11549 instruct safePoint_poll(iRegPdst poll) %{
11550 match(SafePoint poll);
11551 predicate(LoadPollAddressFromThread);
11553 // It caused problems to add the effect that r0 is killed, but this
11554 // effect no longer needs to be mentioned, since r0 is not contained
11555 // in a reg_class.
11557 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11558 size(4);
11559 ins_encode( enc_poll(0x0, poll) );
11560 ins_pipe(pipe_class_default);
11561 %}
11563 // Safepoint without per-thread support. Load address of page to poll
11564 // as constant.
11565 // Rscratch2RegP is R12.
11566 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11567 // a seperate node so that the oop map is at the right location.
11568 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11569 match(SafePoint poll);
11570 predicate(!LoadPollAddressFromThread);
11572 // It caused problems to add the effect that r0 is killed, but this
11573 // effect no longer needs to be mentioned, since r0 is not contained
11574 // in a reg_class.
11576 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11577 ins_encode( enc_poll(0x0, poll) );
11578 ins_pipe(pipe_class_default);
11579 %}
11581 // ============================================================================
11582 // Call Instructions
11584 // Call Java Static Instruction
11586 // Schedulable version of call static node.
11587 instruct CallStaticJavaDirect(method meth) %{
11588 match(CallStaticJava);
11589 effect(USE meth);
11590 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11591 ins_cost(CALL_COST);
11593 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11595 format %{ "CALL,static $meth \t// ==> " %}
11596 size(4);
11597 ins_encode( enc_java_static_call(meth) );
11598 ins_pipe(pipe_class_call);
11599 %}
11601 // Schedulable version of call static node.
11602 instruct CallStaticJavaDirectHandle(method meth) %{
11603 match(CallStaticJava);
11604 effect(USE meth);
11605 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11606 ins_cost(CALL_COST);
11608 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11610 format %{ "CALL,static $meth \t// ==> " %}
11611 ins_encode( enc_java_handle_call(meth) );
11612 ins_pipe(pipe_class_call);
11613 %}
11615 // Call Java Dynamic Instruction
11617 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11618 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11619 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11620 // The call destination must still be placed in the constant pool.
11621 instruct CallDynamicJavaDirectSched(method meth) %{
11622 match(CallDynamicJava); // To get all the data fields we need ...
11623 effect(USE meth);
11624 predicate(false); // ... but never match.
11626 ins_field_load_ic_hi_node(loadConL_hiNode*);
11627 ins_field_load_ic_node(loadConLNode*);
11628 ins_num_consts(1 /* 1 patchable constant: call destination */);
11630 format %{ "BL \t// dynamic $meth ==> " %}
11631 size(4);
11632 ins_encode( enc_java_dynamic_call_sched(meth) );
11633 ins_pipe(pipe_class_call);
11634 %}
11636 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11637 // We use postalloc expanded calls if we use inline caches
11638 // and do not update method data.
11639 //
11640 // This instruction has two constants: inline cache (IC) and call destination.
11641 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11642 // one constant.
11643 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11644 match(CallDynamicJava);
11645 effect(USE meth);
11646 predicate(UseInlineCaches);
11647 ins_cost(CALL_COST);
11649 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11651 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11652 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11653 %}
11655 // Compound version of call dynamic java
11656 // We use postalloc expanded calls if we use inline caches
11657 // and do not update method data.
11658 instruct CallDynamicJavaDirect(method meth) %{
11659 match(CallDynamicJava);
11660 effect(USE meth);
11661 predicate(!UseInlineCaches);
11662 ins_cost(CALL_COST);
11664 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11665 ins_num_consts(4);
11667 format %{ "CALL,dynamic $meth \t// ==> " %}
11668 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11669 ins_pipe(pipe_class_call);
11670 %}
11672 // Call Runtime Instruction
11674 instruct CallRuntimeDirect(method meth) %{
11675 match(CallRuntime);
11676 effect(USE meth);
11677 ins_cost(CALL_COST);
11679 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11680 // env for callee, C-toc.
11681 ins_num_consts(3);
11683 format %{ "CALL,runtime" %}
11684 ins_encode( enc_java_to_runtime_call(meth) );
11685 ins_pipe(pipe_class_call);
11686 %}
11688 // Call Leaf
11690 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11691 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11692 effect(DEF dst, USE src);
11694 ins_num_consts(1);
11696 format %{ "MTCTR $src" %}
11697 size(4);
11698 ins_encode( enc_leaf_call_mtctr(src) );
11699 ins_pipe(pipe_class_default);
11700 %}
11702 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11703 instruct CallLeafDirect(method meth) %{
11704 match(CallLeaf); // To get the data all the data fields we need ...
11705 effect(USE meth);
11706 predicate(false); // but never match.
11708 format %{ "BCTRL \t// leaf call $meth ==> " %}
11709 size(4);
11710 ins_encode %{
11711 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11712 __ bctrl();
11713 %}
11714 ins_pipe(pipe_class_call);
11715 %}
11717 // postalloc expand of CallLeafDirect.
11718 // Load adress to call from TOC, then bl to it.
11719 instruct CallLeafDirect_Ex(method meth) %{
11720 match(CallLeaf);
11721 effect(USE meth);
11722 ins_cost(CALL_COST);
11724 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11725 // env for callee, C-toc.
11726 ins_num_consts(3);
11728 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11729 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11730 %}
11732 // Call runtime without safepoint - same as CallLeaf.
11733 // postalloc expand of CallLeafNoFPDirect.
11734 // Load adress to call from TOC, then bl to it.
11735 instruct CallLeafNoFPDirect_Ex(method meth) %{
11736 match(CallLeafNoFP);
11737 effect(USE meth);
11738 ins_cost(CALL_COST);
11740 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11741 // env for callee, C-toc.
11742 ins_num_consts(3);
11744 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11745 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11746 %}
11748 // Tail Call; Jump from runtime stub to Java code.
11749 // Also known as an 'interprocedural jump'.
11750 // Target of jump will eventually return to caller.
11751 // TailJump below removes the return address.
11752 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11753 match(TailCall jump_target method_oop);
11754 ins_cost(CALL_COST);
11756 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11757 "BCTR \t// tail call" %}
11758 size(8);
11759 ins_encode %{
11760 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11761 __ mtctr($jump_target$$Register);
11762 __ bctr();
11763 %}
11764 ins_pipe(pipe_class_call);
11765 %}
11767 // Return Instruction
11768 instruct Ret() %{
11769 match(Return);
11770 format %{ "BLR \t// branch to link register" %}
11771 size(4);
11772 ins_encode %{
11773 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11774 // LR is restored in MachEpilogNode. Just do the RET here.
11775 __ blr();
11776 %}
11777 ins_pipe(pipe_class_default);
11778 %}
11780 // Tail Jump; remove the return address; jump to target.
11781 // TailCall above leaves the return address around.
11782 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11783 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11784 // "restore" before this instruction (in Epilogue), we need to materialize it
11785 // in %i0.
11786 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11787 match(TailJump jump_target ex_oop);
11788 ins_cost(CALL_COST);
11790 format %{ "LD R4_ARG2 = LR\n\t"
11791 "MTCTR $jump_target\n\t"
11792 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11793 size(12);
11794 ins_encode %{
11795 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11796 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11797 __ mtctr($jump_target$$Register);
11798 __ bctr();
11799 %}
11800 ins_pipe(pipe_class_call);
11801 %}
11803 // Create exception oop: created by stack-crawling runtime code.
11804 // Created exception is now available to this handler, and is setup
11805 // just prior to jumping to this handler. No code emitted.
11806 instruct CreateException(rarg1RegP ex_oop) %{
11807 match(Set ex_oop (CreateEx));
11808 ins_cost(0);
11810 format %{ " -- \t// exception oop; no code emitted" %}
11811 size(0);
11812 ins_encode( /*empty*/ );
11813 ins_pipe(pipe_class_default);
11814 %}
11816 // Rethrow exception: The exception oop will come in the first
11817 // argument position. Then JUMP (not call) to the rethrow stub code.
11818 instruct RethrowException() %{
11819 match(Rethrow);
11820 ins_cost(CALL_COST);
11822 format %{ "Jmp rethrow_stub" %}
11823 ins_encode %{
11824 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11825 cbuf.set_insts_mark();
11826 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11827 %}
11828 ins_pipe(pipe_class_call);
11829 %}
11831 // Die now.
11832 instruct ShouldNotReachHere() %{
11833 match(Halt);
11834 ins_cost(CALL_COST);
11836 format %{ "ShouldNotReachHere" %}
11837 size(4);
11838 ins_encode %{
11839 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11840 __ trap_should_not_reach_here();
11841 %}
11842 ins_pipe(pipe_class_default);
11843 %}
11845 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11846 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11847 // Get a DEF on threadRegP, no costs, no encoding, use
11848 // 'ins_should_rematerialize(true)' to avoid spilling.
11849 instruct tlsLoadP(threadRegP dst) %{
11850 match(Set dst (ThreadLocal));
11851 ins_cost(0);
11853 ins_should_rematerialize(true);
11855 format %{ " -- \t// $dst=Thread::current(), empty" %}
11856 size(0);
11857 ins_encode( /*empty*/ );
11858 ins_pipe(pipe_class_empty);
11859 %}
11861 //---Some PPC specific nodes---------------------------------------------------
11863 // Stop a group.
11864 instruct endGroup() %{
11865 ins_cost(0);
11867 ins_is_nop(true);
11869 format %{ "End Bundle (ori r1, r1, 0)" %}
11870 size(4);
11871 ins_encode %{
11872 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11873 __ endgroup();
11874 %}
11875 ins_pipe(pipe_class_default);
11876 %}
11878 // Nop instructions
11880 instruct fxNop() %{
11881 ins_cost(0);
11883 ins_is_nop(true);
11885 format %{ "fxNop" %}
11886 size(4);
11887 ins_encode %{
11888 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11889 __ nop();
11890 %}
11891 ins_pipe(pipe_class_default);
11892 %}
11894 instruct fpNop0() %{
11895 ins_cost(0);
11897 ins_is_nop(true);
11899 format %{ "fpNop0" %}
11900 size(4);
11901 ins_encode %{
11902 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11903 __ fpnop0();
11904 %}
11905 ins_pipe(pipe_class_default);
11906 %}
11908 instruct fpNop1() %{
11909 ins_cost(0);
11911 ins_is_nop(true);
11913 format %{ "fpNop1" %}
11914 size(4);
11915 ins_encode %{
11916 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11917 __ fpnop1();
11918 %}
11919 ins_pipe(pipe_class_default);
11920 %}
11922 instruct brNop0() %{
11923 ins_cost(0);
11924 size(4);
11925 format %{ "brNop0" %}
11926 ins_encode %{
11927 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11928 __ brnop0();
11929 %}
11930 ins_is_nop(true);
11931 ins_pipe(pipe_class_default);
11932 %}
11934 instruct brNop1() %{
11935 ins_cost(0);
11937 ins_is_nop(true);
11939 format %{ "brNop1" %}
11940 size(4);
11941 ins_encode %{
11942 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11943 __ brnop1();
11944 %}
11945 ins_pipe(pipe_class_default);
11946 %}
11948 instruct brNop2() %{
11949 ins_cost(0);
11951 ins_is_nop(true);
11953 format %{ "brNop2" %}
11954 size(4);
11955 ins_encode %{
11956 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11957 __ brnop2();
11958 %}
11959 ins_pipe(pipe_class_default);
11960 %}
11962 //----------PEEPHOLE RULES-----------------------------------------------------
11963 // These must follow all instruction definitions as they use the names
11964 // defined in the instructions definitions.
11965 //
11966 // peepmatch ( root_instr_name [preceeding_instruction]* );
11967 //
11968 // peepconstraint %{
11969 // (instruction_number.operand_name relational_op instruction_number.operand_name
11970 // [, ...] );
11971 // // instruction numbers are zero-based using left to right order in peepmatch
11972 //
11973 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11974 // // provide an instruction_number.operand_name for each operand that appears
11975 // // in the replacement instruction's match rule
11976 //
11977 // ---------VM FLAGS---------------------------------------------------------
11978 //
11979 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11980 //
11981 // Each peephole rule is given an identifying number starting with zero and
11982 // increasing by one in the order seen by the parser. An individual peephole
11983 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11984 // on the command-line.
11985 //
11986 // ---------CURRENT LIMITATIONS----------------------------------------------
11987 //
11988 // Only match adjacent instructions in same basic block
11989 // Only equality constraints
11990 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11991 // Only one replacement instruction
11992 //
11993 // ---------EXAMPLE----------------------------------------------------------
11994 //
11995 // // pertinent parts of existing instructions in architecture description
11996 // instruct movI(eRegI dst, eRegI src) %{
11997 // match(Set dst (CopyI src));
11998 // %}
11999 //
12000 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12001 // match(Set dst (AddI dst src));
12002 // effect(KILL cr);
12003 // %}
12004 //
12005 // // Change (inc mov) to lea
12006 // peephole %{
12007 // // increment preceeded by register-register move
12008 // peepmatch ( incI_eReg movI );
12009 // // require that the destination register of the increment
12010 // // match the destination register of the move
12011 // peepconstraint ( 0.dst == 1.dst );
12012 // // construct a replacement instruction that sets
12013 // // the destination to ( move's source register + one )
12014 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12015 // %}
12016 //
12017 // Implementation no longer uses movX instructions since
12018 // machine-independent system no longer uses CopyX nodes.
12019 //
12020 // peephole %{
12021 // peepmatch ( incI_eReg movI );
12022 // peepconstraint ( 0.dst == 1.dst );
12023 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12024 // %}
12025 //
12026 // peephole %{
12027 // peepmatch ( decI_eReg movI );
12028 // peepconstraint ( 0.dst == 1.dst );
12029 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12030 // %}
12031 //
12032 // peephole %{
12033 // peepmatch ( addI_eReg_imm movI );
12034 // peepconstraint ( 0.dst == 1.dst );
12035 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12036 // %}
12037 //
12038 // peephole %{
12039 // peepmatch ( addP_eReg_imm movP );
12040 // peepconstraint ( 0.dst == 1.dst );
12041 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12042 // %}
12044 // // Change load of spilled value to only a spill
12045 // instruct storeI(memory mem, eRegI src) %{
12046 // match(Set mem (StoreI mem src));
12047 // %}
12048 //
12049 // instruct loadI(eRegI dst, memory mem) %{
12050 // match(Set dst (LoadI mem));
12051 // %}
12052 //
12053 peephole %{
12054 peepmatch ( loadI storeI );
12055 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12056 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12057 %}
12059 peephole %{
12060 peepmatch ( loadL storeL );
12061 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12062 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12063 %}
12065 peephole %{
12066 peepmatch ( loadP storeP );
12067 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12068 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12069 %}
12071 //----------SMARTSPILL RULES---------------------------------------------------
12072 // These must follow all instruction definitions as they use the names
12073 // defined in the instructions definitions.