Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Mon Sep 18 15:15:14 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Wed Sep 20 09:24:48 2017 +0800
     1.3 @@ -1322,11 +1322,6 @@
     1.4      // accessing M[reg] w/o changing any (non-CC) registers
     1.5      // NOTE: cmpl is plenty here to provoke a segv
     1.6      lw(AT, reg, 0);
     1.7 -/* Jin
     1.8 -    nop();
     1.9 -    nop();
    1.10 -    nop();
    1.11 -*/
    1.12      // Note: should probably use testl(rax, Address(reg, 0));
    1.13      //       may be shorter code (however, this version of
    1.14      //       testl needs to be implemented first)

     2.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Mon Sep 18 15:15:14 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 09:24:48 2017 +0800
     2.3 @@ -208,8 +208,6 @@
     2.4    } else {
     2.5      __ move(FSR, value);
     2.6    }
     2.7 -  assert(value >= 0, "check this code");
     2.8 -  //__ move(SSR, R0);
     2.9  }
    2.10  
    2.11  void TemplateTable::fconst(int value) {
    2.12 @@ -1456,7 +1454,6 @@
    2.13      __ bind(L);
    2.14    }
    2.15  #endif
    2.16 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    2.17    __ dsllv(FSR, T0, FSR);
    2.18  }
    2.19  
    2.20 @@ -1473,7 +1470,6 @@
    2.21      __ bind(L);
    2.22    }
    2.23  #endif
    2.24 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    2.25    __ dsrav(FSR, T0, FSR);
    2.26  }
    2.27  
    2.28 @@ -1490,7 +1486,6 @@
    2.29      __ bind(L);
    2.30    }
    2.31  #endif
    2.32 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    2.33    __ dsrlv(FSR, T0, FSR);
    2.34  }
    2.35