src/cpu/mips/vm/templateTable_mips_64.cpp

changeset 6886
2fa8027581f6
parent 6885
75ee8543b584
child 6887
59aca571c8d0
     1.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Mon Sep 18 15:15:14 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 09:24:48 2017 +0800
     1.3 @@ -208,8 +208,6 @@
     1.4    } else {
     1.5      __ move(FSR, value);
     1.6    }
     1.7 -  assert(value >= 0, "check this code");
     1.8 -  //__ move(SSR, R0);
     1.9  }
    1.10  
    1.11  void TemplateTable::fconst(int value) {
    1.12 @@ -1456,7 +1454,6 @@
    1.13      __ bind(L);
    1.14    }
    1.15  #endif
    1.16 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    1.17    __ dsllv(FSR, T0, FSR);
    1.18  }
    1.19  
    1.20 @@ -1473,7 +1470,6 @@
    1.21      __ bind(L);
    1.22    }
    1.23  #endif
    1.24 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    1.25    __ dsrav(FSR, T0, FSR);
    1.26  }
    1.27  
    1.28 @@ -1490,7 +1486,6 @@
    1.29      __ bind(L);
    1.30    }
    1.31  #endif
    1.32 -  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
    1.33    __ dsrlv(FSR, T0, FSR);
    1.34  }
    1.35  

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