Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 09:24:48 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 09:38:17 2017 +0800
     1.3 @@ -506,7 +506,6 @@
     1.4    transition(vtos, dtos);
     1.5    locals_index(T2);
     1.6    __ ldc1(FSF, T2, -wordSize);
     1.7 -  __ ldc1(SSF, T2, 0);
     1.8  }
     1.9  
    1.10  // used register T2
    1.11 @@ -1272,44 +1271,18 @@
    1.12  
    1.13  void TemplateTable::iop2(Operation op) {
    1.14    transition(itos, itos);
    1.15 +
    1.16 +  __ pop_i(SSR);
    1.17    switch (op) {
    1.18 -    case add  :
    1.19 -      __ pop_i(SSR);
    1.20 -      __ addu32(FSR, SSR, FSR);
    1.21 -      break;
    1.22 -    case sub  :
    1.23 -      __ pop_i(SSR);
    1.24 -      __ subu32(FSR, SSR, FSR);
    1.25 -      break;
    1.26 -    case mul  :
    1.27 -      __ lw(SSR, SP, 0);
    1.28 -      __ daddi(SP, SP, wordSize);
    1.29 -                        __ mul(FSR, SSR, FSR);
    1.30 -      break;
    1.31 -    case _and :
    1.32 -      __ pop_i(SSR);
    1.33 -      __ andr(FSR, SSR, FSR);
    1.34 -      break;
    1.35 -    case _or  :
    1.36 -      __ pop_i(SSR);
    1.37 -      __ orr(FSR, SSR, FSR);
    1.38 -      break;
    1.39 -    case _xor :
    1.40 -      __ pop_i(SSR);
    1.41 -      __ xorr(FSR, SSR, FSR);
    1.42 -      break;
    1.43 -    case shl  :
    1.44 -      __ pop_i(SSR);
    1.45 -      __ sllv(FSR, SSR, FSR);
    1.46 -      break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.47 -    case shr  :
    1.48 -      __ pop_i(SSR);
    1.49 -      __ srav(FSR, SSR, FSR);
    1.50 -      break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.51 -    case ushr :
    1.52 -      __ pop_i(SSR);
    1.53 -      __ srlv(FSR, SSR, FSR);
    1.54 -      break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.55 +    case add  : __ addu32(FSR, SSR, FSR); break;
    1.56 +    case sub  : __ subu32(FSR, SSR, FSR); break;
    1.57 +    case mul  : __ mul(FSR, SSR, FSR);    break;
    1.58 +    case _and : __ andr(FSR, SSR, FSR);   break;
    1.59 +    case _or  : __ orr(FSR, SSR, FSR);    break;
    1.60 +    case _xor : __ xorr(FSR, SSR, FSR);   break;
    1.61 +    case shl  : __ sllv(FSR, SSR, FSR);   break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.62 +    case shr  : __ srav(FSR, SSR, FSR);   break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.63 +    case ushr : __ srlv(FSR, SSR, FSR);   break; // implicit masking of lower 5 bits by Intel shift instr. mips also
    1.64      default   : ShouldNotReachHere();
    1.65    }
    1.66  }
    1.67 @@ -1328,21 +1301,11 @@
    1.68    }
    1.69  #endif
    1.70    switch (op) {
    1.71 -    case add :
    1.72 -      __ daddu(FSR, T2, FSR);
    1.73 -      break;
    1.74 -    case sub :
    1.75 -      __ dsubu(FSR, T2, FSR);
    1.76 -      break;
    1.77 -    case _and:
    1.78 -      __ andr(FSR, T2, FSR);
    1.79 -      break;
    1.80 -    case _or :
    1.81 -      __ orr(FSR, T2, FSR);
    1.82 -      break;
    1.83 -    case _xor:
    1.84 -      __ xorr(FSR, T2, FSR);
    1.85 -      break;
    1.86 +    case add : __ daddu(FSR, T2, FSR); break;
    1.87 +    case sub : __ dsubu(FSR, T2, FSR); break;
    1.88 +    case _and: __ andr(FSR, T2, FSR);  break;
    1.89 +    case _or : __ orr(FSR, T2, FSR);   break;
    1.90 +    case _xor: __ xorr(FSR, T2, FSR);  break;
    1.91      default : ShouldNotReachHere();
    1.92    }
    1.93  }