# HG changeset patch
# User fujie
# Date 1505870688 -28800
# Node ID 2fa8027581f6fadf5fdc070b3423fedd75cc5e20
# Parent  75ee8543b584210d3fe1b91f4eaed1a478835032
[Interpreter] Remove redundant andi for shift operations.

diff -r 75ee8543b584 -r 2fa8027581f6 src/cpu/mips/vm/macroAssembler_mips.cpp
--- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Mon Sep 18 15:15:14 2017 +0800
+++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Wed Sep 20 09:24:48 2017 +0800
@@ -1322,11 +1322,6 @@
     // accessing M[reg] w/o changing any (non-CC) registers
     // NOTE: cmpl is plenty here to provoke a segv
     lw(AT, reg, 0);
-/* Jin
-    nop();
-    nop();
-    nop();
-*/
     // Note: should probably use testl(rax, Address(reg, 0));
     //       may be shorter code (however, this version of
     //       testl needs to be implemented first)
diff -r 75ee8543b584 -r 2fa8027581f6 src/cpu/mips/vm/templateTable_mips_64.cpp
--- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Mon Sep 18 15:15:14 2017 +0800
+++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 09:24:48 2017 +0800
@@ -208,8 +208,6 @@
   } else {
     __ move(FSR, value);
   }
-  assert(value >= 0, "check this code");
-  //__ move(SSR, R0);
 }
 
 void TemplateTable::fconst(int value) {
@@ -1456,7 +1454,6 @@
     __ bind(L);
   }
 #endif
-  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
   __ dsllv(FSR, T0, FSR);
 }
 
@@ -1473,7 +1470,6 @@
     __ bind(L);
   }
 #endif
-  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
   __ dsrav(FSR, T0, FSR);
 }
 
@@ -1490,7 +1486,6 @@
     __ bind(L);
   }
 #endif
-  __ andi(FSR, FSR, 0x3f);        // the bit to be shifted
   __ dsrlv(FSR, T0, FSR);
 }