Tue, 12 Dec 2017 10:30:27 +0800 |
#6345 sync is controled by UseSyncLevel instead of Use3A2000 |
file | diff | annotate
|
Thu, 07 Dec 2017 16:07:58 +0800 |
#6439 3B1500 is not gs464v but gs464. |
file | diff | annotate
|
Tue, 28 Nov 2017 15:50:12 +0800 |
#6408 cpuinfo support 2K1000 and gs264 |
file | diff | annotate
|
Fri, 01 Dec 2017 13:52:28 +0800 |
Tuning G1 for MIPS. |
file | diff | annotate
|
Mon, 23 Oct 2017 17:07:19 +0800 |
[G1] Initial porting of MacroAssembler::g1_write_barrier_{pre/post} |
file | diff | annotate
|
Tue, 10 Oct 2017 10:42:36 +0800 |
#6199 cpuinfo supports 3B2000/3B3000 |
file | diff | annotate
|
Thu, 07 Sep 2017 09:12:16 +0800 |
#5745 [Code Reorganization] code cleanup and code style fix |
file | diff | annotate
|
Wed, 17 May 2017 03:46:25 -0400 |
#5481 Vector optimization was not used by default. |
file | diff | annotate
|
Wed, 29 Mar 2017 09:43:19 +0800 |
#4662 UseG1GC is turned off. |
file | diff | annotate
|
Wed, 29 Mar 2017 09:41:51 +0800 |
#4662 TieredCompilation is turned off. |
file | diff | annotate
|
Sun, 12 Mar 2017 09:04:47 +0800 |
#4670 Detect LoongsonCPUs to adapt different platforms. |
file | diff | annotate
|
Wed, 01 Feb 2017 16:15:19 +0800 |
Set VM prefetch allocation args for Loongson CPUs. |
file | diff | annotate
|
Tue, 17 Jan 2017 19:57:30 -0500 |
ctz/dctz are only supported on 3A2000/3A3000 CPUs (Follows changeset:32b76f240db3). |
file | diff | annotate
|
Tue, 17 Jan 2017 21:53:02 -0500 |
Fix a SIGILL bug introduced by changeset 101daea92bb3. |
file | diff | annotate
|
Thu, 29 Dec 2016 13:40:20 +0800 |
#4814 [C2] initial 64-bit vector support |
file | diff | annotate
|
Fri, 16 Dec 2016 11:39:00 +0800 |
[C2] Added Zeros Count Instructions support in mips_64.ad |
file | diff | annotate
|
Fri, 29 Apr 2016 00:06:10 +0800 |
Added MIPS 64-bit port. |
file | diff | annotate
|