| Thu, 10 Nov 2016 10:48:04 +0800 |
[C2] Remove redundant sync operations. |
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| Thu, 10 Nov 2016 09:41:51 +0800 |
[Register Allocation] Add more registers for operand mRegL in mips_64.ad |
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| Thu, 10 Nov 2016 09:36:28 +0800 |
[Register Allocation] Adjust the register allocation priority for scimark.monte_carlo. |
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| Mon, 07 Nov 2016 16:50:14 +0800 |
[C2] Add operand no_Ax_mRegI for MIPS CPUs. |
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| Mon, 07 Nov 2016 16:34:45 +0800 |
[Intrinsic] Add java.lang.String::equals (81 bytes) (intrinsic) for MIPS C2 compiler. |
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| Thu, 10 Nov 2016 02:26:20 +0800 |
#4754 [C2] Fix a bug in cmpF3_reg_reg and cmpD3_reg_reg. |
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| Tue, 01 Nov 2016 17:47:21 +0800 |
[C2] Add more operands for RegN in mips_64.ad |
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| Tue, 01 Nov 2016 16:30:01 +0800 |
[C2] Add reg_class no_T8_p_reg in mips_64.ad |
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| Tue, 01 Nov 2016 11:29:24 +0800 |
[C2] Add T8 for register allocation. |
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| Tue, 01 Nov 2016 11:12:57 +0800 |
[C2] Release T8 from partialSubtypeCheck in mips_64.ad |
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| Mon, 31 Oct 2016 17:19:33 +0800 |
[C2] string_compare optimization. |
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| Mon, 31 Oct 2016 15:57:37 +0800 |
[C2] Since V0,V1 have been used in [stubGenerator_mips.cpp] generate_forward_exception(), disable them in register allocation temporarily. |
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| Fri, 28 Oct 2016 14:50:44 +0800 |
[C2] Parameter registers should be compared one by one in Matcher::can_be_java_arg(int). |
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| Fri, 28 Oct 2016 11:27:58 +0800 |
[C2] Since MIPS doesn't have absolute addressing, it needs a polling address input at SafePoint. |
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| Thu, 27 Oct 2016 14:28:02 +0800 |
[C2] Release S5 from storeImmN0_enc in mips_64.ad |
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| Thu, 27 Oct 2016 14:09:42 +0800 |
[C2] Add S7 in the available list for register allocation. |
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| Thu, 27 Oct 2016 13:53:34 +0800 |
[C2] Release S7,T8,T9 from string_compare in mips_64.ad |
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| Thu, 27 Oct 2016 13:31:22 +0800 |
[C2] Release S7 from safePoint_poll in mips_64.ad |
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| Thu, 27 Oct 2016 09:41:35 +0800 |
[C2] [T8,T9,S5,S6,S7] will be added into the list of available registers soon. |
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| Wed, 26 Oct 2016 17:27:08 +0800 |
[C2] Add more reg_class for operand mRegP. |
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| Wed, 26 Oct 2016 17:07:56 +0800 |
[C2] Extend available registers for RegI register allocation. |
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| Wed, 26 Oct 2016 16:23:45 +0800 |
[C2] Add more registers in reg_class. |
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| Wed, 26 Oct 2016 14:18:22 +0800 |
[C2] Adjust the allocation priority. |
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| Wed, 26 Oct 2016 13:56:47 +0800 |
[C2] Add more registers for allocation and remove useless reg_class in mips_64.ad |
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| Tue, 25 Oct 2016 13:51:52 +0800 |
[C2] Remove useless FlagsReg in mips_64.ad |
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| Tue, 25 Oct 2016 11:28:44 +0800 |
[C2] Memory(base + index<<scale + offset) addressing is extended for double and long types. |
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| Mon, 24 Oct 2016 14:59:49 +0800 |
[C2] Memory(base + index<<scale + offset) addressing for MIPS is OK. |
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| Mon, 24 Oct 2016 12:36:06 +0800 |
[C2] Add operand indPosIndexScaleOffset8Narrow in mips_64.ad |
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| Mon, 24 Oct 2016 11:45:44 +0800 |
[C2] Support for Memory(base + index<<scale + offset) addressing is enabled. |
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| Mon, 24 Oct 2016 10:10:54 +0800 |
[C2] Add operand baseIndexScaleOffset8 in mips_64.ad |
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| Fri, 21 Oct 2016 16:05:17 +0800 |
[C2] Add addL_RegI2L_RegI2L in mips_64.ad |
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| Fri, 21 Oct 2016 15:27:23 +0800 |
[C2] Add salL_RegI2L_imm in mips_64.ad |
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| Fri, 21 Oct 2016 15:21:03 +0800 |
[C2] Add andL_Reg_Reg_convI2L in mips64.ad |
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| Fri, 21 Oct 2016 14:45:19 +0800 |
[C2] Add addP_reg_reg_convI2L in mips64.ad |
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| Wed, 19 Oct 2016 14:29:12 +0800 |
#4607 C2: Crash in ObjectSynchronizer::slow_exit |
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| Mon, 26 Sep 2016 13:56:18 -0400 |
Mark changes for 3A2000 only with the Use3A2000 flag. |
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| Sun, 25 Sep 2016 17:38:33 -0400 |
Sync after card marking in C2 compiler. |
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| Mon, 12 Sep 2016 13:26:09 -0400 |
Add debugging infomation for C2 compiler. |
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| Wed, 24 Aug 2016 15:38:31 +0800 |
Add salI_RegL2I_imm in mips_64.ad |
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| Tue, 23 Aug 2016 17:00:34 +0800 |
Refine the implementation of cmpLTMask_immI0. |
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| Tue, 23 Aug 2016 15:23:48 +0800 |
Add slrL_Reg_immI_0_31 and slrL_Reg_immI_32_63 in mips_64.ad |
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| Tue, 23 Aug 2016 14:22:12 +0800 |
Add storeI_convL2I in mips_64.add. crypto.rsa is 13% up. |
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| Tue, 23 Aug 2016 10:45:23 +0800 |
Add immL16 im mips_64.ad |
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| Tue, 23 Aug 2016 09:21:30 +0800 |
Add loadUS_convI2L in mips_64.ad |
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| Tue, 23 Aug 2016 09:16:04 +0800 |
Add loadS_convI2L in mips_64.ad |
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| Tue, 23 Aug 2016 09:12:34 +0800 |
Add loadUB_convI2L in mips_64.ad |
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| Tue, 23 Aug 2016 09:07:41 +0800 |
Add loadB_convI2L in mips_64.ad |
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| Mon, 22 Aug 2016 17:51:21 +0800 |
Add cmpLTMask_immI0. |
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| Mon, 22 Aug 2016 17:29:54 +0800 |
Add andL_Reg_imm_0_65535 for AndL. |
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| Thu, 25 Aug 2016 17:34:45 +0800 |
For safety reason, disable gslbx for Loongson processors. |
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| Thu, 25 Aug 2016 14:46:18 +0800 |
#4476 #4461: Fix a bug related to float comparison. |
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| Thu, 18 Aug 2016 15:57:28 +0800 |
Remove sync in PrefetchAllocation. |
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| Thu, 18 Aug 2016 15:23:16 +0800 |
Remove unnecessary sync instructions in mips_64.ad |
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| Thu, 18 Aug 2016 14:17:07 +0800 |
Enable gsswx in store_I_reg_enc for Loongson processors. |
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| Thu, 18 Aug 2016 13:51:09 +0800 |
Enable gssdxc1 in store_D_reg_enc for Loongson processors. |
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| Thu, 18 Aug 2016 13:38:41 +0800 |
Enable gsldxc1 in load_D_enc for Loongson processors. |
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| Thu, 18 Aug 2016 11:50:18 +0800 |
Enable gsswxc1 for Loongson Processors. |
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| Thu, 18 Aug 2016 11:41:31 +0800 |
Enable gslwxc1 in load_F_enc for Loongson processors. |
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| Thu, 18 Aug 2016 11:16:54 +0800 |
Add addL_RegI2L_Reg and addL_Reg_RegI2L in mips_64.ad |
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| Thu, 18 Aug 2016 11:12:52 +0800 |
Add subL_Reg_RegI2L and subL_RegI2L_Reg in mips_64.ad |
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