[C2] Add andL_Reg_Reg_convI2L in mips64.ad

Fri, 21 Oct 2016 15:21:03 +0800

author
fujie
date
Fri, 21 Oct 2016 15:21:03 +0800
changeset 145
44c6dc8aeb6f
parent 144
df0e09eb84bd
child 146
d4a5de2c668a

[C2] Add andL_Reg_Reg_convI2L in mips64.ad

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Fri Oct 21 14:45:19 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Fri Oct 21 15:21:03 2016 +0800
     1.3 @@ -9032,6 +9032,19 @@
     1.4    ins_pipe( ialu_regL_regL );
     1.5  %}
     1.6  
     1.7 +instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
     1.8 +  match(Set dst (AndL src1 (ConvI2L src2)));
     1.9 +  format %{ "AND    $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
    1.10 +  ins_encode %{
    1.11 +    Register dst_reg = as_Register($dst$$reg);
    1.12 +    Register src1_reg = as_Register($src1$$reg);
    1.13 +    Register src2_reg = as_Register($src2$$reg);
    1.14 +
    1.15 +    __ andr(dst_reg, src1_reg, src2_reg);
    1.16 +  %}
    1.17 +  ins_pipe( ialu_regL_regL );
    1.18 +%}
    1.19 +
    1.20  instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1,  immL_0_65535 src2) %{
    1.21    match(Set dst (AndL src1 src2));
    1.22    ins_cost(60);

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