src/cpu/mips/vm/c1_LinearScan_mips.hpp

Tue, 26 Jul 2016 17:06:17 +0800

author
fujie
date
Tue, 26 Jul 2016 17:06:17 +0800
changeset 41
d885f8d65c58
parent 1
2d8a650513c2
child 6880
52ea28d233d2
permissions
-rw-r--r--

Add multiply word to GPR instruction (mul) in MIPS assembler.

     1 /*
     2  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     8  * published by the Free Software Foundation.
     9  *
    10  * This code is distributed in the hope that it will be useful, but WITHOUT
    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    13  * version 2 for more details (a copy is included in the LICENSE file that
    14  * accompanied this code).
    15  *
    16  * You should have received a copy of the GNU General Public License version
    17  * 2 along with this work; if not, write to the Free Software Foundation,
    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    19  *
    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    23  *
    24  */
    26 inline bool LinearScan::is_processed_reg_num(int reg_num) {
    27 	return reg_num < 26 || reg_num > 30;
    28 }
    30 inline int LinearScan::num_physical_regs(BasicType type) {
    31 	if (type == T_LONG || type== T_DOUBLE || type == T_FLOAT) {
    32 		return 2;
    33 	}
    34 	return 1;
    35 }
    38 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
    39 	return type == T_FLOAT || type == T_DOUBLE;
    40 }
    42 inline bool LinearScan::is_caller_save(int assigned_reg) {
    43 	assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
    44 	// return true; // no callee-saved registers on Intel
    45 	//FIXME, here, MIPS indeed got callee-saved registers
    46 	return true;
    47 }
    50 inline void LinearScan::pd_add_temps(LIR_Op* op) {
    51 }
    54 // Implementation of LinearScanWalker
    56 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
    57 	if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) {
    58 		assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
    59 		_first_reg = pd_first_callee_saved_reg;
    60 //		_first_reg = 8;
    61 		_last_reg = pd_last_callee_saved_reg;
    62 		return true;
    63 	} else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT) {
    64 //		_first_reg = pd_first_cpu_reg;
    65 #ifdef _LP64
    66 		_first_reg = 12;	/* From T0 */
    67 #else
    68 		_first_reg = 8;		/* From T0 */
    69 #endif
    70 		_last_reg = pd_last_allocatable_cpu_reg;
    71 		return true;
    72 	}
    73 	return false;
    74 }

mercurial