src/cpu/mips/vm/c1_LinearScan_mips.hpp

Thu, 07 Sep 2017 09:12:16 +0800

author
aoqi
date
Thu, 07 Sep 2017 09:12:16 +0800
changeset 6880
52ea28d233d2
parent 1
2d8a650513c2
child 8865
ffcdff41a92f
permissions
-rw-r--r--

#5745 [Code Reorganization] code cleanup and code style fix
This is a huge patch, but only code cleanup, code style fix and useless code deletion are included, for example:
tab -> two spaces, deleted spacees at the end of a line, delete useless comments.

This patch also included:
Declaration and definition of class MacroAssembler is moved from assembler_mips.h/cpp to macroAssembler_mips.h/cpp

     1 /*
     2  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     8  * published by the Free Software Foundation.
     9  *
    10  * This code is distributed in the hope that it will be useful, but WITHOUT
    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    13  * version 2 for more details (a copy is included in the LICENSE file that
    14  * accompanied this code).
    15  *
    16  * You should have received a copy of the GNU General Public License version
    17  * 2 along with this work; if not, write to the Free Software Foundation,
    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    19  *
    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    23  *
    24  */
    26 inline bool LinearScan::is_processed_reg_num(int reg_num) {
    27   return reg_num < 26 || reg_num > 30;
    28 }
    30 inline int LinearScan::num_physical_regs(BasicType type) {
    31   if (type == T_LONG || type== T_DOUBLE || type == T_FLOAT) {
    32     return 2;
    33   }
    34   return 1;
    35 }
    38 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
    39   return type == T_FLOAT || type == T_DOUBLE;
    40 }
    42 inline bool LinearScan::is_caller_save(int assigned_reg) {
    43   assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
    44   // return true; // no callee-saved registers on Intel
    45   //FIXME, here, MIPS indeed got callee-saved registers
    46   return true;
    47 }
    50 inline void LinearScan::pd_add_temps(LIR_Op* op) {
    51 }
    54 // Implementation of LinearScanWalker
    56 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
    57   if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) {
    58     assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
    59     _first_reg = pd_first_callee_saved_reg;
    60     _last_reg = pd_last_callee_saved_reg;
    61     return true;
    62   } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT) {
    63 #ifdef _LP64
    64     _first_reg = 12;  /* From T0 */
    65 #else
    66     _first_reg = 8;    /* From T0 */
    67 #endif
    68     _last_reg = pd_last_allocatable_cpu_reg;
    69     return true;
    70   }
    71   return false;
    72 }

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