1.1 --- a/src/share/vm/c1/c1_LIR.cpp Wed Sep 06 00:35:24 2017 -0700
1.2 +++ b/src/share/vm/c1/c1_LIR.cpp Thu May 24 18:41:44 2018 +0800
1.3 @@ -22,6 +22,12 @@
1.4 *
1.5 */
1.6
1.7 +/*
1.8 + * This file has been modified by Loongson Technology in 2015. These
1.9 + * modifications are Copyright (c) 2015 Loongson Technology, and are made
1.10 + * available on the same license terms set forth above.
1.11 + */
1.12 +
1.13 #include "precompiled.hpp"
1.14 #include "c1/c1_InstructionPrinter.hpp"
1.15 #include "c1/c1_LIR.hpp"
1.16 @@ -66,6 +72,25 @@
1.17 }
1.18
1.19 #endif
1.20 +#ifdef MIPS64
1.21 +
1.22 +FloatRegister LIR_OprDesc::as_float_reg() const {
1.23 + return FrameMap::nr2floatreg(fpu_regnr());
1.24 +}
1.25 +
1.26 +FloatRegister LIR_OprDesc::as_double_reg() const {
1.27 + return FrameMap::nr2floatreg(fpu_regnrHi());
1.28 +}
1.29 +
1.30 +FloatRegister LIR_OprDesc::as_fpu_lo() const {
1.31 + return FrameMap::nr2floatreg(fpu_regnrLo());
1.32 +}
1.33 +
1.34 +FloatRegister LIR_OprDesc::as_fpu_hi() const {
1.35 + return FrameMap::nr2floatreg(fpu_regnrHi());
1.36 +}
1.37 +
1.38 +#endif
1.39
1.40 #ifdef ARM
1.41
1.42 @@ -150,8 +175,10 @@
1.43 #ifdef _LP64
1.44 assert(base()->is_cpu_register(), "wrong base operand");
1.45 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
1.46 +#ifndef MIPS64
1.47 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
1.48 "wrong type for addresses");
1.49 +#endif
1.50 #else
1.51 assert(base()->is_single_cpu(), "wrong base operand");
1.52 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
1.53 @@ -298,6 +325,7 @@
1.54 }
1.55
1.56
1.57 +#ifndef MIPS64
1.58 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
1.59 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
1.60 , _cond(cond)
1.61 @@ -329,6 +357,43 @@
1.62 {
1.63 }
1.64
1.65 +#else
1.66 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.67 + BlockBegin* block):
1.68 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.69 + _cond(cond),
1.70 + _type(type),
1.71 + _label(block->label()),
1.72 + _block(block),
1.73 + _ublock(NULL),
1.74 + _stub(NULL) {
1.75 +}
1.76 +
1.77 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.78 + CodeStub* stub):
1.79 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.80 + _cond(cond),
1.81 + _type(type),
1.82 + _label(stub->entry()),
1.83 + _block(NULL),
1.84 + _ublock(NULL),
1.85 + _stub(stub) {
1.86 +}
1.87 +
1.88 +
1.89 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.90 + BlockBegin *block, BlockBegin *ublock):
1.91 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.92 + _cond(cond),
1.93 + _type(type),
1.94 + _label(block->label()),
1.95 + _block(block),
1.96 + _ublock(ublock),
1.97 + _stub(NULL) {
1.98 +}
1.99 +
1.100 +#endif
1.101 +
1.102 void LIR_OpBranch::change_block(BlockBegin* b) {
1.103 assert(_block != NULL, "must have old block");
1.104 assert(_block->label() == label(), "must be equal");
1.105 @@ -572,6 +637,15 @@
1.106 assert(op->as_OpBranch() != NULL, "must be");
1.107 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
1.108
1.109 +#ifdef MIPS64
1.110 + if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
1.111 + if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
1.112 + if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
1.113 + if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
1.114 + if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
1.115 + if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
1.116 + if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
1.117 +#endif
1.118 if (opBranch->_info != NULL) do_info(opBranch->_info);
1.119 assert(opBranch->_result->is_illegal(), "not used");
1.120 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
1.121 @@ -594,6 +668,10 @@
1.122 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
1.123 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
1.124 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
1.125 +#ifdef MIPS64
1.126 + if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
1.127 + if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
1.128 +#endif
1.129 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
1.130 do_stub(opAllocObj->_stub);
1.131 break;
1.132 @@ -615,7 +693,11 @@
1.133
1.134
1.135 // LIR_Op2
1.136 +#ifdef MIPS64
1.137 + case lir_null_check_for_branch:
1.138 +#else
1.139 case lir_cmp:
1.140 +#endif
1.141 case lir_cmp_l2i:
1.142 case lir_ucmp_fd2i:
1.143 case lir_cmp_fd2i:
1.144 @@ -783,6 +865,9 @@
1.145 }
1.146
1.147 // LIR_Op3
1.148 +#ifdef MIPS64
1.149 + case lir_frem:
1.150 +#endif
1.151 case lir_idiv:
1.152 case lir_irem: {
1.153 assert(op->as_Op3() != NULL, "must be");
1.154 @@ -867,7 +952,9 @@
1.155 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
1.156 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
1.157 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
1.158 +#ifndef MIPS64
1.159 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
1.160 +#endif
1.161 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1.162
1.163 // the implementation of arraycopy always has a call into the runtime
1.164 @@ -982,6 +1069,9 @@
1.165 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1.166 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1.167 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1.168 +#ifdef MIPS64
1.169 + if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1.170 +#endif
1.171 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1.172 do_stub(opAllocArray->_stub);
1.173 break;
1.174 @@ -1252,6 +1342,7 @@
1.175 }
1.176
1.177 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.178 +#ifndef MIPS64
1.179 append(new LIR_Op1(
1.180 lir_move,
1.181 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1.182 @@ -1259,6 +1350,16 @@
1.183 type,
1.184 patch_code,
1.185 info, lir_move_volatile));
1.186 +#else
1.187 + add(base, offset, base);
1.188 + append(new LIR_Op1(
1.189 + lir_move,
1.190 + LIR_OprFact::address(new LIR_Address(base, 0, type)),
1.191 + dst,
1.192 + type,
1.193 + patch_code,
1.194 + info, lir_move_volatile));
1.195 +#endif
1.196 }
1.197
1.198
1.199 @@ -1314,6 +1415,7 @@
1.200 }
1.201
1.202 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.203 +#ifndef MIPS64
1.204 append(new LIR_Op1(
1.205 lir_move,
1.206 src,
1.207 @@ -1321,8 +1423,31 @@
1.208 type,
1.209 patch_code,
1.210 info, lir_move_volatile));
1.211 +#else
1.212 + add(base, offset, base);
1.213 + append(new LIR_Op1(
1.214 + lir_move,
1.215 + src,
1.216 + LIR_OprFact::address(new LIR_Address(base, 0, type)),
1.217 + type,
1.218 + patch_code,
1.219 + info, lir_move_volatile));
1.220 +
1.221 +#endif
1.222 +
1.223 }
1.224
1.225 +#ifdef MIPS64
1.226 +void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1.227 + append(new LIR_Op3(
1.228 + lir_frem,
1.229 + left,
1.230 + right,
1.231 + tmp,
1.232 + res,
1.233 + info));
1.234 +}
1.235 +#endif
1.236
1.237 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1.238 append(new LIR_Op3(
1.239 @@ -1368,6 +1493,7 @@
1.240 }
1.241
1.242
1.243 +#ifndef MIPS64
1.244 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1.245 append(new LIR_Op2(
1.246 lir_cmp,
1.247 @@ -1377,6 +1503,17 @@
1.248 info));
1.249 }
1.250
1.251 +void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1.252 + if (deoptimize_on_null) {
1.253 + // Emit an explicit null check and deoptimize if opr is null
1.254 + CodeStub* deopt = new DeoptimizeStub(info);
1.255 + cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1.256 + branch(lir_cond_equal, T_OBJECT, deopt);
1.257 + } else {
1.258 + // Emit an implicit null check
1.259 + append(new LIR_Op1(lir_null_check, opr, info));
1.260 + }
1.261 +}
1.262
1.263 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1.264 append(new LIR_Op2(
1.265 @@ -1414,6 +1551,39 @@
1.266 type,
1.267 stub));
1.268 }
1.269 +#else
1.270 + void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1.271 + int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1.272 + append(new LIR_OpAllocObj(
1.273 + klass,
1.274 + dst,
1.275 + t1,
1.276 + t2,
1.277 + t3,
1.278 + t4,
1.279 + t5,
1.280 + t6,
1.281 + header_size,
1.282 + object_size,
1.283 + init_check,
1.284 + stub));
1.285 +}
1.286 +void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1.287 + BasicType type, LIR_Opr klass, CodeStub* stub) {
1.288 + append(new LIR_OpAllocArray(
1.289 + klass,
1.290 + len,
1.291 + dst,
1.292 + t1,
1.293 + t2,
1.294 + t3,
1.295 + t4,
1.296 + t5,
1.297 + type,
1.298 + stub));
1.299 +}
1.300 +
1.301 +#endif
1.302
1.303 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1.304 append(new LIR_Op2(
1.305 @@ -1504,7 +1674,6 @@
1.306 append(c);
1.307 }
1.308
1.309 -
1.310 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1.311 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1.312 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1.313 @@ -1516,18 +1685,7 @@
1.314 append(c);
1.315 }
1.316
1.317 -void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1.318 - if (deoptimize_on_null) {
1.319 - // Emit an explicit null check and deoptimize if opr is null
1.320 - CodeStub* deopt = new DeoptimizeStub(info);
1.321 - cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1.322 - branch(lir_cond_equal, T_OBJECT, deopt);
1.323 - } else {
1.324 - // Emit an implicit null check
1.325 - append(new LIR_Op1(lir_null_check, opr, info));
1.326 - }
1.327 -}
1.328 -
1.329 +#ifndef MIPS64
1.330 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.331 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.332 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1.333 @@ -1542,6 +1700,43 @@
1.334 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.335 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1.336 }
1.337 +#else
1.338 +void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.339 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.340 + // // implying successful swap of new_value into addr
1.341 + append(new LIR_OpCompareAndSwap(lir_cas_long,
1.342 + addr,
1.343 + cmp_value,
1.344 + new_value,
1.345 + t1,
1.346 + t2,
1.347 + result));
1.348 +}
1.349 +
1.350 +void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.351 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.352 + // // implying successful swap of new_value into addr
1.353 + append(new LIR_OpCompareAndSwap(lir_cas_obj,
1.354 + addr,
1.355 + cmp_value,
1.356 + new_value,
1.357 + t1,
1.358 + t2,
1.359 + result));
1.360 +}
1.361 +
1.362 +void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.363 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.364 + // // implying successful swap of new_value into addr
1.365 + append(new LIR_OpCompareAndSwap(lir_cas_int,
1.366 + addr,
1.367 + cmp_value,
1.368 + new_value,
1.369 + t1,
1.370 + t2,
1.371 + result));
1.372 +}
1.373 +#endif
1.374
1.375
1.376 #ifdef PRODUCT
1.377 @@ -1627,6 +1822,7 @@
1.378 // LIR_Address
1.379 void LIR_Address::print_value_on(outputStream* out) const {
1.380 out->print("Base:"); _base->print(out);
1.381 +#ifndef MIPS64
1.382 if (!_index->is_illegal()) {
1.383 out->print(" Index:"); _index->print(out);
1.384 switch (scale()) {
1.385 @@ -1636,6 +1832,7 @@
1.386 case times_8: out->print(" * 8"); break;
1.387 }
1.388 }
1.389 +#endif
1.390 out->print(" Disp: " INTX_FORMAT, _disp);
1.391 }
1.392
1.393 @@ -1767,7 +1964,11 @@
1.394 case lir_pack64: s = "pack64"; break;
1.395 case lir_unpack64: s = "unpack64"; break;
1.396 // LIR_Op2
1.397 +#ifdef MIPS64
1.398 + case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1.399 +#else
1.400 case lir_cmp: s = "cmp"; break;
1.401 +#endif
1.402 case lir_cmp_l2i: s = "cmp_l2i"; break;
1.403 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1.404 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1.405 @@ -1798,6 +1999,9 @@
1.406 case lir_xadd: s = "xadd"; break;
1.407 case lir_xchg: s = "xchg"; break;
1.408 // LIR_Op3
1.409 +#ifdef MIPS64
1.410 + case lir_frem: s = "frem"; break;
1.411 +#endif
1.412 case lir_idiv: s = "idiv"; break;
1.413 case lir_irem: s = "irem"; break;
1.414 // LIR_OpJavaCall
1.415 @@ -1936,6 +2140,10 @@
1.416 // LIR_OpBranch
1.417 void LIR_OpBranch::print_instr(outputStream* out) const {
1.418 print_condition(out, cond()); out->print(" ");
1.419 +#ifdef MIPS64
1.420 + in_opr1()->print(out); out->print(" ");
1.421 + in_opr2()->print(out); out->print(" ");
1.422 +#endif
1.423 if (block() != NULL) {
1.424 out->print("[B%d] ", block()->block_id());
1.425 } else if (stub() != NULL) {
1.426 @@ -2009,6 +2217,10 @@
1.427 tmp2()->print(out); out->print(" ");
1.428 tmp3()->print(out); out->print(" ");
1.429 tmp4()->print(out); out->print(" ");
1.430 +#ifdef MIPS64
1.431 + tmp5()->print(out); out->print(" ");
1.432 + tmp6()->print(out); out->print(" ");
1.433 +#endif
1.434 out->print("[hdr:%d]", header_size()); out->print(" ");
1.435 out->print("[obj:%d]", object_size()); out->print(" ");
1.436 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1.437 @@ -2022,9 +2234,11 @@
1.438
1.439 // LIR_Op2
1.440 void LIR_Op2::print_instr(outputStream* out) const {
1.441 +#ifndef MIPS64
1.442 if (code() == lir_cmove) {
1.443 print_condition(out, condition()); out->print(" ");
1.444 }
1.445 +#endif
1.446 in_opr1()->print(out); out->print(" ");
1.447 in_opr2()->print(out); out->print(" ");
1.448 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1.449 @@ -2043,6 +2257,9 @@
1.450 tmp2()->print(out); out->print(" ");
1.451 tmp3()->print(out); out->print(" ");
1.452 tmp4()->print(out); out->print(" ");
1.453 +#ifdef MIPS64
1.454 + tmp5()->print(out); out->print(" ");
1.455 +#endif
1.456 out->print("[type:0x%x]", type()); out->print(" ");
1.457 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1.458 }
1.459 @@ -2086,10 +2303,14 @@
1.460
1.461 #ifdef ASSERT
1.462 void LIR_OpAssert::print_instr(outputStream* out) const {
1.463 + tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
1.464 + Unimplemented();
1.465 + /*
1.466 print_condition(out, condition()); out->print(" ");
1.467 in_opr1()->print(out); out->print(" ");
1.468 in_opr2()->print(out); out->print(", \"");
1.469 out->print("%s", msg()); out->print("\"");
1.470 + */
1.471 }
1.472 #endif
1.473
