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comparison: src/share/vm/c1/c1_LIR.cpp

src/share/vm/c1/c1_LIR.cpp

changeset 8856
ac27a9c85bea
parent 8735
dcaab7b518c4
parent 7994
04ff2f6cd0eb
child 8865
ffcdff41a92f
equal deleted inserted replaced
8855:98b4b0661837 8856:ac27a9c85bea
20 * or visit www.oracle.com if you need additional information or have any 20 * or visit www.oracle.com if you need additional information or have any
21 * questions. 21 * questions.
22 * 22 *
23 */ 23 */
24 24
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
30
25 #include "precompiled.hpp" 31 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp" 32 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp" 33 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp" 34 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp" 35 #include "c1/c1_ValueStack.hpp"
61 return FrameMap::nr2floatreg(fpu_regnr()); 67 return FrameMap::nr2floatreg(fpu_regnr());
62 } 68 }
63 69
64 FloatRegister LIR_OprDesc::as_double_reg() const { 70 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi()); 71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
73
74 #endif
75 #ifdef MIPS64
76
77 FloatRegister LIR_OprDesc::as_float_reg() const {
78 return FrameMap::nr2floatreg(fpu_regnr());
79 }
80
81 FloatRegister LIR_OprDesc::as_double_reg() const {
82 return FrameMap::nr2floatreg(fpu_regnrHi());
83 }
84
85 FloatRegister LIR_OprDesc::as_fpu_lo() const {
86 return FrameMap::nr2floatreg(fpu_regnrLo());
87 }
88
89 FloatRegister LIR_OprDesc::as_fpu_hi() const {
90 return FrameMap::nr2floatreg(fpu_regnrHi());
66 } 91 }
67 92
68 #endif 93 #endif
69 94
70 #ifdef ARM 95 #ifdef ARM
148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 173 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif 174 #endif
150 #ifdef _LP64 175 #ifdef _LP64
151 assert(base()->is_cpu_register(), "wrong base operand"); 176 assert(base()->is_cpu_register(), "wrong base operand");
152 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 177 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
178 #ifndef MIPS64
153 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 179 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
154 "wrong type for addresses"); 180 "wrong type for addresses");
181 #endif
155 #else 182 #else
156 assert(base()->is_single_cpu(), "wrong base operand"); 183 assert(base()->is_single_cpu(), "wrong base operand");
157 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 184 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
158 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 185 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
159 "wrong type for addresses"); 186 "wrong type for addresses");
296 } 323 }
297 #endif 324 #endif
298 } 325 }
299 326
300 327
328 #ifndef MIPS64
301 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 329 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
302 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 330 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
303 , _cond(cond) 331 , _cond(cond)
304 , _type(type) 332 , _type(type)
305 , _label(block->label()) 333 , _label(block->label())
326 , _block(block) 354 , _block(block)
327 , _ublock(ublock) 355 , _ublock(ublock)
328 , _stub(NULL) 356 , _stub(NULL)
329 { 357 {
330 } 358 }
359
360 #else
361 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
362 BlockBegin* block):
363 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
364 _cond(cond),
365 _type(type),
366 _label(block->label()),
367 _block(block),
368 _ublock(NULL),
369 _stub(NULL) {
370 }
371
372 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
373 CodeStub* stub):
374 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
375 _cond(cond),
376 _type(type),
377 _label(stub->entry()),
378 _block(NULL),
379 _ublock(NULL),
380 _stub(stub) {
381 }
382
383
384 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
385 BlockBegin *block, BlockBegin *ublock):
386 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
387 _cond(cond),
388 _type(type),
389 _label(block->label()),
390 _block(block),
391 _ublock(ublock),
392 _stub(NULL) {
393 }
394
395 #endif
331 396
332 void LIR_OpBranch::change_block(BlockBegin* b) { 397 void LIR_OpBranch::change_block(BlockBegin* b) {
333 assert(_block != NULL, "must have old block"); 398 assert(_block != NULL, "must have old block");
334 assert(_block->label() == label(), "must be equal"); 399 assert(_block->label() == label(), "must be equal");
335 400
570 case lir_cond_float_branch: // may have info, input and result register always invalid 635 case lir_cond_float_branch: // may have info, input and result register always invalid
571 { 636 {
572 assert(op->as_OpBranch() != NULL, "must be"); 637 assert(op->as_OpBranch() != NULL, "must be");
573 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 638 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
574 639
640 #ifdef MIPS64
641 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
642 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
643 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
644 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
645 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
646 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
647 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
648 #endif
575 if (opBranch->_info != NULL) do_info(opBranch->_info); 649 if (opBranch->_info != NULL) do_info(opBranch->_info);
576 assert(opBranch->_result->is_illegal(), "not used"); 650 assert(opBranch->_result->is_illegal(), "not used");
577 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 651 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
578 652
579 break; 653 break;
592 } 666 }
593 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 667 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
594 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 668 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
595 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 669 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
596 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 670 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
671 #ifdef MIPS64
672 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
673 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
674 #endif
597 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 675 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
598 do_stub(opAllocObj->_stub); 676 do_stub(opAllocObj->_stub);
599 break; 677 break;
600 } 678 }
601 679
613 break; 691 break;
614 } 692 }
615 693
616 694
617 // LIR_Op2 695 // LIR_Op2
696 #ifdef MIPS64
697 case lir_null_check_for_branch:
698 #else
618 case lir_cmp: 699 case lir_cmp:
700 #endif
619 case lir_cmp_l2i: 701 case lir_cmp_l2i:
620 case lir_ucmp_fd2i: 702 case lir_ucmp_fd2i:
621 case lir_cmp_fd2i: 703 case lir_cmp_fd2i:
622 case lir_add: 704 case lir_add:
623 case lir_sub: 705 case lir_sub:
781 863
782 break; 864 break;
783 } 865 }
784 866
785 // LIR_Op3 867 // LIR_Op3
868 #ifdef MIPS64
869 case lir_frem:
870 #endif
786 case lir_idiv: 871 case lir_idiv:
787 case lir_irem: { 872 case lir_irem: {
788 assert(op->as_Op3() != NULL, "must be"); 873 assert(op->as_Op3() != NULL, "must be");
789 LIR_Op3* op3= (LIR_Op3*)op; 874 LIR_Op3* op3= (LIR_Op3*)op;
790 875
865 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 950 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
866 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 951 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
867 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 952 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
868 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 953 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
869 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 954 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
955 #ifndef MIPS64
870 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 956 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
957 #endif
871 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 958 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
872 959
873 // the implementation of arraycopy always has a call into the runtime 960 // the implementation of arraycopy always has a call into the runtime
874 do_call(); 961 do_call();
875 962
980 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 1067 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
981 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 1068 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
982 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 1069 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
983 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 1070 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
984 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 1071 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1072 #ifdef MIPS64
1073 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1074 #endif
985 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 1075 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
986 do_stub(opAllocArray->_stub); 1076 do_stub(opAllocArray->_stub);
987 break; 1077 break;
988 } 1078 }
989 1079
1250 patch_code, 1340 patch_code,
1251 info, lir_move_volatile)); 1341 info, lir_move_volatile));
1252 } 1342 }
1253 1343
1254 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1344 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1345 #ifndef MIPS64
1255 append(new LIR_Op1( 1346 append(new LIR_Op1(
1256 lir_move, 1347 lir_move,
1257 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1348 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1258 dst, 1349 dst,
1259 type, 1350 type,
1260 patch_code, 1351 patch_code,
1261 info, lir_move_volatile)); 1352 info, lir_move_volatile));
1353 #else
1354 add(base, offset, base);
1355 append(new LIR_Op1(
1356 lir_move,
1357 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1358 dst,
1359 type,
1360 patch_code,
1361 info, lir_move_volatile));
1362 #endif
1262 } 1363 }
1263 1364
1264 1365
1265 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1366 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1266 append(new LIR_Op1( 1367 append(new LIR_Op1(
1312 info, 1413 info,
1313 lir_move_volatile)); 1414 lir_move_volatile));
1314 } 1415 }
1315 1416
1316 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1417 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1418 #ifndef MIPS64
1317 append(new LIR_Op1( 1419 append(new LIR_Op1(
1318 lir_move, 1420 lir_move,
1319 src, 1421 src,
1320 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1422 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1321 type, 1423 type,
1322 patch_code, 1424 patch_code,
1323 info, lir_move_volatile)); 1425 info, lir_move_volatile));
1324 } 1426 #else
1325 1427 add(base, offset, base);
1428 append(new LIR_Op1(
1429 lir_move,
1430 src,
1431 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1432 type,
1433 patch_code,
1434 info, lir_move_volatile));
1435
1436 #endif
1437
1438 }
1439
1440 #ifdef MIPS64
1441 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1442 append(new LIR_Op3(
1443 lir_frem,
1444 left,
1445 right,
1446 tmp,
1447 res,
1448 info));
1449 }
1450 #endif
1326 1451
1327 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1452 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1328 append(new LIR_Op3( 1453 append(new LIR_Op3(
1329 lir_idiv, 1454 lir_idiv,
1330 left, 1455 left,
1366 res, 1491 res,
1367 info)); 1492 info));
1368 } 1493 }
1369 1494
1370 1495
1496 #ifndef MIPS64
1371 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1497 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1372 append(new LIR_Op2( 1498 append(new LIR_Op2(
1373 lir_cmp, 1499 lir_cmp,
1374 condition, 1500 condition,
1375 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1501 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1376 LIR_OprFact::intConst(c), 1502 LIR_OprFact::intConst(c),
1377 info)); 1503 info));
1378 } 1504 }
1379 1505
1506 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1507 if (deoptimize_on_null) {
1508 // Emit an explicit null check and deoptimize if opr is null
1509 CodeStub* deopt = new DeoptimizeStub(info);
1510 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1511 branch(lir_cond_equal, T_OBJECT, deopt);
1512 } else {
1513 // Emit an implicit null check
1514 append(new LIR_Op1(lir_null_check, opr, info));
1515 }
1516 }
1380 1517
1381 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1518 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1382 append(new LIR_Op2( 1519 append(new LIR_Op2(
1383 lir_cmp, 1520 lir_cmp,
1384 condition, 1521 condition,
1412 t3, 1549 t3,
1413 t4, 1550 t4,
1414 type, 1551 type,
1415 stub)); 1552 stub));
1416 } 1553 }
1554 #else
1555 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1556 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1557 append(new LIR_OpAllocObj(
1558 klass,
1559 dst,
1560 t1,
1561 t2,
1562 t3,
1563 t4,
1564 t5,
1565 t6,
1566 header_size,
1567 object_size,
1568 init_check,
1569 stub));
1570 }
1571 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1572 BasicType type, LIR_Opr klass, CodeStub* stub) {
1573 append(new LIR_OpAllocArray(
1574 klass,
1575 len,
1576 dst,
1577 t1,
1578 t2,
1579 t3,
1580 t4,
1581 t5,
1582 type,
1583 stub));
1584 }
1585
1586 #endif
1417 1587
1418 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1588 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1419 append(new LIR_Op2( 1589 append(new LIR_Op2(
1420 lir_shl, 1590 lir_shl,
1421 value, 1591 value,
1502 c->set_should_profile(true); 1672 c->set_should_profile(true);
1503 } 1673 }
1504 append(c); 1674 append(c);
1505 } 1675 }
1506 1676
1507
1508 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1677 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1509 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1678 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1510 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1679 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1511 if (profiled_method != NULL) { 1680 if (profiled_method != NULL) {
1512 c->set_profiled_method(profiled_method); 1681 c->set_profiled_method(profiled_method);
1514 c->set_should_profile(true); 1683 c->set_should_profile(true);
1515 } 1684 }
1516 append(c); 1685 append(c);
1517 } 1686 }
1518 1687
1519 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) { 1688 #ifndef MIPS64
1520 if (deoptimize_on_null) {
1521 // Emit an explicit null check and deoptimize if opr is null
1522 CodeStub* deopt = new DeoptimizeStub(info);
1523 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1524 branch(lir_cond_equal, T_OBJECT, deopt);
1525 } else {
1526 // Emit an implicit null check
1527 append(new LIR_Op1(lir_null_check, opr, info));
1528 }
1529 }
1530
1531 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1689 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1532 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1690 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1533 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1691 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1534 } 1692 }
1535 1693
1540 1698
1541 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1699 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1542 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1700 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1543 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1701 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1544 } 1702 }
1703 #else
1704 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1705 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1706 // // implying successful swap of new_value into addr
1707 append(new LIR_OpCompareAndSwap(lir_cas_long,
1708 addr,
1709 cmp_value,
1710 new_value,
1711 t1,
1712 t2,
1713 result));
1714 }
1715
1716 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1717 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1718 // // implying successful swap of new_value into addr
1719 append(new LIR_OpCompareAndSwap(lir_cas_obj,
1720 addr,
1721 cmp_value,
1722 new_value,
1723 t1,
1724 t2,
1725 result));
1726 }
1727
1728 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1729 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1730 // // implying successful swap of new_value into addr
1731 append(new LIR_OpCompareAndSwap(lir_cas_int,
1732 addr,
1733 cmp_value,
1734 new_value,
1735 t1,
1736 t2,
1737 result));
1738 }
1739 #endif
1545 1740
1546 1741
1547 #ifdef PRODUCT 1742 #ifdef PRODUCT
1548 1743
1549 void print_LIR(BlockList* blocks) { 1744 void print_LIR(BlockList* blocks) {
1625 } 1820 }
1626 1821
1627 // LIR_Address 1822 // LIR_Address
1628 void LIR_Address::print_value_on(outputStream* out) const { 1823 void LIR_Address::print_value_on(outputStream* out) const {
1629 out->print("Base:"); _base->print(out); 1824 out->print("Base:"); _base->print(out);
1825 #ifndef MIPS64
1630 if (!_index->is_illegal()) { 1826 if (!_index->is_illegal()) {
1631 out->print(" Index:"); _index->print(out); 1827 out->print(" Index:"); _index->print(out);
1632 switch (scale()) { 1828 switch (scale()) {
1633 case times_1: break; 1829 case times_1: break;
1634 case times_2: out->print(" * 2"); break; 1830 case times_2: out->print(" * 2"); break;
1635 case times_4: out->print(" * 4"); break; 1831 case times_4: out->print(" * 4"); break;
1636 case times_8: out->print(" * 8"); break; 1832 case times_8: out->print(" * 8"); break;
1637 } 1833 }
1638 } 1834 }
1835 #endif
1639 out->print(" Disp: " INTX_FORMAT, _disp); 1836 out->print(" Disp: " INTX_FORMAT, _disp);
1640 } 1837 }
1641 1838
1642 // debug output of block header without InstructionPrinter 1839 // debug output of block header without InstructionPrinter
1643 // (because phi functions are not necessary for LIR) 1840 // (because phi functions are not necessary for LIR)
1765 case lir_alloc_object: s = "alloc_obj"; break; 1962 case lir_alloc_object: s = "alloc_obj"; break;
1766 case lir_monaddr: s = "mon_addr"; break; 1963 case lir_monaddr: s = "mon_addr"; break;
1767 case lir_pack64: s = "pack64"; break; 1964 case lir_pack64: s = "pack64"; break;
1768 case lir_unpack64: s = "unpack64"; break; 1965 case lir_unpack64: s = "unpack64"; break;
1769 // LIR_Op2 1966 // LIR_Op2
1967 #ifdef MIPS64
1968 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1969 #else
1770 case lir_cmp: s = "cmp"; break; 1970 case lir_cmp: s = "cmp"; break;
1971 #endif
1771 case lir_cmp_l2i: s = "cmp_l2i"; break; 1972 case lir_cmp_l2i: s = "cmp_l2i"; break;
1772 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1973 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1773 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1974 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1774 case lir_cmove: s = "cmove"; break; 1975 case lir_cmove: s = "cmove"; break;
1775 case lir_add: s = "add"; break; 1976 case lir_add: s = "add"; break;
1796 case lir_ushr: s = "ushift_right"; break; 1997 case lir_ushr: s = "ushift_right"; break;
1797 case lir_alloc_array: s = "alloc_array"; break; 1998 case lir_alloc_array: s = "alloc_array"; break;
1798 case lir_xadd: s = "xadd"; break; 1999 case lir_xadd: s = "xadd"; break;
1799 case lir_xchg: s = "xchg"; break; 2000 case lir_xchg: s = "xchg"; break;
1800 // LIR_Op3 2001 // LIR_Op3
2002 #ifdef MIPS64
2003 case lir_frem: s = "frem"; break;
2004 #endif
1801 case lir_idiv: s = "idiv"; break; 2005 case lir_idiv: s = "idiv"; break;
1802 case lir_irem: s = "irem"; break; 2006 case lir_irem: s = "irem"; break;
1803 // LIR_OpJavaCall 2007 // LIR_OpJavaCall
1804 case lir_static_call: s = "static"; break; 2008 case lir_static_call: s = "static"; break;
1805 case lir_optvirtual_call: s = "optvirtual"; break; 2009 case lir_optvirtual_call: s = "optvirtual"; break;
1934 } 2138 }
1935 2139
1936 // LIR_OpBranch 2140 // LIR_OpBranch
1937 void LIR_OpBranch::print_instr(outputStream* out) const { 2141 void LIR_OpBranch::print_instr(outputStream* out) const {
1938 print_condition(out, cond()); out->print(" "); 2142 print_condition(out, cond()); out->print(" ");
2143 #ifdef MIPS64
2144 in_opr1()->print(out); out->print(" ");
2145 in_opr2()->print(out); out->print(" ");
2146 #endif
1939 if (block() != NULL) { 2147 if (block() != NULL) {
1940 out->print("[B%d] ", block()->block_id()); 2148 out->print("[B%d] ", block()->block_id());
1941 } else if (stub() != NULL) { 2149 } else if (stub() != NULL) {
1942 out->print("["); 2150 out->print("[");
1943 stub()->print_name(out); 2151 stub()->print_name(out);
2007 obj()->print(out); out->print(" "); 2215 obj()->print(out); out->print(" ");
2008 tmp1()->print(out); out->print(" "); 2216 tmp1()->print(out); out->print(" ");
2009 tmp2()->print(out); out->print(" "); 2217 tmp2()->print(out); out->print(" ");
2010 tmp3()->print(out); out->print(" "); 2218 tmp3()->print(out); out->print(" ");
2011 tmp4()->print(out); out->print(" "); 2219 tmp4()->print(out); out->print(" ");
2220 #ifdef MIPS64
2221 tmp5()->print(out); out->print(" ");
2222 tmp6()->print(out); out->print(" ");
2223 #endif
2012 out->print("[hdr:%d]", header_size()); out->print(" "); 2224 out->print("[hdr:%d]", header_size()); out->print(" ");
2013 out->print("[obj:%d]", object_size()); out->print(" "); 2225 out->print("[obj:%d]", object_size()); out->print(" ");
2014 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2226 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2015 } 2227 }
2016 2228
2020 result_opr()->print(out); out->print(" "); 2232 result_opr()->print(out); out->print(" ");
2021 } 2233 }
2022 2234
2023 // LIR_Op2 2235 // LIR_Op2
2024 void LIR_Op2::print_instr(outputStream* out) const { 2236 void LIR_Op2::print_instr(outputStream* out) const {
2237 #ifndef MIPS64
2025 if (code() == lir_cmove) { 2238 if (code() == lir_cmove) {
2026 print_condition(out, condition()); out->print(" "); 2239 print_condition(out, condition()); out->print(" ");
2027 } 2240 }
2241 #endif
2028 in_opr1()->print(out); out->print(" "); 2242 in_opr1()->print(out); out->print(" ");
2029 in_opr2()->print(out); out->print(" "); 2243 in_opr2()->print(out); out->print(" ");
2030 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 2244 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2031 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 2245 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2032 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 2246 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2041 obj()->print(out); out->print(" "); 2255 obj()->print(out); out->print(" ");
2042 tmp1()->print(out); out->print(" "); 2256 tmp1()->print(out); out->print(" ");
2043 tmp2()->print(out); out->print(" "); 2257 tmp2()->print(out); out->print(" ");
2044 tmp3()->print(out); out->print(" "); 2258 tmp3()->print(out); out->print(" ");
2045 tmp4()->print(out); out->print(" "); 2259 tmp4()->print(out); out->print(" ");
2260 #ifdef MIPS64
2261 tmp5()->print(out); out->print(" ");
2262 #endif
2046 out->print("[type:0x%x]", type()); out->print(" "); 2263 out->print("[type:0x%x]", type()); out->print(" ");
2047 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2264 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2048 } 2265 }
2049 2266
2050 2267
2084 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2301 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2085 } 2302 }
2086 2303
2087 #ifdef ASSERT 2304 #ifdef ASSERT
2088 void LIR_OpAssert::print_instr(outputStream* out) const { 2305 void LIR_OpAssert::print_instr(outputStream* out) const {
2306 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2307 Unimplemented();
2308 /*
2089 print_condition(out, condition()); out->print(" "); 2309 print_condition(out, condition()); out->print(" ");
2090 in_opr1()->print(out); out->print(" "); 2310 in_opr1()->print(out); out->print(" ");
2091 in_opr2()->print(out); out->print(", \""); 2311 in_opr2()->print(out); out->print(", \"");
2092 out->print("%s", msg()); out->print("\""); 2312 out->print("%s", msg()); out->print("\"");
2313 */
2093 } 2314 }
2094 #endif 2315 #endif
2095 2316
2096 2317
2097 void LIR_OpDelay::print_instr(outputStream* out) const { 2318 void LIR_OpDelay::print_instr(outputStream* out) const {

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