Thu, 24 May 2018 18:41:44 +0800
Merge
aoqi@0 | 1 | /* |
dlong@7598 | 2 | * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@1 | 25 | /* |
aoqi@1 | 26 | * This file has been modified by Loongson Technology in 2015. These |
aoqi@1 | 27 | * modifications are Copyright (c) 2015 Loongson Technology, and are made |
aoqi@1 | 28 | * available on the same license terms set forth above. |
aoqi@1 | 29 | */ |
aoqi@1 | 30 | |
aoqi@0 | 31 | #include "precompiled.hpp" |
aoqi@0 | 32 | #include "c1/c1_InstructionPrinter.hpp" |
aoqi@0 | 33 | #include "c1/c1_LIR.hpp" |
aoqi@0 | 34 | #include "c1/c1_LIRAssembler.hpp" |
aoqi@0 | 35 | #include "c1/c1_ValueStack.hpp" |
aoqi@0 | 36 | #include "ci/ciInstance.hpp" |
aoqi@0 | 37 | #include "runtime/sharedRuntime.hpp" |
aoqi@0 | 38 | |
aoqi@0 | 39 | Register LIR_OprDesc::as_register() const { |
aoqi@0 | 40 | return FrameMap::cpu_rnr2reg(cpu_regnr()); |
aoqi@0 | 41 | } |
aoqi@0 | 42 | |
aoqi@0 | 43 | Register LIR_OprDesc::as_register_lo() const { |
aoqi@0 | 44 | return FrameMap::cpu_rnr2reg(cpu_regnrLo()); |
aoqi@0 | 45 | } |
aoqi@0 | 46 | |
aoqi@0 | 47 | Register LIR_OprDesc::as_register_hi() const { |
aoqi@0 | 48 | return FrameMap::cpu_rnr2reg(cpu_regnrHi()); |
aoqi@0 | 49 | } |
aoqi@0 | 50 | |
aoqi@0 | 51 | #if defined(X86) |
aoqi@0 | 52 | |
aoqi@0 | 53 | XMMRegister LIR_OprDesc::as_xmm_float_reg() const { |
aoqi@0 | 54 | return FrameMap::nr2xmmreg(xmm_regnr()); |
aoqi@0 | 55 | } |
aoqi@0 | 56 | |
aoqi@0 | 57 | XMMRegister LIR_OprDesc::as_xmm_double_reg() const { |
aoqi@0 | 58 | assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); |
aoqi@0 | 59 | return FrameMap::nr2xmmreg(xmm_regnrLo()); |
aoqi@0 | 60 | } |
aoqi@0 | 61 | |
aoqi@0 | 62 | #endif // X86 |
aoqi@0 | 63 | |
aoqi@0 | 64 | #if defined(SPARC) || defined(PPC) |
aoqi@0 | 65 | |
aoqi@0 | 66 | FloatRegister LIR_OprDesc::as_float_reg() const { |
aoqi@0 | 67 | return FrameMap::nr2floatreg(fpu_regnr()); |
aoqi@0 | 68 | } |
aoqi@0 | 69 | |
aoqi@0 | 70 | FloatRegister LIR_OprDesc::as_double_reg() const { |
aoqi@0 | 71 | return FrameMap::nr2floatreg(fpu_regnrHi()); |
aoqi@0 | 72 | } |
aoqi@0 | 73 | |
aoqi@0 | 74 | #endif |
aoqi@1 | 75 | #ifdef MIPS64 |
aoqi@1 | 76 | |
aoqi@1 | 77 | FloatRegister LIR_OprDesc::as_float_reg() const { |
aoqi@1 | 78 | return FrameMap::nr2floatreg(fpu_regnr()); |
aoqi@1 | 79 | } |
aoqi@1 | 80 | |
aoqi@1 | 81 | FloatRegister LIR_OprDesc::as_double_reg() const { |
aoqi@1 | 82 | return FrameMap::nr2floatreg(fpu_regnrHi()); |
aoqi@1 | 83 | } |
aoqi@1 | 84 | |
aoqi@1 | 85 | FloatRegister LIR_OprDesc::as_fpu_lo() const { |
aoqi@1 | 86 | return FrameMap::nr2floatreg(fpu_regnrLo()); |
aoqi@1 | 87 | } |
aoqi@1 | 88 | |
aoqi@1 | 89 | FloatRegister LIR_OprDesc::as_fpu_hi() const { |
aoqi@1 | 90 | return FrameMap::nr2floatreg(fpu_regnrHi()); |
aoqi@1 | 91 | } |
aoqi@1 | 92 | |
aoqi@1 | 93 | #endif |
aoqi@0 | 94 | |
aoqi@0 | 95 | #ifdef ARM |
aoqi@0 | 96 | |
aoqi@0 | 97 | FloatRegister LIR_OprDesc::as_float_reg() const { |
aoqi@0 | 98 | return as_FloatRegister(fpu_regnr()); |
aoqi@0 | 99 | } |
aoqi@0 | 100 | |
aoqi@0 | 101 | FloatRegister LIR_OprDesc::as_double_reg() const { |
aoqi@0 | 102 | return as_FloatRegister(fpu_regnrLo()); |
aoqi@0 | 103 | } |
aoqi@0 | 104 | |
aoqi@0 | 105 | #endif |
aoqi@0 | 106 | |
aoqi@0 | 107 | |
aoqi@0 | 108 | LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
aoqi@0 | 109 | |
aoqi@0 | 110 | LIR_Opr LIR_OprFact::value_type(ValueType* type) { |
aoqi@0 | 111 | ValueTag tag = type->tag(); |
aoqi@0 | 112 | switch (tag) { |
aoqi@0 | 113 | case metaDataTag : { |
aoqi@0 | 114 | ClassConstant* c = type->as_ClassConstant(); |
aoqi@0 | 115 | if (c != NULL && !c->value()->is_loaded()) { |
aoqi@0 | 116 | return LIR_OprFact::metadataConst(NULL); |
aoqi@0 | 117 | } else if (c != NULL) { |
aoqi@0 | 118 | return LIR_OprFact::metadataConst(c->value()->constant_encoding()); |
aoqi@0 | 119 | } else { |
aoqi@0 | 120 | MethodConstant* m = type->as_MethodConstant(); |
aoqi@0 | 121 | assert (m != NULL, "not a class or a method?"); |
aoqi@0 | 122 | return LIR_OprFact::metadataConst(m->value()->constant_encoding()); |
aoqi@0 | 123 | } |
aoqi@0 | 124 | } |
aoqi@0 | 125 | case objectTag : { |
aoqi@0 | 126 | return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); |
aoqi@0 | 127 | } |
aoqi@0 | 128 | case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
aoqi@0 | 129 | case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
aoqi@0 | 130 | case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); |
aoqi@0 | 131 | case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); |
aoqi@0 | 132 | case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); |
aoqi@0 | 133 | default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
aoqi@0 | 134 | } |
aoqi@0 | 135 | } |
aoqi@0 | 136 | |
aoqi@0 | 137 | |
aoqi@0 | 138 | LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { |
aoqi@0 | 139 | switch (type->tag()) { |
aoqi@0 | 140 | case objectTag: return LIR_OprFact::oopConst(NULL); |
aoqi@0 | 141 | case addressTag:return LIR_OprFact::addressConst(0); |
aoqi@0 | 142 | case intTag: return LIR_OprFact::intConst(0); |
aoqi@0 | 143 | case floatTag: return LIR_OprFact::floatConst(0.0); |
aoqi@0 | 144 | case longTag: return LIR_OprFact::longConst(0); |
aoqi@0 | 145 | case doubleTag: return LIR_OprFact::doubleConst(0.0); |
aoqi@0 | 146 | default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
aoqi@0 | 147 | } |
aoqi@0 | 148 | return illegalOpr; |
aoqi@0 | 149 | } |
aoqi@0 | 150 | |
aoqi@0 | 151 | |
aoqi@0 | 152 | |
aoqi@0 | 153 | //--------------------------------------------------- |
aoqi@0 | 154 | |
aoqi@0 | 155 | |
aoqi@0 | 156 | LIR_Address::Scale LIR_Address::scale(BasicType type) { |
aoqi@0 | 157 | int elem_size = type2aelembytes(type); |
aoqi@0 | 158 | switch (elem_size) { |
aoqi@0 | 159 | case 1: return LIR_Address::times_1; |
aoqi@0 | 160 | case 2: return LIR_Address::times_2; |
aoqi@0 | 161 | case 4: return LIR_Address::times_4; |
aoqi@0 | 162 | case 8: return LIR_Address::times_8; |
aoqi@0 | 163 | } |
aoqi@0 | 164 | ShouldNotReachHere(); |
aoqi@0 | 165 | return LIR_Address::times_1; |
aoqi@0 | 166 | } |
aoqi@0 | 167 | |
aoqi@0 | 168 | |
aoqi@0 | 169 | #ifndef PRODUCT |
dlong@7598 | 170 | void LIR_Address::verify0() const { |
aoqi@0 | 171 | #if defined(SPARC) || defined(PPC) |
aoqi@0 | 172 | assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
aoqi@0 | 173 | assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
aoqi@0 | 174 | #endif |
aoqi@0 | 175 | #ifdef _LP64 |
aoqi@0 | 176 | assert(base()->is_cpu_register(), "wrong base operand"); |
aoqi@0 | 177 | assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); |
aoqi@1 | 178 | #ifndef MIPS64 |
aoqi@0 | 179 | assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
aoqi@0 | 180 | "wrong type for addresses"); |
aoqi@1 | 181 | #endif |
aoqi@0 | 182 | #else |
aoqi@0 | 183 | assert(base()->is_single_cpu(), "wrong base operand"); |
aoqi@0 | 184 | assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); |
aoqi@0 | 185 | assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
aoqi@0 | 186 | "wrong type for addresses"); |
aoqi@0 | 187 | #endif |
aoqi@0 | 188 | } |
aoqi@0 | 189 | #endif |
aoqi@0 | 190 | |
aoqi@0 | 191 | |
aoqi@0 | 192 | //--------------------------------------------------- |
aoqi@0 | 193 | |
aoqi@0 | 194 | char LIR_OprDesc::type_char(BasicType t) { |
aoqi@0 | 195 | switch (t) { |
aoqi@0 | 196 | case T_ARRAY: |
aoqi@0 | 197 | t = T_OBJECT; |
aoqi@0 | 198 | case T_BOOLEAN: |
aoqi@0 | 199 | case T_CHAR: |
aoqi@0 | 200 | case T_FLOAT: |
aoqi@0 | 201 | case T_DOUBLE: |
aoqi@0 | 202 | case T_BYTE: |
aoqi@0 | 203 | case T_SHORT: |
aoqi@0 | 204 | case T_INT: |
aoqi@0 | 205 | case T_LONG: |
aoqi@0 | 206 | case T_OBJECT: |
aoqi@0 | 207 | case T_ADDRESS: |
aoqi@0 | 208 | case T_VOID: |
aoqi@0 | 209 | return ::type2char(t); |
aoqi@0 | 210 | case T_METADATA: |
aoqi@0 | 211 | return 'M'; |
aoqi@0 | 212 | case T_ILLEGAL: |
aoqi@0 | 213 | return '?'; |
aoqi@0 | 214 | |
aoqi@0 | 215 | default: |
aoqi@0 | 216 | ShouldNotReachHere(); |
aoqi@0 | 217 | return '?'; |
aoqi@0 | 218 | } |
aoqi@0 | 219 | } |
aoqi@0 | 220 | |
aoqi@0 | 221 | #ifndef PRODUCT |
aoqi@0 | 222 | void LIR_OprDesc::validate_type() const { |
aoqi@0 | 223 | |
aoqi@0 | 224 | #ifdef ASSERT |
aoqi@0 | 225 | if (!is_pointer() && !is_illegal()) { |
aoqi@0 | 226 | OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 |
aoqi@0 | 227 | switch (as_BasicType(type_field())) { |
aoqi@0 | 228 | case T_LONG: |
aoqi@0 | 229 | assert((kindfield == cpu_register || kindfield == stack_value) && |
aoqi@0 | 230 | size_field() == double_size, "must match"); |
aoqi@0 | 231 | break; |
aoqi@0 | 232 | case T_FLOAT: |
aoqi@0 | 233 | // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
aoqi@0 | 234 | assert((kindfield == fpu_register || kindfield == stack_value |
aoqi@0 | 235 | ARM_ONLY(|| kindfield == cpu_register) |
aoqi@0 | 236 | PPC_ONLY(|| kindfield == cpu_register) ) && |
aoqi@0 | 237 | size_field() == single_size, "must match"); |
aoqi@0 | 238 | break; |
aoqi@0 | 239 | case T_DOUBLE: |
aoqi@0 | 240 | // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
aoqi@0 | 241 | assert((kindfield == fpu_register || kindfield == stack_value |
aoqi@0 | 242 | ARM_ONLY(|| kindfield == cpu_register) |
aoqi@0 | 243 | PPC_ONLY(|| kindfield == cpu_register) ) && |
aoqi@0 | 244 | size_field() == double_size, "must match"); |
aoqi@0 | 245 | break; |
aoqi@0 | 246 | case T_BOOLEAN: |
aoqi@0 | 247 | case T_CHAR: |
aoqi@0 | 248 | case T_BYTE: |
aoqi@0 | 249 | case T_SHORT: |
aoqi@0 | 250 | case T_INT: |
aoqi@0 | 251 | case T_ADDRESS: |
aoqi@0 | 252 | case T_OBJECT: |
aoqi@0 | 253 | case T_METADATA: |
aoqi@0 | 254 | case T_ARRAY: |
aoqi@0 | 255 | assert((kindfield == cpu_register || kindfield == stack_value) && |
aoqi@0 | 256 | size_field() == single_size, "must match"); |
aoqi@0 | 257 | break; |
aoqi@0 | 258 | |
aoqi@0 | 259 | case T_ILLEGAL: |
aoqi@0 | 260 | // XXX TKR also means unknown right now |
aoqi@0 | 261 | // assert(is_illegal(), "must match"); |
aoqi@0 | 262 | break; |
aoqi@0 | 263 | |
aoqi@0 | 264 | default: |
aoqi@0 | 265 | ShouldNotReachHere(); |
aoqi@0 | 266 | } |
aoqi@0 | 267 | } |
aoqi@0 | 268 | #endif |
aoqi@0 | 269 | |
aoqi@0 | 270 | } |
aoqi@0 | 271 | #endif // PRODUCT |
aoqi@0 | 272 | |
aoqi@0 | 273 | |
aoqi@0 | 274 | bool LIR_OprDesc::is_oop() const { |
aoqi@0 | 275 | if (is_pointer()) { |
aoqi@0 | 276 | return pointer()->is_oop_pointer(); |
aoqi@0 | 277 | } else { |
aoqi@0 | 278 | OprType t= type_field(); |
aoqi@0 | 279 | assert(t != unknown_type, "not set"); |
aoqi@0 | 280 | return t == object_type; |
aoqi@0 | 281 | } |
aoqi@0 | 282 | } |
aoqi@0 | 283 | |
aoqi@0 | 284 | |
aoqi@0 | 285 | |
aoqi@0 | 286 | void LIR_Op2::verify() const { |
aoqi@0 | 287 | #ifdef ASSERT |
aoqi@0 | 288 | switch (code()) { |
aoqi@0 | 289 | case lir_cmove: |
aoqi@0 | 290 | case lir_xchg: |
aoqi@0 | 291 | break; |
aoqi@0 | 292 | |
aoqi@0 | 293 | default: |
aoqi@0 | 294 | assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), |
aoqi@0 | 295 | "can't produce oops from arith"); |
aoqi@0 | 296 | } |
aoqi@0 | 297 | |
aoqi@0 | 298 | if (TwoOperandLIRForm) { |
aoqi@0 | 299 | switch (code()) { |
aoqi@0 | 300 | case lir_add: |
aoqi@0 | 301 | case lir_sub: |
aoqi@0 | 302 | case lir_mul: |
aoqi@0 | 303 | case lir_mul_strictfp: |
aoqi@0 | 304 | case lir_div: |
aoqi@0 | 305 | case lir_div_strictfp: |
aoqi@0 | 306 | case lir_rem: |
aoqi@0 | 307 | case lir_logic_and: |
aoqi@0 | 308 | case lir_logic_or: |
aoqi@0 | 309 | case lir_logic_xor: |
aoqi@0 | 310 | case lir_shl: |
aoqi@0 | 311 | case lir_shr: |
aoqi@0 | 312 | assert(in_opr1() == result_opr(), "opr1 and result must match"); |
aoqi@0 | 313 | assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); |
aoqi@0 | 314 | break; |
aoqi@0 | 315 | |
aoqi@0 | 316 | // special handling for lir_ushr because of write barriers |
aoqi@0 | 317 | case lir_ushr: |
aoqi@0 | 318 | assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); |
aoqi@0 | 319 | assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); |
aoqi@0 | 320 | break; |
aoqi@0 | 321 | |
aoqi@0 | 322 | } |
aoqi@0 | 323 | } |
aoqi@0 | 324 | #endif |
aoqi@0 | 325 | } |
aoqi@0 | 326 | |
aoqi@0 | 327 | |
aoqi@1 | 328 | #ifndef MIPS64 |
aoqi@0 | 329 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) |
aoqi@0 | 330 | : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
aoqi@0 | 331 | , _cond(cond) |
aoqi@0 | 332 | , _type(type) |
aoqi@0 | 333 | , _label(block->label()) |
aoqi@0 | 334 | , _block(block) |
aoqi@0 | 335 | , _ublock(NULL) |
aoqi@0 | 336 | , _stub(NULL) { |
aoqi@0 | 337 | } |
aoqi@0 | 338 | |
aoqi@0 | 339 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : |
aoqi@0 | 340 | LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
aoqi@0 | 341 | , _cond(cond) |
aoqi@0 | 342 | , _type(type) |
aoqi@0 | 343 | , _label(stub->entry()) |
aoqi@0 | 344 | , _block(NULL) |
aoqi@0 | 345 | , _ublock(NULL) |
aoqi@0 | 346 | , _stub(stub) { |
aoqi@0 | 347 | } |
aoqi@0 | 348 | |
aoqi@0 | 349 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) |
aoqi@0 | 350 | : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
aoqi@0 | 351 | , _cond(cond) |
aoqi@0 | 352 | , _type(type) |
aoqi@0 | 353 | , _label(block->label()) |
aoqi@0 | 354 | , _block(block) |
aoqi@0 | 355 | , _ublock(ublock) |
aoqi@0 | 356 | , _stub(NULL) |
aoqi@0 | 357 | { |
aoqi@0 | 358 | } |
aoqi@0 | 359 | |
aoqi@1 | 360 | #else |
aoqi@1 | 361 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, |
aoqi@1 | 362 | BlockBegin* block): |
aoqi@1 | 363 | LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)), |
aoqi@1 | 364 | _cond(cond), |
aoqi@1 | 365 | _type(type), |
aoqi@1 | 366 | _label(block->label()), |
aoqi@1 | 367 | _block(block), |
aoqi@1 | 368 | _ublock(NULL), |
aoqi@1 | 369 | _stub(NULL) { |
aoqi@1 | 370 | } |
aoqi@1 | 371 | |
aoqi@1 | 372 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, |
aoqi@1 | 373 | CodeStub* stub): |
aoqi@1 | 374 | LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)), |
aoqi@1 | 375 | _cond(cond), |
aoqi@1 | 376 | _type(type), |
aoqi@1 | 377 | _label(stub->entry()), |
aoqi@1 | 378 | _block(NULL), |
aoqi@1 | 379 | _ublock(NULL), |
aoqi@1 | 380 | _stub(stub) { |
aoqi@1 | 381 | } |
aoqi@1 | 382 | |
aoqi@1 | 383 | |
aoqi@1 | 384 | LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, |
aoqi@1 | 385 | BlockBegin *block, BlockBegin *ublock): |
aoqi@1 | 386 | LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)), |
aoqi@1 | 387 | _cond(cond), |
aoqi@1 | 388 | _type(type), |
aoqi@1 | 389 | _label(block->label()), |
aoqi@1 | 390 | _block(block), |
aoqi@1 | 391 | _ublock(ublock), |
aoqi@1 | 392 | _stub(NULL) { |
aoqi@1 | 393 | } |
aoqi@1 | 394 | |
aoqi@1 | 395 | #endif |
aoqi@1 | 396 | |
aoqi@0 | 397 | void LIR_OpBranch::change_block(BlockBegin* b) { |
aoqi@0 | 398 | assert(_block != NULL, "must have old block"); |
aoqi@0 | 399 | assert(_block->label() == label(), "must be equal"); |
aoqi@0 | 400 | |
aoqi@0 | 401 | _block = b; |
aoqi@0 | 402 | _label = b->label(); |
aoqi@0 | 403 | } |
aoqi@0 | 404 | |
aoqi@0 | 405 | void LIR_OpBranch::change_ublock(BlockBegin* b) { |
aoqi@0 | 406 | assert(_ublock != NULL, "must have old block"); |
aoqi@0 | 407 | _ublock = b; |
aoqi@0 | 408 | } |
aoqi@0 | 409 | |
aoqi@0 | 410 | void LIR_OpBranch::negate_cond() { |
aoqi@0 | 411 | switch (_cond) { |
aoqi@0 | 412 | case lir_cond_equal: _cond = lir_cond_notEqual; break; |
aoqi@0 | 413 | case lir_cond_notEqual: _cond = lir_cond_equal; break; |
aoqi@0 | 414 | case lir_cond_less: _cond = lir_cond_greaterEqual; break; |
aoqi@0 | 415 | case lir_cond_lessEqual: _cond = lir_cond_greater; break; |
aoqi@0 | 416 | case lir_cond_greaterEqual: _cond = lir_cond_less; break; |
aoqi@0 | 417 | case lir_cond_greater: _cond = lir_cond_lessEqual; break; |
aoqi@0 | 418 | default: ShouldNotReachHere(); |
aoqi@0 | 419 | } |
aoqi@0 | 420 | } |
aoqi@0 | 421 | |
aoqi@0 | 422 | |
aoqi@0 | 423 | LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, |
aoqi@0 | 424 | LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
aoqi@0 | 425 | bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, |
aoqi@0 | 426 | CodeStub* stub) |
aoqi@0 | 427 | |
aoqi@0 | 428 | : LIR_Op(code, result, NULL) |
aoqi@0 | 429 | , _object(object) |
aoqi@0 | 430 | , _array(LIR_OprFact::illegalOpr) |
aoqi@0 | 431 | , _klass(klass) |
aoqi@0 | 432 | , _tmp1(tmp1) |
aoqi@0 | 433 | , _tmp2(tmp2) |
aoqi@0 | 434 | , _tmp3(tmp3) |
aoqi@0 | 435 | , _fast_check(fast_check) |
aoqi@0 | 436 | , _stub(stub) |
aoqi@0 | 437 | , _info_for_patch(info_for_patch) |
aoqi@0 | 438 | , _info_for_exception(info_for_exception) |
aoqi@0 | 439 | , _profiled_method(NULL) |
aoqi@0 | 440 | , _profiled_bci(-1) |
aoqi@0 | 441 | , _should_profile(false) |
aoqi@0 | 442 | { |
aoqi@0 | 443 | if (code == lir_checkcast) { |
aoqi@0 | 444 | assert(info_for_exception != NULL, "checkcast throws exceptions"); |
aoqi@0 | 445 | } else if (code == lir_instanceof) { |
aoqi@0 | 446 | assert(info_for_exception == NULL, "instanceof throws no exceptions"); |
aoqi@0 | 447 | } else { |
aoqi@0 | 448 | ShouldNotReachHere(); |
aoqi@0 | 449 | } |
aoqi@0 | 450 | } |
aoqi@0 | 451 | |
aoqi@0 | 452 | |
aoqi@0 | 453 | |
aoqi@0 | 454 | LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) |
aoqi@0 | 455 | : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) |
aoqi@0 | 456 | , _object(object) |
aoqi@0 | 457 | , _array(array) |
aoqi@0 | 458 | , _klass(NULL) |
aoqi@0 | 459 | , _tmp1(tmp1) |
aoqi@0 | 460 | , _tmp2(tmp2) |
aoqi@0 | 461 | , _tmp3(tmp3) |
aoqi@0 | 462 | , _fast_check(false) |
aoqi@0 | 463 | , _stub(NULL) |
aoqi@0 | 464 | , _info_for_patch(NULL) |
aoqi@0 | 465 | , _info_for_exception(info_for_exception) |
aoqi@0 | 466 | , _profiled_method(NULL) |
aoqi@0 | 467 | , _profiled_bci(-1) |
aoqi@0 | 468 | , _should_profile(false) |
aoqi@0 | 469 | { |
aoqi@0 | 470 | if (code == lir_store_check) { |
aoqi@0 | 471 | _stub = new ArrayStoreExceptionStub(object, info_for_exception); |
aoqi@0 | 472 | assert(info_for_exception != NULL, "store_check throws exceptions"); |
aoqi@0 | 473 | } else { |
aoqi@0 | 474 | ShouldNotReachHere(); |
aoqi@0 | 475 | } |
aoqi@0 | 476 | } |
aoqi@0 | 477 | |
aoqi@0 | 478 | |
aoqi@0 | 479 | LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, |
aoqi@0 | 480 | LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) |
aoqi@0 | 481 | : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) |
aoqi@0 | 482 | , _tmp(tmp) |
aoqi@0 | 483 | , _src(src) |
aoqi@0 | 484 | , _src_pos(src_pos) |
aoqi@0 | 485 | , _dst(dst) |
aoqi@0 | 486 | , _dst_pos(dst_pos) |
aoqi@0 | 487 | , _flags(flags) |
aoqi@0 | 488 | , _expected_type(expected_type) |
aoqi@0 | 489 | , _length(length) { |
aoqi@0 | 490 | _stub = new ArrayCopyStub(this); |
aoqi@0 | 491 | } |
aoqi@0 | 492 | |
aoqi@0 | 493 | LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) |
aoqi@0 | 494 | : LIR_Op(lir_updatecrc32, res, NULL) |
aoqi@0 | 495 | , _crc(crc) |
aoqi@0 | 496 | , _val(val) { |
aoqi@0 | 497 | } |
aoqi@0 | 498 | |
aoqi@0 | 499 | //-------------------verify-------------------------- |
aoqi@0 | 500 | |
aoqi@0 | 501 | void LIR_Op1::verify() const { |
aoqi@0 | 502 | switch(code()) { |
aoqi@0 | 503 | case lir_move: |
aoqi@0 | 504 | assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); |
aoqi@0 | 505 | break; |
aoqi@0 | 506 | case lir_null_check: |
aoqi@0 | 507 | assert(in_opr()->is_register(), "must be"); |
aoqi@0 | 508 | break; |
aoqi@0 | 509 | case lir_return: |
aoqi@0 | 510 | assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); |
aoqi@0 | 511 | break; |
aoqi@0 | 512 | } |
aoqi@0 | 513 | } |
aoqi@0 | 514 | |
aoqi@0 | 515 | void LIR_OpRTCall::verify() const { |
aoqi@0 | 516 | assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); |
aoqi@0 | 517 | } |
aoqi@0 | 518 | |
aoqi@0 | 519 | //-------------------visits-------------------------- |
aoqi@0 | 520 | |
aoqi@0 | 521 | // complete rework of LIR instruction visitor. |
zmajo@7854 | 522 | // The virtual call for each instruction type is replaced by a big |
aoqi@0 | 523 | // switch that adds the operands for each instruction |
aoqi@0 | 524 | |
aoqi@0 | 525 | void LIR_OpVisitState::visit(LIR_Op* op) { |
aoqi@0 | 526 | // copy information from the LIR_Op |
aoqi@0 | 527 | reset(); |
aoqi@0 | 528 | set_op(op); |
aoqi@0 | 529 | |
aoqi@0 | 530 | switch (op->code()) { |
aoqi@0 | 531 | |
aoqi@0 | 532 | // LIR_Op0 |
aoqi@0 | 533 | case lir_word_align: // result and info always invalid |
aoqi@0 | 534 | case lir_backwardbranch_target: // result and info always invalid |
aoqi@0 | 535 | case lir_build_frame: // result and info always invalid |
aoqi@0 | 536 | case lir_fpop_raw: // result and info always invalid |
aoqi@0 | 537 | case lir_24bit_FPU: // result and info always invalid |
aoqi@0 | 538 | case lir_reset_FPU: // result and info always invalid |
aoqi@0 | 539 | case lir_breakpoint: // result and info always invalid |
aoqi@0 | 540 | case lir_membar: // result and info always invalid |
aoqi@0 | 541 | case lir_membar_acquire: // result and info always invalid |
aoqi@0 | 542 | case lir_membar_release: // result and info always invalid |
aoqi@0 | 543 | case lir_membar_loadload: // result and info always invalid |
aoqi@0 | 544 | case lir_membar_storestore: // result and info always invalid |
aoqi@0 | 545 | case lir_membar_loadstore: // result and info always invalid |
aoqi@0 | 546 | case lir_membar_storeload: // result and info always invalid |
aoqi@0 | 547 | { |
aoqi@0 | 548 | assert(op->as_Op0() != NULL, "must be"); |
aoqi@0 | 549 | assert(op->_info == NULL, "info not used by this instruction"); |
aoqi@0 | 550 | assert(op->_result->is_illegal(), "not used"); |
aoqi@0 | 551 | break; |
aoqi@0 | 552 | } |
aoqi@0 | 553 | |
aoqi@0 | 554 | case lir_nop: // may have info, result always invalid |
aoqi@0 | 555 | case lir_std_entry: // may have result, info always invalid |
aoqi@0 | 556 | case lir_osr_entry: // may have result, info always invalid |
aoqi@0 | 557 | case lir_get_thread: // may have result, info always invalid |
aoqi@0 | 558 | { |
aoqi@0 | 559 | assert(op->as_Op0() != NULL, "must be"); |
aoqi@0 | 560 | if (op->_info != NULL) do_info(op->_info); |
aoqi@0 | 561 | if (op->_result->is_valid()) do_output(op->_result); |
aoqi@0 | 562 | break; |
aoqi@0 | 563 | } |
aoqi@0 | 564 | |
aoqi@0 | 565 | |
aoqi@0 | 566 | // LIR_OpLabel |
aoqi@0 | 567 | case lir_label: // result and info always invalid |
aoqi@0 | 568 | { |
aoqi@0 | 569 | assert(op->as_OpLabel() != NULL, "must be"); |
aoqi@0 | 570 | assert(op->_info == NULL, "info not used by this instruction"); |
aoqi@0 | 571 | assert(op->_result->is_illegal(), "not used"); |
aoqi@0 | 572 | break; |
aoqi@0 | 573 | } |
aoqi@0 | 574 | |
aoqi@0 | 575 | |
aoqi@0 | 576 | // LIR_Op1 |
aoqi@0 | 577 | case lir_fxch: // input always valid, result and info always invalid |
aoqi@0 | 578 | case lir_fld: // input always valid, result and info always invalid |
aoqi@0 | 579 | case lir_ffree: // input always valid, result and info always invalid |
aoqi@0 | 580 | case lir_push: // input always valid, result and info always invalid |
aoqi@0 | 581 | case lir_pop: // input always valid, result and info always invalid |
aoqi@0 | 582 | case lir_return: // input always valid, result and info always invalid |
aoqi@0 | 583 | case lir_leal: // input and result always valid, info always invalid |
aoqi@0 | 584 | case lir_neg: // input and result always valid, info always invalid |
aoqi@0 | 585 | case lir_monaddr: // input and result always valid, info always invalid |
aoqi@0 | 586 | case lir_null_check: // input and info always valid, result always invalid |
aoqi@0 | 587 | case lir_move: // input and result always valid, may have info |
aoqi@0 | 588 | case lir_pack64: // input and result always valid |
aoqi@0 | 589 | case lir_unpack64: // input and result always valid |
aoqi@0 | 590 | case lir_prefetchr: // input always valid, result and info always invalid |
aoqi@0 | 591 | case lir_prefetchw: // input always valid, result and info always invalid |
aoqi@0 | 592 | { |
aoqi@0 | 593 | assert(op->as_Op1() != NULL, "must be"); |
aoqi@0 | 594 | LIR_Op1* op1 = (LIR_Op1*)op; |
aoqi@0 | 595 | |
aoqi@0 | 596 | if (op1->_info) do_info(op1->_info); |
aoqi@0 | 597 | if (op1->_opr->is_valid()) do_input(op1->_opr); |
aoqi@0 | 598 | if (op1->_result->is_valid()) do_output(op1->_result); |
aoqi@0 | 599 | |
aoqi@0 | 600 | break; |
aoqi@0 | 601 | } |
aoqi@0 | 602 | |
aoqi@0 | 603 | case lir_safepoint: |
aoqi@0 | 604 | { |
aoqi@0 | 605 | assert(op->as_Op1() != NULL, "must be"); |
aoqi@0 | 606 | LIR_Op1* op1 = (LIR_Op1*)op; |
aoqi@0 | 607 | |
aoqi@0 | 608 | assert(op1->_info != NULL, ""); do_info(op1->_info); |
aoqi@0 | 609 | if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register |
aoqi@0 | 610 | assert(op1->_result->is_illegal(), "safepoint does not produce value"); |
aoqi@0 | 611 | |
aoqi@0 | 612 | break; |
aoqi@0 | 613 | } |
aoqi@0 | 614 | |
aoqi@0 | 615 | // LIR_OpConvert; |
aoqi@0 | 616 | case lir_convert: // input and result always valid, info always invalid |
aoqi@0 | 617 | { |
aoqi@0 | 618 | assert(op->as_OpConvert() != NULL, "must be"); |
aoqi@0 | 619 | LIR_OpConvert* opConvert = (LIR_OpConvert*)op; |
aoqi@0 | 620 | |
aoqi@0 | 621 | assert(opConvert->_info == NULL, "must be"); |
aoqi@0 | 622 | if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); |
aoqi@0 | 623 | if (opConvert->_result->is_valid()) do_output(opConvert->_result); |
aoqi@0 | 624 | #ifdef PPC |
aoqi@0 | 625 | if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
aoqi@0 | 626 | if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
aoqi@0 | 627 | #endif |
aoqi@0 | 628 | do_stub(opConvert->_stub); |
aoqi@0 | 629 | |
aoqi@0 | 630 | break; |
aoqi@0 | 631 | } |
aoqi@0 | 632 | |
aoqi@0 | 633 | // LIR_OpBranch; |
aoqi@0 | 634 | case lir_branch: // may have info, input and result register always invalid |
aoqi@0 | 635 | case lir_cond_float_branch: // may have info, input and result register always invalid |
aoqi@0 | 636 | { |
aoqi@0 | 637 | assert(op->as_OpBranch() != NULL, "must be"); |
aoqi@0 | 638 | LIR_OpBranch* opBranch = (LIR_OpBranch*)op; |
aoqi@0 | 639 | |
aoqi@1 | 640 | #ifdef MIPS64 |
aoqi@1 | 641 | if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1); |
aoqi@1 | 642 | if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2); |
aoqi@1 | 643 | if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1); |
aoqi@1 | 644 | if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2); |
aoqi@1 | 645 | if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3); |
aoqi@1 | 646 | if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4); |
aoqi@1 | 647 | if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5); |
aoqi@1 | 648 | #endif |
aoqi@0 | 649 | if (opBranch->_info != NULL) do_info(opBranch->_info); |
aoqi@0 | 650 | assert(opBranch->_result->is_illegal(), "not used"); |
aoqi@0 | 651 | if (opBranch->_stub != NULL) opBranch->stub()->visit(this); |
aoqi@0 | 652 | |
aoqi@0 | 653 | break; |
aoqi@0 | 654 | } |
aoqi@0 | 655 | |
aoqi@0 | 656 | |
aoqi@0 | 657 | // LIR_OpAllocObj |
aoqi@0 | 658 | case lir_alloc_object: |
aoqi@0 | 659 | { |
aoqi@0 | 660 | assert(op->as_OpAllocObj() != NULL, "must be"); |
aoqi@0 | 661 | LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; |
aoqi@0 | 662 | |
aoqi@0 | 663 | if (opAllocObj->_info) do_info(opAllocObj->_info); |
aoqi@0 | 664 | if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
aoqi@0 | 665 | do_temp(opAllocObj->_opr); |
aoqi@0 | 666 | } |
aoqi@0 | 667 | if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
aoqi@0 | 668 | if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); |
aoqi@0 | 669 | if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); |
aoqi@0 | 670 | if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); |
aoqi@1 | 671 | #ifdef MIPS64 |
aoqi@1 | 672 | if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5); |
aoqi@1 | 673 | if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6); |
aoqi@1 | 674 | #endif |
aoqi@0 | 675 | if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); |
aoqi@0 | 676 | do_stub(opAllocObj->_stub); |
aoqi@0 | 677 | break; |
aoqi@0 | 678 | } |
aoqi@0 | 679 | |
aoqi@0 | 680 | |
aoqi@0 | 681 | // LIR_OpRoundFP; |
aoqi@0 | 682 | case lir_roundfp: { |
aoqi@0 | 683 | assert(op->as_OpRoundFP() != NULL, "must be"); |
aoqi@0 | 684 | LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; |
aoqi@0 | 685 | |
aoqi@0 | 686 | assert(op->_info == NULL, "info not used by this instruction"); |
aoqi@0 | 687 | assert(opRoundFP->_tmp->is_illegal(), "not used"); |
aoqi@0 | 688 | do_input(opRoundFP->_opr); |
aoqi@0 | 689 | do_output(opRoundFP->_result); |
aoqi@0 | 690 | |
aoqi@0 | 691 | break; |
aoqi@0 | 692 | } |
aoqi@0 | 693 | |
aoqi@0 | 694 | |
aoqi@0 | 695 | // LIR_Op2 |
aoqi@1 | 696 | #ifdef MIPS64 |
aoqi@1 | 697 | case lir_null_check_for_branch: |
aoqi@1 | 698 | #else |
aoqi@0 | 699 | case lir_cmp: |
aoqi@1 | 700 | #endif |
aoqi@0 | 701 | case lir_cmp_l2i: |
aoqi@0 | 702 | case lir_ucmp_fd2i: |
aoqi@0 | 703 | case lir_cmp_fd2i: |
aoqi@0 | 704 | case lir_add: |
aoqi@0 | 705 | case lir_sub: |
aoqi@0 | 706 | case lir_mul: |
aoqi@0 | 707 | case lir_div: |
aoqi@0 | 708 | case lir_rem: |
aoqi@0 | 709 | case lir_sqrt: |
aoqi@0 | 710 | case lir_abs: |
aoqi@0 | 711 | case lir_logic_and: |
aoqi@0 | 712 | case lir_logic_or: |
aoqi@0 | 713 | case lir_logic_xor: |
aoqi@0 | 714 | case lir_shl: |
aoqi@0 | 715 | case lir_shr: |
aoqi@0 | 716 | case lir_ushr: |
aoqi@0 | 717 | case lir_xadd: |
aoqi@0 | 718 | case lir_xchg: |
aoqi@0 | 719 | case lir_assert: |
aoqi@0 | 720 | { |
aoqi@0 | 721 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 722 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 723 | assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
aoqi@0 | 724 | op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
aoqi@0 | 725 | |
aoqi@0 | 726 | if (op2->_info) do_info(op2->_info); |
aoqi@0 | 727 | if (op2->_opr1->is_valid()) do_input(op2->_opr1); |
aoqi@0 | 728 | if (op2->_opr2->is_valid()) do_input(op2->_opr2); |
aoqi@0 | 729 | if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
aoqi@0 | 730 | if (op2->_result->is_valid()) do_output(op2->_result); |
aoqi@0 | 731 | if (op->code() == lir_xchg || op->code() == lir_xadd) { |
aoqi@0 | 732 | // on ARM and PPC, return value is loaded first so could |
aoqi@0 | 733 | // destroy inputs. On other platforms that implement those |
aoqi@0 | 734 | // (x86, sparc), the extra constrainsts are harmless. |
aoqi@0 | 735 | if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
aoqi@0 | 736 | if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
aoqi@0 | 737 | } |
aoqi@0 | 738 | |
aoqi@0 | 739 | break; |
aoqi@0 | 740 | } |
aoqi@0 | 741 | |
aoqi@0 | 742 | // special handling for cmove: right input operand must not be equal |
aoqi@0 | 743 | // to the result operand, otherwise the backend fails |
aoqi@0 | 744 | case lir_cmove: |
aoqi@0 | 745 | { |
aoqi@0 | 746 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 747 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 748 | |
aoqi@0 | 749 | assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && |
aoqi@0 | 750 | op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
aoqi@0 | 751 | assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); |
aoqi@0 | 752 | |
aoqi@0 | 753 | do_input(op2->_opr1); |
aoqi@0 | 754 | do_input(op2->_opr2); |
aoqi@0 | 755 | do_temp(op2->_opr2); |
aoqi@0 | 756 | do_output(op2->_result); |
aoqi@0 | 757 | |
aoqi@0 | 758 | break; |
aoqi@0 | 759 | } |
aoqi@0 | 760 | |
aoqi@0 | 761 | // vspecial handling for strict operations: register input operands |
aoqi@0 | 762 | // as temp to guarantee that they do not overlap with other |
aoqi@0 | 763 | // registers |
aoqi@0 | 764 | case lir_mul_strictfp: |
aoqi@0 | 765 | case lir_div_strictfp: |
aoqi@0 | 766 | { |
aoqi@0 | 767 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 768 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 769 | |
aoqi@0 | 770 | assert(op2->_info == NULL, "not used"); |
aoqi@0 | 771 | assert(op2->_opr1->is_valid(), "used"); |
aoqi@0 | 772 | assert(op2->_opr2->is_valid(), "used"); |
aoqi@0 | 773 | assert(op2->_result->is_valid(), "used"); |
aoqi@0 | 774 | assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
aoqi@0 | 775 | op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
aoqi@0 | 776 | |
aoqi@0 | 777 | do_input(op2->_opr1); do_temp(op2->_opr1); |
aoqi@0 | 778 | do_input(op2->_opr2); do_temp(op2->_opr2); |
aoqi@0 | 779 | if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
aoqi@0 | 780 | do_output(op2->_result); |
aoqi@0 | 781 | |
aoqi@0 | 782 | break; |
aoqi@0 | 783 | } |
aoqi@0 | 784 | |
aoqi@0 | 785 | case lir_throw: { |
aoqi@0 | 786 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 787 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 788 | |
aoqi@0 | 789 | if (op2->_info) do_info(op2->_info); |
aoqi@0 | 790 | if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
aoqi@0 | 791 | if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter |
aoqi@0 | 792 | assert(op2->_result->is_illegal(), "no result"); |
aoqi@0 | 793 | assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
aoqi@0 | 794 | op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
aoqi@0 | 795 | |
aoqi@0 | 796 | break; |
aoqi@0 | 797 | } |
aoqi@0 | 798 | |
aoqi@0 | 799 | case lir_unwind: { |
aoqi@0 | 800 | assert(op->as_Op1() != NULL, "must be"); |
aoqi@0 | 801 | LIR_Op1* op1 = (LIR_Op1*)op; |
aoqi@0 | 802 | |
aoqi@0 | 803 | assert(op1->_info == NULL, "no info"); |
aoqi@0 | 804 | assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
aoqi@0 | 805 | assert(op1->_result->is_illegal(), "no result"); |
aoqi@0 | 806 | |
aoqi@0 | 807 | break; |
aoqi@0 | 808 | } |
aoqi@0 | 809 | |
aoqi@0 | 810 | |
aoqi@0 | 811 | case lir_tan: |
aoqi@0 | 812 | case lir_sin: |
aoqi@0 | 813 | case lir_cos: |
aoqi@0 | 814 | case lir_log: |
aoqi@0 | 815 | case lir_log10: |
aoqi@0 | 816 | case lir_exp: { |
aoqi@0 | 817 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 818 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 819 | |
aoqi@0 | 820 | // On x86 tan/sin/cos need two temporary fpu stack slots and |
aoqi@0 | 821 | // log/log10 need one so handle opr2 and tmp as temp inputs. |
aoqi@0 | 822 | // Register input operand as temp to guarantee that it doesn't |
aoqi@0 | 823 | // overlap with the input. |
aoqi@0 | 824 | assert(op2->_info == NULL, "not used"); |
aoqi@0 | 825 | assert(op2->_tmp5->is_illegal(), "not used"); |
aoqi@0 | 826 | assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); |
aoqi@0 | 827 | assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); |
aoqi@0 | 828 | assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); |
aoqi@0 | 829 | assert(op2->_opr1->is_valid(), "used"); |
aoqi@0 | 830 | do_input(op2->_opr1); do_temp(op2->_opr1); |
aoqi@0 | 831 | |
aoqi@0 | 832 | if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
aoqi@0 | 833 | if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
aoqi@0 | 834 | if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); |
aoqi@0 | 835 | if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); |
aoqi@0 | 836 | if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); |
aoqi@0 | 837 | if (op2->_result->is_valid()) do_output(op2->_result); |
aoqi@0 | 838 | |
aoqi@0 | 839 | break; |
aoqi@0 | 840 | } |
aoqi@0 | 841 | |
aoqi@0 | 842 | case lir_pow: { |
aoqi@0 | 843 | assert(op->as_Op2() != NULL, "must be"); |
aoqi@0 | 844 | LIR_Op2* op2 = (LIR_Op2*)op; |
aoqi@0 | 845 | |
aoqi@0 | 846 | // On x86 pow needs two temporary fpu stack slots: tmp1 and |
aoqi@0 | 847 | // tmp2. Register input operands as temps to guarantee that it |
aoqi@0 | 848 | // doesn't overlap with the temporary slots. |
aoqi@0 | 849 | assert(op2->_info == NULL, "not used"); |
aoqi@0 | 850 | assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); |
aoqi@0 | 851 | assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() |
aoqi@0 | 852 | && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); |
aoqi@0 | 853 | assert(op2->_result->is_valid(), "used"); |
aoqi@0 | 854 | |
aoqi@0 | 855 | do_input(op2->_opr1); do_temp(op2->_opr1); |
aoqi@0 | 856 | do_input(op2->_opr2); do_temp(op2->_opr2); |
aoqi@0 | 857 | do_temp(op2->_tmp1); |
aoqi@0 | 858 | do_temp(op2->_tmp2); |
aoqi@0 | 859 | do_temp(op2->_tmp3); |
aoqi@0 | 860 | do_temp(op2->_tmp4); |
aoqi@0 | 861 | do_temp(op2->_tmp5); |
aoqi@0 | 862 | do_output(op2->_result); |
aoqi@0 | 863 | |
aoqi@0 | 864 | break; |
aoqi@0 | 865 | } |
aoqi@0 | 866 | |
aoqi@0 | 867 | // LIR_Op3 |
aoqi@1 | 868 | #ifdef MIPS64 |
aoqi@1 | 869 | case lir_frem: |
aoqi@1 | 870 | #endif |
aoqi@0 | 871 | case lir_idiv: |
aoqi@0 | 872 | case lir_irem: { |
aoqi@0 | 873 | assert(op->as_Op3() != NULL, "must be"); |
aoqi@0 | 874 | LIR_Op3* op3= (LIR_Op3*)op; |
aoqi@0 | 875 | |
aoqi@0 | 876 | if (op3->_info) do_info(op3->_info); |
aoqi@0 | 877 | if (op3->_opr1->is_valid()) do_input(op3->_opr1); |
aoqi@0 | 878 | |
aoqi@0 | 879 | // second operand is input and temp, so ensure that second operand |
aoqi@0 | 880 | // and third operand get not the same register |
aoqi@0 | 881 | if (op3->_opr2->is_valid()) do_input(op3->_opr2); |
aoqi@0 | 882 | if (op3->_opr2->is_valid()) do_temp(op3->_opr2); |
aoqi@0 | 883 | if (op3->_opr3->is_valid()) do_temp(op3->_opr3); |
aoqi@0 | 884 | |
aoqi@0 | 885 | if (op3->_result->is_valid()) do_output(op3->_result); |
aoqi@0 | 886 | |
aoqi@0 | 887 | break; |
aoqi@0 | 888 | } |
aoqi@0 | 889 | |
aoqi@0 | 890 | |
aoqi@0 | 891 | // LIR_OpJavaCall |
aoqi@0 | 892 | case lir_static_call: |
aoqi@0 | 893 | case lir_optvirtual_call: |
aoqi@0 | 894 | case lir_icvirtual_call: |
aoqi@0 | 895 | case lir_virtual_call: |
aoqi@0 | 896 | case lir_dynamic_call: { |
aoqi@0 | 897 | LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); |
aoqi@0 | 898 | assert(opJavaCall != NULL, "must be"); |
aoqi@0 | 899 | |
aoqi@0 | 900 | if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); |
aoqi@0 | 901 | |
aoqi@0 | 902 | // only visit register parameters |
aoqi@0 | 903 | int n = opJavaCall->_arguments->length(); |
aoqi@0 | 904 | for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { |
aoqi@0 | 905 | if (!opJavaCall->_arguments->at(i)->is_pointer()) { |
aoqi@0 | 906 | do_input(*opJavaCall->_arguments->adr_at(i)); |
aoqi@0 | 907 | } |
aoqi@0 | 908 | } |
aoqi@0 | 909 | |
aoqi@0 | 910 | if (opJavaCall->_info) do_info(opJavaCall->_info); |
zmajo@7854 | 911 | if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr && |
zmajo@7854 | 912 | opJavaCall->is_method_handle_invoke()) { |
aoqi@0 | 913 | opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); |
aoqi@0 | 914 | do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); |
aoqi@0 | 915 | } |
aoqi@0 | 916 | do_call(); |
aoqi@0 | 917 | if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); |
aoqi@0 | 918 | |
aoqi@0 | 919 | break; |
aoqi@0 | 920 | } |
aoqi@0 | 921 | |
aoqi@0 | 922 | |
aoqi@0 | 923 | // LIR_OpRTCall |
aoqi@0 | 924 | case lir_rtcall: { |
aoqi@0 | 925 | assert(op->as_OpRTCall() != NULL, "must be"); |
aoqi@0 | 926 | LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; |
aoqi@0 | 927 | |
aoqi@0 | 928 | // only visit register parameters |
aoqi@0 | 929 | int n = opRTCall->_arguments->length(); |
aoqi@0 | 930 | for (int i = 0; i < n; i++) { |
aoqi@0 | 931 | if (!opRTCall->_arguments->at(i)->is_pointer()) { |
aoqi@0 | 932 | do_input(*opRTCall->_arguments->adr_at(i)); |
aoqi@0 | 933 | } |
aoqi@0 | 934 | } |
aoqi@0 | 935 | if (opRTCall->_info) do_info(opRTCall->_info); |
aoqi@0 | 936 | if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); |
aoqi@0 | 937 | do_call(); |
aoqi@0 | 938 | if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); |
aoqi@0 | 939 | |
aoqi@0 | 940 | break; |
aoqi@0 | 941 | } |
aoqi@0 | 942 | |
aoqi@0 | 943 | |
aoqi@0 | 944 | // LIR_OpArrayCopy |
aoqi@0 | 945 | case lir_arraycopy: { |
aoqi@0 | 946 | assert(op->as_OpArrayCopy() != NULL, "must be"); |
aoqi@0 | 947 | LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; |
aoqi@0 | 948 | |
aoqi@0 | 949 | assert(opArrayCopy->_result->is_illegal(), "unused"); |
aoqi@0 | 950 | assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); |
aoqi@0 | 951 | assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); |
aoqi@0 | 952 | assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); |
aoqi@0 | 953 | assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); |
aoqi@0 | 954 | assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); |
aoqi@1 | 955 | #ifndef MIPS64 |
aoqi@0 | 956 | assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); |
aoqi@1 | 957 | #endif |
aoqi@0 | 958 | if (opArrayCopy->_info) do_info(opArrayCopy->_info); |
aoqi@0 | 959 | |
aoqi@0 | 960 | // the implementation of arraycopy always has a call into the runtime |
aoqi@0 | 961 | do_call(); |
aoqi@0 | 962 | |
aoqi@0 | 963 | break; |
aoqi@0 | 964 | } |
aoqi@0 | 965 | |
aoqi@0 | 966 | |
aoqi@0 | 967 | // LIR_OpUpdateCRC32 |
aoqi@0 | 968 | case lir_updatecrc32: { |
aoqi@0 | 969 | assert(op->as_OpUpdateCRC32() != NULL, "must be"); |
aoqi@0 | 970 | LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; |
aoqi@0 | 971 | |
aoqi@0 | 972 | assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); |
aoqi@0 | 973 | assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); |
aoqi@0 | 974 | assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); |
aoqi@0 | 975 | assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); |
aoqi@0 | 976 | |
aoqi@0 | 977 | break; |
aoqi@0 | 978 | } |
aoqi@0 | 979 | |
aoqi@0 | 980 | |
aoqi@0 | 981 | // LIR_OpLock |
aoqi@0 | 982 | case lir_lock: |
aoqi@0 | 983 | case lir_unlock: { |
aoqi@0 | 984 | assert(op->as_OpLock() != NULL, "must be"); |
aoqi@0 | 985 | LIR_OpLock* opLock = (LIR_OpLock*)op; |
aoqi@0 | 986 | |
aoqi@0 | 987 | if (opLock->_info) do_info(opLock->_info); |
aoqi@0 | 988 | |
aoqi@0 | 989 | // TODO: check if these operands really have to be temp |
aoqi@0 | 990 | // (or if input is sufficient). This may have influence on the oop map! |
aoqi@0 | 991 | assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); |
aoqi@0 | 992 | assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); |
aoqi@0 | 993 | assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); |
aoqi@0 | 994 | |
aoqi@0 | 995 | if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); |
aoqi@0 | 996 | assert(opLock->_result->is_illegal(), "unused"); |
aoqi@0 | 997 | |
aoqi@0 | 998 | do_stub(opLock->_stub); |
aoqi@0 | 999 | |
aoqi@0 | 1000 | break; |
aoqi@0 | 1001 | } |
aoqi@0 | 1002 | |
aoqi@0 | 1003 | |
aoqi@0 | 1004 | // LIR_OpDelay |
aoqi@0 | 1005 | case lir_delay_slot: { |
aoqi@0 | 1006 | assert(op->as_OpDelay() != NULL, "must be"); |
aoqi@0 | 1007 | LIR_OpDelay* opDelay = (LIR_OpDelay*)op; |
aoqi@0 | 1008 | |
aoqi@0 | 1009 | visit(opDelay->delay_op()); |
aoqi@0 | 1010 | break; |
aoqi@0 | 1011 | } |
aoqi@0 | 1012 | |
aoqi@0 | 1013 | // LIR_OpTypeCheck |
aoqi@0 | 1014 | case lir_instanceof: |
aoqi@0 | 1015 | case lir_checkcast: |
aoqi@0 | 1016 | case lir_store_check: { |
aoqi@0 | 1017 | assert(op->as_OpTypeCheck() != NULL, "must be"); |
aoqi@0 | 1018 | LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; |
aoqi@0 | 1019 | |
aoqi@0 | 1020 | if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); |
aoqi@0 | 1021 | if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); |
aoqi@0 | 1022 | if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); |
aoqi@0 | 1023 | if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { |
aoqi@0 | 1024 | do_temp(opTypeCheck->_object); |
aoqi@0 | 1025 | } |
aoqi@0 | 1026 | if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); |
aoqi@0 | 1027 | if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); |
aoqi@0 | 1028 | if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); |
aoqi@0 | 1029 | if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); |
aoqi@0 | 1030 | if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); |
aoqi@0 | 1031 | do_stub(opTypeCheck->_stub); |
aoqi@0 | 1032 | break; |
aoqi@0 | 1033 | } |
aoqi@0 | 1034 | |
aoqi@0 | 1035 | // LIR_OpCompareAndSwap |
aoqi@0 | 1036 | case lir_cas_long: |
aoqi@0 | 1037 | case lir_cas_obj: |
aoqi@0 | 1038 | case lir_cas_int: { |
aoqi@0 | 1039 | assert(op->as_OpCompareAndSwap() != NULL, "must be"); |
aoqi@0 | 1040 | LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; |
aoqi@0 | 1041 | |
aoqi@0 | 1042 | assert(opCompareAndSwap->_addr->is_valid(), "used"); |
aoqi@0 | 1043 | assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
aoqi@0 | 1044 | assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
aoqi@0 | 1045 | if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
aoqi@0 | 1046 | do_input(opCompareAndSwap->_addr); |
aoqi@0 | 1047 | do_temp(opCompareAndSwap->_addr); |
aoqi@0 | 1048 | do_input(opCompareAndSwap->_cmp_value); |
aoqi@0 | 1049 | do_temp(opCompareAndSwap->_cmp_value); |
aoqi@0 | 1050 | do_input(opCompareAndSwap->_new_value); |
aoqi@0 | 1051 | do_temp(opCompareAndSwap->_new_value); |
aoqi@0 | 1052 | if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
aoqi@0 | 1053 | if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); |
aoqi@0 | 1054 | if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); |
aoqi@0 | 1055 | |
aoqi@0 | 1056 | break; |
aoqi@0 | 1057 | } |
aoqi@0 | 1058 | |
aoqi@0 | 1059 | |
aoqi@0 | 1060 | // LIR_OpAllocArray; |
aoqi@0 | 1061 | case lir_alloc_array: { |
aoqi@0 | 1062 | assert(op->as_OpAllocArray() != NULL, "must be"); |
aoqi@0 | 1063 | LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; |
aoqi@0 | 1064 | |
aoqi@0 | 1065 | if (opAllocArray->_info) do_info(opAllocArray->_info); |
aoqi@0 | 1066 | if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); |
aoqi@0 | 1067 | if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); |
aoqi@0 | 1068 | if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); |
aoqi@0 | 1069 | if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); |
aoqi@0 | 1070 | if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); |
aoqi@0 | 1071 | if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); |
aoqi@1 | 1072 | #ifdef MIPS64 |
aoqi@1 | 1073 | if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5); |
aoqi@1 | 1074 | #endif |
aoqi@0 | 1075 | if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); |
aoqi@0 | 1076 | do_stub(opAllocArray->_stub); |
aoqi@0 | 1077 | break; |
aoqi@0 | 1078 | } |
aoqi@0 | 1079 | |
aoqi@0 | 1080 | // LIR_OpProfileCall: |
aoqi@0 | 1081 | case lir_profile_call: { |
aoqi@0 | 1082 | assert(op->as_OpProfileCall() != NULL, "must be"); |
aoqi@0 | 1083 | LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; |
aoqi@0 | 1084 | |
aoqi@0 | 1085 | if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); |
aoqi@0 | 1086 | assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); |
aoqi@0 | 1087 | assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); |
aoqi@0 | 1088 | break; |
aoqi@0 | 1089 | } |
aoqi@0 | 1090 | |
aoqi@0 | 1091 | // LIR_OpProfileType: |
aoqi@0 | 1092 | case lir_profile_type: { |
aoqi@0 | 1093 | assert(op->as_OpProfileType() != NULL, "must be"); |
aoqi@0 | 1094 | LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; |
aoqi@0 | 1095 | |
aoqi@0 | 1096 | do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); |
aoqi@0 | 1097 | do_input(opProfileType->_obj); |
aoqi@0 | 1098 | do_temp(opProfileType->_tmp); |
aoqi@0 | 1099 | break; |
aoqi@0 | 1100 | } |
aoqi@0 | 1101 | default: |
aoqi@0 | 1102 | ShouldNotReachHere(); |
aoqi@0 | 1103 | } |
aoqi@0 | 1104 | } |
aoqi@0 | 1105 | |
aoqi@0 | 1106 | |
aoqi@0 | 1107 | void LIR_OpVisitState::do_stub(CodeStub* stub) { |
aoqi@0 | 1108 | if (stub != NULL) { |
aoqi@0 | 1109 | stub->visit(this); |
aoqi@0 | 1110 | } |
aoqi@0 | 1111 | } |
aoqi@0 | 1112 | |
aoqi@0 | 1113 | XHandlers* LIR_OpVisitState::all_xhandler() { |
aoqi@0 | 1114 | XHandlers* result = NULL; |
aoqi@0 | 1115 | |
aoqi@0 | 1116 | int i; |
aoqi@0 | 1117 | for (i = 0; i < info_count(); i++) { |
aoqi@0 | 1118 | if (info_at(i)->exception_handlers() != NULL) { |
aoqi@0 | 1119 | result = info_at(i)->exception_handlers(); |
aoqi@0 | 1120 | break; |
aoqi@0 | 1121 | } |
aoqi@0 | 1122 | } |
aoqi@0 | 1123 | |
aoqi@0 | 1124 | #ifdef ASSERT |
aoqi@0 | 1125 | for (i = 0; i < info_count(); i++) { |
aoqi@0 | 1126 | assert(info_at(i)->exception_handlers() == NULL || |
aoqi@0 | 1127 | info_at(i)->exception_handlers() == result, |
aoqi@0 | 1128 | "only one xhandler list allowed per LIR-operation"); |
aoqi@0 | 1129 | } |
aoqi@0 | 1130 | #endif |
aoqi@0 | 1131 | |
aoqi@0 | 1132 | if (result != NULL) { |
aoqi@0 | 1133 | return result; |
aoqi@0 | 1134 | } else { |
aoqi@0 | 1135 | return new XHandlers(); |
aoqi@0 | 1136 | } |
aoqi@0 | 1137 | |
aoqi@0 | 1138 | return result; |
aoqi@0 | 1139 | } |
aoqi@0 | 1140 | |
aoqi@0 | 1141 | |
aoqi@0 | 1142 | #ifdef ASSERT |
aoqi@0 | 1143 | bool LIR_OpVisitState::no_operands(LIR_Op* op) { |
aoqi@0 | 1144 | visit(op); |
aoqi@0 | 1145 | |
aoqi@0 | 1146 | return opr_count(inputMode) == 0 && |
aoqi@0 | 1147 | opr_count(outputMode) == 0 && |
aoqi@0 | 1148 | opr_count(tempMode) == 0 && |
aoqi@0 | 1149 | info_count() == 0 && |
aoqi@0 | 1150 | !has_call() && |
aoqi@0 | 1151 | !has_slow_case(); |
aoqi@0 | 1152 | } |
aoqi@0 | 1153 | #endif |
aoqi@0 | 1154 | |
aoqi@0 | 1155 | //--------------------------------------------------- |
aoqi@0 | 1156 | |
aoqi@0 | 1157 | |
aoqi@0 | 1158 | void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1159 | masm->emit_call(this); |
aoqi@0 | 1160 | } |
aoqi@0 | 1161 | |
aoqi@0 | 1162 | void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1163 | masm->emit_rtcall(this); |
aoqi@0 | 1164 | } |
aoqi@0 | 1165 | |
aoqi@0 | 1166 | void LIR_OpLabel::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1167 | masm->emit_opLabel(this); |
aoqi@0 | 1168 | } |
aoqi@0 | 1169 | |
aoqi@0 | 1170 | void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1171 | masm->emit_arraycopy(this); |
aoqi@0 | 1172 | masm->append_code_stub(stub()); |
aoqi@0 | 1173 | } |
aoqi@0 | 1174 | |
aoqi@0 | 1175 | void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1176 | masm->emit_updatecrc32(this); |
aoqi@0 | 1177 | } |
aoqi@0 | 1178 | |
aoqi@0 | 1179 | void LIR_Op0::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1180 | masm->emit_op0(this); |
aoqi@0 | 1181 | } |
aoqi@0 | 1182 | |
aoqi@0 | 1183 | void LIR_Op1::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1184 | masm->emit_op1(this); |
aoqi@0 | 1185 | } |
aoqi@0 | 1186 | |
aoqi@0 | 1187 | void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1188 | masm->emit_alloc_obj(this); |
aoqi@0 | 1189 | masm->append_code_stub(stub()); |
aoqi@0 | 1190 | } |
aoqi@0 | 1191 | |
aoqi@0 | 1192 | void LIR_OpBranch::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1193 | masm->emit_opBranch(this); |
aoqi@0 | 1194 | if (stub()) { |
aoqi@0 | 1195 | masm->append_code_stub(stub()); |
aoqi@0 | 1196 | } |
aoqi@0 | 1197 | } |
aoqi@0 | 1198 | |
aoqi@0 | 1199 | void LIR_OpConvert::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1200 | masm->emit_opConvert(this); |
aoqi@0 | 1201 | if (stub() != NULL) { |
aoqi@0 | 1202 | masm->append_code_stub(stub()); |
aoqi@0 | 1203 | } |
aoqi@0 | 1204 | } |
aoqi@0 | 1205 | |
aoqi@0 | 1206 | void LIR_Op2::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1207 | masm->emit_op2(this); |
aoqi@0 | 1208 | } |
aoqi@0 | 1209 | |
aoqi@0 | 1210 | void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1211 | masm->emit_alloc_array(this); |
aoqi@0 | 1212 | masm->append_code_stub(stub()); |
aoqi@0 | 1213 | } |
aoqi@0 | 1214 | |
aoqi@0 | 1215 | void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1216 | masm->emit_opTypeCheck(this); |
aoqi@0 | 1217 | if (stub()) { |
aoqi@0 | 1218 | masm->append_code_stub(stub()); |
aoqi@0 | 1219 | } |
aoqi@0 | 1220 | } |
aoqi@0 | 1221 | |
aoqi@0 | 1222 | void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1223 | masm->emit_compare_and_swap(this); |
aoqi@0 | 1224 | } |
aoqi@0 | 1225 | |
aoqi@0 | 1226 | void LIR_Op3::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1227 | masm->emit_op3(this); |
aoqi@0 | 1228 | } |
aoqi@0 | 1229 | |
aoqi@0 | 1230 | void LIR_OpLock::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1231 | masm->emit_lock(this); |
aoqi@0 | 1232 | if (stub()) { |
aoqi@0 | 1233 | masm->append_code_stub(stub()); |
aoqi@0 | 1234 | } |
aoqi@0 | 1235 | } |
aoqi@0 | 1236 | |
aoqi@0 | 1237 | #ifdef ASSERT |
aoqi@0 | 1238 | void LIR_OpAssert::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1239 | masm->emit_assert(this); |
aoqi@0 | 1240 | } |
aoqi@0 | 1241 | #endif |
aoqi@0 | 1242 | |
aoqi@0 | 1243 | void LIR_OpDelay::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1244 | masm->emit_delay(this); |
aoqi@0 | 1245 | } |
aoqi@0 | 1246 | |
aoqi@0 | 1247 | void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1248 | masm->emit_profile_call(this); |
aoqi@0 | 1249 | } |
aoqi@0 | 1250 | |
aoqi@0 | 1251 | void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { |
aoqi@0 | 1252 | masm->emit_profile_type(this); |
aoqi@0 | 1253 | } |
aoqi@0 | 1254 | |
aoqi@0 | 1255 | // LIR_List |
aoqi@0 | 1256 | LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) |
aoqi@0 | 1257 | : _operations(8) |
aoqi@0 | 1258 | , _compilation(compilation) |
aoqi@0 | 1259 | #ifndef PRODUCT |
aoqi@0 | 1260 | , _block(block) |
aoqi@0 | 1261 | #endif |
aoqi@0 | 1262 | #ifdef ASSERT |
aoqi@0 | 1263 | , _file(NULL) |
aoqi@0 | 1264 | , _line(0) |
aoqi@0 | 1265 | #endif |
aoqi@0 | 1266 | { } |
aoqi@0 | 1267 | |
aoqi@0 | 1268 | |
aoqi@0 | 1269 | #ifdef ASSERT |
aoqi@0 | 1270 | void LIR_List::set_file_and_line(const char * file, int line) { |
aoqi@0 | 1271 | const char * f = strrchr(file, '/'); |
aoqi@0 | 1272 | if (f == NULL) f = strrchr(file, '\\'); |
aoqi@0 | 1273 | if (f == NULL) { |
aoqi@0 | 1274 | f = file; |
aoqi@0 | 1275 | } else { |
aoqi@0 | 1276 | f++; |
aoqi@0 | 1277 | } |
aoqi@0 | 1278 | _file = f; |
aoqi@0 | 1279 | _line = line; |
aoqi@0 | 1280 | } |
aoqi@0 | 1281 | #endif |
aoqi@0 | 1282 | |
aoqi@0 | 1283 | |
aoqi@0 | 1284 | void LIR_List::append(LIR_InsertionBuffer* buffer) { |
aoqi@0 | 1285 | assert(this == buffer->lir_list(), "wrong lir list"); |
aoqi@0 | 1286 | const int n = _operations.length(); |
aoqi@0 | 1287 | |
aoqi@0 | 1288 | if (buffer->number_of_ops() > 0) { |
aoqi@0 | 1289 | // increase size of instructions list |
aoqi@0 | 1290 | _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); |
aoqi@0 | 1291 | // insert ops from buffer into instructions list |
aoqi@0 | 1292 | int op_index = buffer->number_of_ops() - 1; |
aoqi@0 | 1293 | int ip_index = buffer->number_of_insertion_points() - 1; |
aoqi@0 | 1294 | int from_index = n - 1; |
aoqi@0 | 1295 | int to_index = _operations.length() - 1; |
aoqi@0 | 1296 | for (; ip_index >= 0; ip_index --) { |
aoqi@0 | 1297 | int index = buffer->index_at(ip_index); |
aoqi@0 | 1298 | // make room after insertion point |
aoqi@0 | 1299 | while (index < from_index) { |
aoqi@0 | 1300 | _operations.at_put(to_index --, _operations.at(from_index --)); |
aoqi@0 | 1301 | } |
aoqi@0 | 1302 | // insert ops from buffer |
aoqi@0 | 1303 | for (int i = buffer->count_at(ip_index); i > 0; i --) { |
aoqi@0 | 1304 | _operations.at_put(to_index --, buffer->op_at(op_index --)); |
aoqi@0 | 1305 | } |
aoqi@0 | 1306 | } |
aoqi@0 | 1307 | } |
aoqi@0 | 1308 | |
aoqi@0 | 1309 | buffer->finish(); |
aoqi@0 | 1310 | } |
aoqi@0 | 1311 | |
aoqi@0 | 1312 | |
aoqi@0 | 1313 | void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { |
aoqi@0 | 1314 | assert(reg->type() == T_OBJECT, "bad reg"); |
aoqi@0 | 1315 | append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); |
aoqi@0 | 1316 | } |
aoqi@0 | 1317 | |
aoqi@0 | 1318 | void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { |
aoqi@0 | 1319 | assert(reg->type() == T_METADATA, "bad reg"); |
aoqi@0 | 1320 | append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); |
aoqi@0 | 1321 | } |
aoqi@0 | 1322 | |
aoqi@0 | 1323 | void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1324 | append(new LIR_Op1( |
aoqi@0 | 1325 | lir_move, |
aoqi@0 | 1326 | LIR_OprFact::address(addr), |
aoqi@0 | 1327 | src, |
aoqi@0 | 1328 | addr->type(), |
aoqi@0 | 1329 | patch_code, |
aoqi@0 | 1330 | info)); |
aoqi@0 | 1331 | } |
aoqi@0 | 1332 | |
aoqi@0 | 1333 | |
aoqi@0 | 1334 | void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1335 | append(new LIR_Op1( |
aoqi@0 | 1336 | lir_move, |
aoqi@0 | 1337 | LIR_OprFact::address(address), |
aoqi@0 | 1338 | dst, |
aoqi@0 | 1339 | address->type(), |
aoqi@0 | 1340 | patch_code, |
aoqi@0 | 1341 | info, lir_move_volatile)); |
aoqi@0 | 1342 | } |
aoqi@0 | 1343 | |
aoqi@0 | 1344 | void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@1 | 1345 | #ifndef MIPS64 |
aoqi@0 | 1346 | append(new LIR_Op1( |
aoqi@0 | 1347 | lir_move, |
aoqi@0 | 1348 | LIR_OprFact::address(new LIR_Address(base, offset, type)), |
aoqi@0 | 1349 | dst, |
aoqi@0 | 1350 | type, |
aoqi@0 | 1351 | patch_code, |
aoqi@0 | 1352 | info, lir_move_volatile)); |
aoqi@1 | 1353 | #else |
aoqi@1 | 1354 | add(base, offset, base); |
aoqi@1 | 1355 | append(new LIR_Op1( |
aoqi@1 | 1356 | lir_move, |
aoqi@1 | 1357 | LIR_OprFact::address(new LIR_Address(base, 0, type)), |
aoqi@1 | 1358 | dst, |
aoqi@1 | 1359 | type, |
aoqi@1 | 1360 | patch_code, |
aoqi@1 | 1361 | info, lir_move_volatile)); |
aoqi@1 | 1362 | #endif |
aoqi@0 | 1363 | } |
aoqi@0 | 1364 | |
aoqi@0 | 1365 | |
aoqi@0 | 1366 | void LIR_List::prefetch(LIR_Address* addr, bool is_store) { |
aoqi@0 | 1367 | append(new LIR_Op1( |
aoqi@0 | 1368 | is_store ? lir_prefetchw : lir_prefetchr, |
aoqi@0 | 1369 | LIR_OprFact::address(addr))); |
aoqi@0 | 1370 | } |
aoqi@0 | 1371 | |
aoqi@0 | 1372 | |
aoqi@0 | 1373 | void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1374 | append(new LIR_Op1( |
aoqi@0 | 1375 | lir_move, |
aoqi@0 | 1376 | LIR_OprFact::intConst(v), |
aoqi@0 | 1377 | LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), |
aoqi@0 | 1378 | type, |
aoqi@0 | 1379 | patch_code, |
aoqi@0 | 1380 | info)); |
aoqi@0 | 1381 | } |
aoqi@0 | 1382 | |
aoqi@0 | 1383 | |
aoqi@0 | 1384 | void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1385 | append(new LIR_Op1( |
aoqi@0 | 1386 | lir_move, |
aoqi@0 | 1387 | LIR_OprFact::oopConst(o), |
aoqi@0 | 1388 | LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), |
aoqi@0 | 1389 | type, |
aoqi@0 | 1390 | patch_code, |
aoqi@0 | 1391 | info)); |
aoqi@0 | 1392 | } |
aoqi@0 | 1393 | |
aoqi@0 | 1394 | |
aoqi@0 | 1395 | void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1396 | append(new LIR_Op1( |
aoqi@0 | 1397 | lir_move, |
aoqi@0 | 1398 | src, |
aoqi@0 | 1399 | LIR_OprFact::address(addr), |
aoqi@0 | 1400 | addr->type(), |
aoqi@0 | 1401 | patch_code, |
aoqi@0 | 1402 | info)); |
aoqi@0 | 1403 | } |
aoqi@0 | 1404 | |
aoqi@0 | 1405 | |
aoqi@0 | 1406 | void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@0 | 1407 | append(new LIR_Op1( |
aoqi@0 | 1408 | lir_move, |
aoqi@0 | 1409 | src, |
aoqi@0 | 1410 | LIR_OprFact::address(addr), |
aoqi@0 | 1411 | addr->type(), |
aoqi@0 | 1412 | patch_code, |
aoqi@0 | 1413 | info, |
aoqi@0 | 1414 | lir_move_volatile)); |
aoqi@0 | 1415 | } |
aoqi@0 | 1416 | |
aoqi@0 | 1417 | void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
aoqi@1 | 1418 | #ifndef MIPS64 |
aoqi@0 | 1419 | append(new LIR_Op1( |
aoqi@0 | 1420 | lir_move, |
aoqi@0 | 1421 | src, |
aoqi@0 | 1422 | LIR_OprFact::address(new LIR_Address(base, offset, type)), |
aoqi@0 | 1423 | type, |
aoqi@0 | 1424 | patch_code, |
aoqi@0 | 1425 | info, lir_move_volatile)); |
aoqi@1 | 1426 | #else |
aoqi@1 | 1427 | add(base, offset, base); |
aoqi@1 | 1428 | append(new LIR_Op1( |
aoqi@1 | 1429 | lir_move, |
aoqi@1 | 1430 | src, |
aoqi@1 | 1431 | LIR_OprFact::address(new LIR_Address(base, 0, type)), |
aoqi@1 | 1432 | type, |
aoqi@1 | 1433 | patch_code, |
aoqi@1 | 1434 | info, lir_move_volatile)); |
aoqi@1 | 1435 | |
aoqi@1 | 1436 | #endif |
aoqi@1 | 1437 | |
aoqi@0 | 1438 | } |
aoqi@0 | 1439 | |
aoqi@1 | 1440 | #ifdef MIPS64 |
aoqi@1 | 1441 | void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
aoqi@1 | 1442 | append(new LIR_Op3( |
aoqi@1 | 1443 | lir_frem, |
aoqi@1 | 1444 | left, |
aoqi@1 | 1445 | right, |
aoqi@1 | 1446 | tmp, |
aoqi@1 | 1447 | res, |
aoqi@1 | 1448 | info)); |
aoqi@1 | 1449 | } |
aoqi@1 | 1450 | #endif |
aoqi@0 | 1451 | |
aoqi@0 | 1452 | void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
aoqi@0 | 1453 | append(new LIR_Op3( |
aoqi@0 | 1454 | lir_idiv, |
aoqi@0 | 1455 | left, |
aoqi@0 | 1456 | right, |
aoqi@0 | 1457 | tmp, |
aoqi@0 | 1458 | res, |
aoqi@0 | 1459 | info)); |
aoqi@0 | 1460 | } |
aoqi@0 | 1461 | |
aoqi@0 | 1462 | |
aoqi@0 | 1463 | void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
aoqi@0 | 1464 | append(new LIR_Op3( |
aoqi@0 | 1465 | lir_idiv, |
aoqi@0 | 1466 | left, |
aoqi@0 | 1467 | LIR_OprFact::intConst(right), |
aoqi@0 | 1468 | tmp, |
aoqi@0 | 1469 | res, |
aoqi@0 | 1470 | info)); |
aoqi@0 | 1471 | } |
aoqi@0 | 1472 | |
aoqi@0 | 1473 | |
aoqi@0 | 1474 | void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
aoqi@0 | 1475 | append(new LIR_Op3( |
aoqi@0 | 1476 | lir_irem, |
aoqi@0 | 1477 | left, |
aoqi@0 | 1478 | right, |
aoqi@0 | 1479 | tmp, |
aoqi@0 | 1480 | res, |
aoqi@0 | 1481 | info)); |
aoqi@0 | 1482 | } |
aoqi@0 | 1483 | |
aoqi@0 | 1484 | |
aoqi@0 | 1485 | void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
aoqi@0 | 1486 | append(new LIR_Op3( |
aoqi@0 | 1487 | lir_irem, |
aoqi@0 | 1488 | left, |
aoqi@0 | 1489 | LIR_OprFact::intConst(right), |
aoqi@0 | 1490 | tmp, |
aoqi@0 | 1491 | res, |
aoqi@0 | 1492 | info)); |
aoqi@0 | 1493 | } |
aoqi@0 | 1494 | |
aoqi@0 | 1495 | |
aoqi@1 | 1496 | #ifndef MIPS64 |
aoqi@0 | 1497 | void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { |
aoqi@0 | 1498 | append(new LIR_Op2( |
aoqi@0 | 1499 | lir_cmp, |
aoqi@0 | 1500 | condition, |
aoqi@0 | 1501 | LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), |
aoqi@0 | 1502 | LIR_OprFact::intConst(c), |
aoqi@0 | 1503 | info)); |
aoqi@0 | 1504 | } |
aoqi@0 | 1505 | |
aoqi@8856 | 1506 | void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) { |
aoqi@8856 | 1507 | if (deoptimize_on_null) { |
aoqi@8856 | 1508 | // Emit an explicit null check and deoptimize if opr is null |
aoqi@8856 | 1509 | CodeStub* deopt = new DeoptimizeStub(info); |
aoqi@8856 | 1510 | cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL)); |
aoqi@8856 | 1511 | branch(lir_cond_equal, T_OBJECT, deopt); |
aoqi@8856 | 1512 | } else { |
aoqi@8856 | 1513 | // Emit an implicit null check |
aoqi@8856 | 1514 | append(new LIR_Op1(lir_null_check, opr, info)); |
aoqi@8856 | 1515 | } |
aoqi@8856 | 1516 | } |
aoqi@0 | 1517 | |
aoqi@0 | 1518 | void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { |
aoqi@0 | 1519 | append(new LIR_Op2( |
aoqi@0 | 1520 | lir_cmp, |
aoqi@0 | 1521 | condition, |
aoqi@0 | 1522 | reg, |
aoqi@0 | 1523 | LIR_OprFact::address(addr), |
aoqi@0 | 1524 | info)); |
aoqi@0 | 1525 | } |
aoqi@0 | 1526 | |
aoqi@0 | 1527 | void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, |
aoqi@0 | 1528 | int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { |
aoqi@0 | 1529 | append(new LIR_OpAllocObj( |
aoqi@0 | 1530 | klass, |
aoqi@0 | 1531 | dst, |
aoqi@0 | 1532 | t1, |
aoqi@0 | 1533 | t2, |
aoqi@0 | 1534 | t3, |
aoqi@0 | 1535 | t4, |
aoqi@0 | 1536 | header_size, |
aoqi@0 | 1537 | object_size, |
aoqi@0 | 1538 | init_check, |
aoqi@0 | 1539 | stub)); |
aoqi@0 | 1540 | } |
aoqi@0 | 1541 | |
aoqi@0 | 1542 | void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { |
aoqi@0 | 1543 | append(new LIR_OpAllocArray( |
aoqi@0 | 1544 | klass, |
aoqi@0 | 1545 | len, |
aoqi@0 | 1546 | dst, |
aoqi@0 | 1547 | t1, |
aoqi@0 | 1548 | t2, |
aoqi@0 | 1549 | t3, |
aoqi@0 | 1550 | t4, |
aoqi@0 | 1551 | type, |
aoqi@0 | 1552 | stub)); |
aoqi@0 | 1553 | } |
aoqi@1 | 1554 | #else |
aoqi@1 | 1555 | void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6, |
aoqi@1 | 1556 | int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { |
aoqi@1 | 1557 | append(new LIR_OpAllocObj( |
aoqi@1 | 1558 | klass, |
aoqi@1 | 1559 | dst, |
aoqi@1 | 1560 | t1, |
aoqi@1 | 1561 | t2, |
aoqi@1 | 1562 | t3, |
aoqi@1 | 1563 | t4, |
aoqi@1 | 1564 | t5, |
aoqi@1 | 1565 | t6, |
aoqi@1 | 1566 | header_size, |
aoqi@1 | 1567 | object_size, |
aoqi@1 | 1568 | init_check, |
aoqi@1 | 1569 | stub)); |
aoqi@1 | 1570 | } |
aoqi@1 | 1571 | void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5, |
aoqi@1 | 1572 | BasicType type, LIR_Opr klass, CodeStub* stub) { |
aoqi@1 | 1573 | append(new LIR_OpAllocArray( |
aoqi@1 | 1574 | klass, |
aoqi@1 | 1575 | len, |
aoqi@1 | 1576 | dst, |
aoqi@1 | 1577 | t1, |
aoqi@1 | 1578 | t2, |
aoqi@1 | 1579 | t3, |
aoqi@1 | 1580 | t4, |
aoqi@1 | 1581 | t5, |
aoqi@1 | 1582 | type, |
aoqi@1 | 1583 | stub)); |
aoqi@1 | 1584 | } |
aoqi@1 | 1585 | |
aoqi@1 | 1586 | #endif |
aoqi@0 | 1587 | |
aoqi@0 | 1588 | void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
aoqi@0 | 1589 | append(new LIR_Op2( |
aoqi@0 | 1590 | lir_shl, |
aoqi@0 | 1591 | value, |
aoqi@0 | 1592 | count, |
aoqi@0 | 1593 | dst, |
aoqi@0 | 1594 | tmp)); |
aoqi@0 | 1595 | } |
aoqi@0 | 1596 | |
aoqi@0 | 1597 | void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
aoqi@0 | 1598 | append(new LIR_Op2( |
aoqi@0 | 1599 | lir_shr, |
aoqi@0 | 1600 | value, |
aoqi@0 | 1601 | count, |
aoqi@0 | 1602 | dst, |
aoqi@0 | 1603 | tmp)); |
aoqi@0 | 1604 | } |
aoqi@0 | 1605 | |
aoqi@0 | 1606 | |
aoqi@0 | 1607 | void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
aoqi@0 | 1608 | append(new LIR_Op2( |
aoqi@0 | 1609 | lir_ushr, |
aoqi@0 | 1610 | value, |
aoqi@0 | 1611 | count, |
aoqi@0 | 1612 | dst, |
aoqi@0 | 1613 | tmp)); |
aoqi@0 | 1614 | } |
aoqi@0 | 1615 | |
aoqi@0 | 1616 | void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { |
aoqi@0 | 1617 | append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, |
aoqi@0 | 1618 | left, |
aoqi@0 | 1619 | right, |
aoqi@0 | 1620 | dst)); |
aoqi@0 | 1621 | } |
aoqi@0 | 1622 | |
aoqi@0 | 1623 | void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { |
aoqi@0 | 1624 | append(new LIR_OpLock( |
aoqi@0 | 1625 | lir_lock, |
aoqi@0 | 1626 | hdr, |
aoqi@0 | 1627 | obj, |
aoqi@0 | 1628 | lock, |
aoqi@0 | 1629 | scratch, |
aoqi@0 | 1630 | stub, |
aoqi@0 | 1631 | info)); |
aoqi@0 | 1632 | } |
aoqi@0 | 1633 | |
aoqi@0 | 1634 | void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
aoqi@0 | 1635 | append(new LIR_OpLock( |
aoqi@0 | 1636 | lir_unlock, |
aoqi@0 | 1637 | hdr, |
aoqi@0 | 1638 | obj, |
aoqi@0 | 1639 | lock, |
aoqi@0 | 1640 | scratch, |
aoqi@0 | 1641 | stub, |
aoqi@0 | 1642 | NULL)); |
aoqi@0 | 1643 | } |
aoqi@0 | 1644 | |
aoqi@0 | 1645 | |
aoqi@0 | 1646 | void check_LIR() { |
aoqi@0 | 1647 | // cannot do the proper checking as PRODUCT and other modes return different results |
aoqi@0 | 1648 | // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); |
aoqi@0 | 1649 | } |
aoqi@0 | 1650 | |
aoqi@0 | 1651 | |
aoqi@0 | 1652 | |
aoqi@0 | 1653 | void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, |
aoqi@0 | 1654 | LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, |
aoqi@0 | 1655 | CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, |
aoqi@0 | 1656 | ciMethod* profiled_method, int profiled_bci) { |
aoqi@0 | 1657 | LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, |
aoqi@0 | 1658 | tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); |
aoqi@0 | 1659 | if (profiled_method != NULL) { |
aoqi@0 | 1660 | c->set_profiled_method(profiled_method); |
aoqi@0 | 1661 | c->set_profiled_bci(profiled_bci); |
aoqi@0 | 1662 | c->set_should_profile(true); |
aoqi@0 | 1663 | } |
aoqi@0 | 1664 | append(c); |
aoqi@0 | 1665 | } |
aoqi@0 | 1666 | |
aoqi@0 | 1667 | void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { |
aoqi@0 | 1668 | LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); |
aoqi@0 | 1669 | if (profiled_method != NULL) { |
aoqi@0 | 1670 | c->set_profiled_method(profiled_method); |
aoqi@0 | 1671 | c->set_profiled_bci(profiled_bci); |
aoqi@0 | 1672 | c->set_should_profile(true); |
aoqi@0 | 1673 | } |
aoqi@0 | 1674 | append(c); |
aoqi@0 | 1675 | } |
aoqi@0 | 1676 | |
aoqi@0 | 1677 | void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
aoqi@0 | 1678 | CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { |
aoqi@0 | 1679 | LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); |
aoqi@0 | 1680 | if (profiled_method != NULL) { |
aoqi@0 | 1681 | c->set_profiled_method(profiled_method); |
aoqi@0 | 1682 | c->set_profiled_bci(profiled_bci); |
aoqi@0 | 1683 | c->set_should_profile(true); |
aoqi@0 | 1684 | } |
aoqi@0 | 1685 | append(c); |
aoqi@0 | 1686 | } |
aoqi@0 | 1687 | |
aoqi@1 | 1688 | #ifndef MIPS64 |
aoqi@0 | 1689 | void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 1690 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@0 | 1691 | append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
aoqi@0 | 1692 | } |
aoqi@0 | 1693 | |
aoqi@0 | 1694 | void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 1695 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@0 | 1696 | append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
aoqi@0 | 1697 | } |
aoqi@0 | 1698 | |
aoqi@0 | 1699 | void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 1700 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@0 | 1701 | append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
aoqi@0 | 1702 | } |
aoqi@1 | 1703 | #else |
aoqi@1 | 1704 | void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@1 | 1705 | // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, |
aoqi@1 | 1706 | // // implying successful swap of new_value into addr |
aoqi@1 | 1707 | append(new LIR_OpCompareAndSwap(lir_cas_long, |
aoqi@1 | 1708 | addr, |
aoqi@1 | 1709 | cmp_value, |
aoqi@1 | 1710 | new_value, |
aoqi@1 | 1711 | t1, |
aoqi@1 | 1712 | t2, |
aoqi@1 | 1713 | result)); |
aoqi@1 | 1714 | } |
aoqi@1 | 1715 | |
aoqi@1 | 1716 | void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@1 | 1717 | // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, |
aoqi@1 | 1718 | // // implying successful swap of new_value into addr |
aoqi@1 | 1719 | append(new LIR_OpCompareAndSwap(lir_cas_obj, |
aoqi@1 | 1720 | addr, |
aoqi@1 | 1721 | cmp_value, |
aoqi@1 | 1722 | new_value, |
aoqi@1 | 1723 | t1, |
aoqi@1 | 1724 | t2, |
aoqi@1 | 1725 | result)); |
aoqi@1 | 1726 | } |
aoqi@1 | 1727 | |
aoqi@1 | 1728 | void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
aoqi@1 | 1729 | // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, |
aoqi@1 | 1730 | // // implying successful swap of new_value into addr |
aoqi@1 | 1731 | append(new LIR_OpCompareAndSwap(lir_cas_int, |
aoqi@1 | 1732 | addr, |
aoqi@1 | 1733 | cmp_value, |
aoqi@1 | 1734 | new_value, |
aoqi@1 | 1735 | t1, |
aoqi@1 | 1736 | t2, |
aoqi@1 | 1737 | result)); |
aoqi@1 | 1738 | } |
aoqi@1 | 1739 | #endif |
aoqi@0 | 1740 | |
aoqi@0 | 1741 | |
aoqi@0 | 1742 | #ifdef PRODUCT |
aoqi@0 | 1743 | |
aoqi@0 | 1744 | void print_LIR(BlockList* blocks) { |
aoqi@0 | 1745 | } |
aoqi@0 | 1746 | |
aoqi@0 | 1747 | #else |
aoqi@0 | 1748 | // LIR_OprDesc |
aoqi@0 | 1749 | void LIR_OprDesc::print() const { |
aoqi@0 | 1750 | print(tty); |
aoqi@0 | 1751 | } |
aoqi@0 | 1752 | |
aoqi@0 | 1753 | void LIR_OprDesc::print(outputStream* out) const { |
aoqi@0 | 1754 | if (is_illegal()) { |
aoqi@0 | 1755 | return; |
aoqi@0 | 1756 | } |
aoqi@0 | 1757 | |
aoqi@0 | 1758 | out->print("["); |
aoqi@0 | 1759 | if (is_pointer()) { |
aoqi@0 | 1760 | pointer()->print_value_on(out); |
aoqi@0 | 1761 | } else if (is_single_stack()) { |
aoqi@0 | 1762 | out->print("stack:%d", single_stack_ix()); |
aoqi@0 | 1763 | } else if (is_double_stack()) { |
aoqi@0 | 1764 | out->print("dbl_stack:%d",double_stack_ix()); |
aoqi@0 | 1765 | } else if (is_virtual()) { |
aoqi@0 | 1766 | out->print("R%d", vreg_number()); |
aoqi@0 | 1767 | } else if (is_single_cpu()) { |
aoqi@0 | 1768 | out->print("%s", as_register()->name()); |
aoqi@0 | 1769 | } else if (is_double_cpu()) { |
aoqi@0 | 1770 | out->print("%s", as_register_hi()->name()); |
aoqi@0 | 1771 | out->print("%s", as_register_lo()->name()); |
aoqi@0 | 1772 | #if defined(X86) |
aoqi@0 | 1773 | } else if (is_single_xmm()) { |
aoqi@0 | 1774 | out->print("%s", as_xmm_float_reg()->name()); |
aoqi@0 | 1775 | } else if (is_double_xmm()) { |
aoqi@0 | 1776 | out->print("%s", as_xmm_double_reg()->name()); |
aoqi@0 | 1777 | } else if (is_single_fpu()) { |
aoqi@0 | 1778 | out->print("fpu%d", fpu_regnr()); |
aoqi@0 | 1779 | } else if (is_double_fpu()) { |
aoqi@0 | 1780 | out->print("fpu%d", fpu_regnrLo()); |
aoqi@0 | 1781 | #elif defined(ARM) |
aoqi@0 | 1782 | } else if (is_single_fpu()) { |
aoqi@0 | 1783 | out->print("s%d", fpu_regnr()); |
aoqi@0 | 1784 | } else if (is_double_fpu()) { |
aoqi@0 | 1785 | out->print("d%d", fpu_regnrLo() >> 1); |
aoqi@0 | 1786 | #else |
aoqi@0 | 1787 | } else if (is_single_fpu()) { |
aoqi@0 | 1788 | out->print("%s", as_float_reg()->name()); |
aoqi@0 | 1789 | } else if (is_double_fpu()) { |
aoqi@0 | 1790 | out->print("%s", as_double_reg()->name()); |
aoqi@0 | 1791 | #endif |
aoqi@0 | 1792 | |
aoqi@0 | 1793 | } else if (is_illegal()) { |
aoqi@0 | 1794 | out->print("-"); |
aoqi@0 | 1795 | } else { |
aoqi@0 | 1796 | out->print("Unknown Operand"); |
aoqi@0 | 1797 | } |
aoqi@0 | 1798 | if (!is_illegal()) { |
aoqi@0 | 1799 | out->print("|%c", type_char()); |
aoqi@0 | 1800 | } |
aoqi@0 | 1801 | if (is_register() && is_last_use()) { |
aoqi@0 | 1802 | out->print("(last_use)"); |
aoqi@0 | 1803 | } |
aoqi@0 | 1804 | out->print("]"); |
aoqi@0 | 1805 | } |
aoqi@0 | 1806 | |
aoqi@0 | 1807 | |
aoqi@0 | 1808 | // LIR_Address |
aoqi@0 | 1809 | void LIR_Const::print_value_on(outputStream* out) const { |
aoqi@0 | 1810 | switch (type()) { |
aoqi@0 | 1811 | case T_ADDRESS:out->print("address:%d",as_jint()); break; |
aoqi@0 | 1812 | case T_INT: out->print("int:%d", as_jint()); break; |
aoqi@0 | 1813 | case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; |
aoqi@0 | 1814 | case T_FLOAT: out->print("flt:%f", as_jfloat()); break; |
aoqi@0 | 1815 | case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; |
aoqi@0 | 1816 | case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; |
aoqi@0 | 1817 | case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; |
aoqi@0 | 1818 | default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; |
aoqi@0 | 1819 | } |
aoqi@0 | 1820 | } |
aoqi@0 | 1821 | |
aoqi@0 | 1822 | // LIR_Address |
aoqi@0 | 1823 | void LIR_Address::print_value_on(outputStream* out) const { |
aoqi@0 | 1824 | out->print("Base:"); _base->print(out); |
aoqi@1 | 1825 | #ifndef MIPS64 |
aoqi@0 | 1826 | if (!_index->is_illegal()) { |
aoqi@0 | 1827 | out->print(" Index:"); _index->print(out); |
aoqi@0 | 1828 | switch (scale()) { |
aoqi@0 | 1829 | case times_1: break; |
aoqi@0 | 1830 | case times_2: out->print(" * 2"); break; |
aoqi@0 | 1831 | case times_4: out->print(" * 4"); break; |
aoqi@0 | 1832 | case times_8: out->print(" * 8"); break; |
aoqi@0 | 1833 | } |
aoqi@0 | 1834 | } |
aoqi@1 | 1835 | #endif |
aoqi@0 | 1836 | out->print(" Disp: " INTX_FORMAT, _disp); |
aoqi@0 | 1837 | } |
aoqi@0 | 1838 | |
aoqi@0 | 1839 | // debug output of block header without InstructionPrinter |
aoqi@0 | 1840 | // (because phi functions are not necessary for LIR) |
aoqi@0 | 1841 | static void print_block(BlockBegin* x) { |
aoqi@0 | 1842 | // print block id |
aoqi@0 | 1843 | BlockEnd* end = x->end(); |
aoqi@0 | 1844 | tty->print("B%d ", x->block_id()); |
aoqi@0 | 1845 | |
aoqi@0 | 1846 | // print flags |
aoqi@0 | 1847 | if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); |
aoqi@0 | 1848 | if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); |
aoqi@0 | 1849 | if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); |
aoqi@0 | 1850 | if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); |
aoqi@0 | 1851 | if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); |
aoqi@0 | 1852 | if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); |
aoqi@0 | 1853 | if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); |
aoqi@0 | 1854 | |
aoqi@0 | 1855 | // print block bci range |
aoqi@0 | 1856 | tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); |
aoqi@0 | 1857 | |
aoqi@0 | 1858 | // print predecessors and successors |
aoqi@0 | 1859 | if (x->number_of_preds() > 0) { |
aoqi@0 | 1860 | tty->print("preds: "); |
aoqi@0 | 1861 | for (int i = 0; i < x->number_of_preds(); i ++) { |
aoqi@0 | 1862 | tty->print("B%d ", x->pred_at(i)->block_id()); |
aoqi@0 | 1863 | } |
aoqi@0 | 1864 | } |
aoqi@0 | 1865 | |
aoqi@0 | 1866 | if (x->number_of_sux() > 0) { |
aoqi@0 | 1867 | tty->print("sux: "); |
aoqi@0 | 1868 | for (int i = 0; i < x->number_of_sux(); i ++) { |
aoqi@0 | 1869 | tty->print("B%d ", x->sux_at(i)->block_id()); |
aoqi@0 | 1870 | } |
aoqi@0 | 1871 | } |
aoqi@0 | 1872 | |
aoqi@0 | 1873 | // print exception handlers |
aoqi@0 | 1874 | if (x->number_of_exception_handlers() > 0) { |
aoqi@0 | 1875 | tty->print("xhandler: "); |
aoqi@0 | 1876 | for (int i = 0; i < x->number_of_exception_handlers(); i++) { |
aoqi@0 | 1877 | tty->print("B%d ", x->exception_handler_at(i)->block_id()); |
aoqi@0 | 1878 | } |
aoqi@0 | 1879 | } |
aoqi@0 | 1880 | |
aoqi@0 | 1881 | tty->cr(); |
aoqi@0 | 1882 | } |
aoqi@0 | 1883 | |
aoqi@0 | 1884 | void print_LIR(BlockList* blocks) { |
aoqi@0 | 1885 | tty->print_cr("LIR:"); |
aoqi@0 | 1886 | int i; |
aoqi@0 | 1887 | for (i = 0; i < blocks->length(); i++) { |
aoqi@0 | 1888 | BlockBegin* bb = blocks->at(i); |
aoqi@0 | 1889 | print_block(bb); |
aoqi@0 | 1890 | tty->print("__id_Instruction___________________________________________"); tty->cr(); |
aoqi@0 | 1891 | bb->lir()->print_instructions(); |
aoqi@0 | 1892 | } |
aoqi@0 | 1893 | } |
aoqi@0 | 1894 | |
aoqi@0 | 1895 | void LIR_List::print_instructions() { |
aoqi@0 | 1896 | for (int i = 0; i < _operations.length(); i++) { |
aoqi@0 | 1897 | _operations.at(i)->print(); tty->cr(); |
aoqi@0 | 1898 | } |
aoqi@0 | 1899 | tty->cr(); |
aoqi@0 | 1900 | } |
aoqi@0 | 1901 | |
aoqi@0 | 1902 | // LIR_Ops printing routines |
aoqi@0 | 1903 | // LIR_Op |
aoqi@0 | 1904 | void LIR_Op::print_on(outputStream* out) const { |
aoqi@0 | 1905 | if (id() != -1 || PrintCFGToFile) { |
aoqi@0 | 1906 | out->print("%4d ", id()); |
aoqi@0 | 1907 | } else { |
aoqi@0 | 1908 | out->print(" "); |
aoqi@0 | 1909 | } |
aoqi@0 | 1910 | out->print("%s ", name()); |
aoqi@0 | 1911 | print_instr(out); |
aoqi@0 | 1912 | if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); |
aoqi@0 | 1913 | #ifdef ASSERT |
aoqi@0 | 1914 | if (Verbose && _file != NULL) { |
aoqi@0 | 1915 | out->print(" (%s:%d)", _file, _line); |
aoqi@0 | 1916 | } |
aoqi@0 | 1917 | #endif |
aoqi@0 | 1918 | } |
aoqi@0 | 1919 | |
aoqi@0 | 1920 | const char * LIR_Op::name() const { |
aoqi@0 | 1921 | const char* s = NULL; |
aoqi@0 | 1922 | switch(code()) { |
aoqi@0 | 1923 | // LIR_Op0 |
aoqi@0 | 1924 | case lir_membar: s = "membar"; break; |
aoqi@0 | 1925 | case lir_membar_acquire: s = "membar_acquire"; break; |
aoqi@0 | 1926 | case lir_membar_release: s = "membar_release"; break; |
aoqi@0 | 1927 | case lir_membar_loadload: s = "membar_loadload"; break; |
aoqi@0 | 1928 | case lir_membar_storestore: s = "membar_storestore"; break; |
aoqi@0 | 1929 | case lir_membar_loadstore: s = "membar_loadstore"; break; |
aoqi@0 | 1930 | case lir_membar_storeload: s = "membar_storeload"; break; |
aoqi@0 | 1931 | case lir_word_align: s = "word_align"; break; |
aoqi@0 | 1932 | case lir_label: s = "label"; break; |
aoqi@0 | 1933 | case lir_nop: s = "nop"; break; |
aoqi@0 | 1934 | case lir_backwardbranch_target: s = "backbranch"; break; |
aoqi@0 | 1935 | case lir_std_entry: s = "std_entry"; break; |
aoqi@0 | 1936 | case lir_osr_entry: s = "osr_entry"; break; |
aoqi@0 | 1937 | case lir_build_frame: s = "build_frm"; break; |
aoqi@0 | 1938 | case lir_fpop_raw: s = "fpop_raw"; break; |
aoqi@0 | 1939 | case lir_24bit_FPU: s = "24bit_FPU"; break; |
aoqi@0 | 1940 | case lir_reset_FPU: s = "reset_FPU"; break; |
aoqi@0 | 1941 | case lir_breakpoint: s = "breakpoint"; break; |
aoqi@0 | 1942 | case lir_get_thread: s = "get_thread"; break; |
aoqi@0 | 1943 | // LIR_Op1 |
aoqi@0 | 1944 | case lir_fxch: s = "fxch"; break; |
aoqi@0 | 1945 | case lir_fld: s = "fld"; break; |
aoqi@0 | 1946 | case lir_ffree: s = "ffree"; break; |
aoqi@0 | 1947 | case lir_push: s = "push"; break; |
aoqi@0 | 1948 | case lir_pop: s = "pop"; break; |
aoqi@0 | 1949 | case lir_null_check: s = "null_check"; break; |
aoqi@0 | 1950 | case lir_return: s = "return"; break; |
aoqi@0 | 1951 | case lir_safepoint: s = "safepoint"; break; |
aoqi@0 | 1952 | case lir_neg: s = "neg"; break; |
aoqi@0 | 1953 | case lir_leal: s = "leal"; break; |
aoqi@0 | 1954 | case lir_branch: s = "branch"; break; |
aoqi@0 | 1955 | case lir_cond_float_branch: s = "flt_cond_br"; break; |
aoqi@0 | 1956 | case lir_move: s = "move"; break; |
aoqi@0 | 1957 | case lir_roundfp: s = "roundfp"; break; |
aoqi@0 | 1958 | case lir_rtcall: s = "rtcall"; break; |
aoqi@0 | 1959 | case lir_throw: s = "throw"; break; |
aoqi@0 | 1960 | case lir_unwind: s = "unwind"; break; |
aoqi@0 | 1961 | case lir_convert: s = "convert"; break; |
aoqi@0 | 1962 | case lir_alloc_object: s = "alloc_obj"; break; |
aoqi@0 | 1963 | case lir_monaddr: s = "mon_addr"; break; |
aoqi@0 | 1964 | case lir_pack64: s = "pack64"; break; |
aoqi@0 | 1965 | case lir_unpack64: s = "unpack64"; break; |
aoqi@0 | 1966 | // LIR_Op2 |
aoqi@1 | 1967 | #ifdef MIPS64 |
aoqi@1 | 1968 | case lir_null_check_for_branch: s = "null_check_for_branch"; break; |
aoqi@1 | 1969 | #else |
aoqi@0 | 1970 | case lir_cmp: s = "cmp"; break; |
aoqi@1 | 1971 | #endif |
aoqi@0 | 1972 | case lir_cmp_l2i: s = "cmp_l2i"; break; |
aoqi@0 | 1973 | case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; |
aoqi@0 | 1974 | case lir_cmp_fd2i: s = "comp_fd2i"; break; |
aoqi@0 | 1975 | case lir_cmove: s = "cmove"; break; |
aoqi@0 | 1976 | case lir_add: s = "add"; break; |
aoqi@0 | 1977 | case lir_sub: s = "sub"; break; |
aoqi@0 | 1978 | case lir_mul: s = "mul"; break; |
aoqi@0 | 1979 | case lir_mul_strictfp: s = "mul_strictfp"; break; |
aoqi@0 | 1980 | case lir_div: s = "div"; break; |
aoqi@0 | 1981 | case lir_div_strictfp: s = "div_strictfp"; break; |
aoqi@0 | 1982 | case lir_rem: s = "rem"; break; |
aoqi@0 | 1983 | case lir_abs: s = "abs"; break; |
aoqi@0 | 1984 | case lir_sqrt: s = "sqrt"; break; |
aoqi@0 | 1985 | case lir_sin: s = "sin"; break; |
aoqi@0 | 1986 | case lir_cos: s = "cos"; break; |
aoqi@0 | 1987 | case lir_tan: s = "tan"; break; |
aoqi@0 | 1988 | case lir_log: s = "log"; break; |
aoqi@0 | 1989 | case lir_log10: s = "log10"; break; |
aoqi@0 | 1990 | case lir_exp: s = "exp"; break; |
aoqi@0 | 1991 | case lir_pow: s = "pow"; break; |
aoqi@0 | 1992 | case lir_logic_and: s = "logic_and"; break; |
aoqi@0 | 1993 | case lir_logic_or: s = "logic_or"; break; |
aoqi@0 | 1994 | case lir_logic_xor: s = "logic_xor"; break; |
aoqi@0 | 1995 | case lir_shl: s = "shift_left"; break; |
aoqi@0 | 1996 | case lir_shr: s = "shift_right"; break; |
aoqi@0 | 1997 | case lir_ushr: s = "ushift_right"; break; |
aoqi@0 | 1998 | case lir_alloc_array: s = "alloc_array"; break; |
aoqi@0 | 1999 | case lir_xadd: s = "xadd"; break; |
aoqi@0 | 2000 | case lir_xchg: s = "xchg"; break; |
aoqi@0 | 2001 | // LIR_Op3 |
aoqi@1 | 2002 | #ifdef MIPS64 |
aoqi@1 | 2003 | case lir_frem: s = "frem"; break; |
aoqi@1 | 2004 | #endif |
aoqi@0 | 2005 | case lir_idiv: s = "idiv"; break; |
aoqi@0 | 2006 | case lir_irem: s = "irem"; break; |
aoqi@0 | 2007 | // LIR_OpJavaCall |
aoqi@0 | 2008 | case lir_static_call: s = "static"; break; |
aoqi@0 | 2009 | case lir_optvirtual_call: s = "optvirtual"; break; |
aoqi@0 | 2010 | case lir_icvirtual_call: s = "icvirtual"; break; |
aoqi@0 | 2011 | case lir_virtual_call: s = "virtual"; break; |
aoqi@0 | 2012 | case lir_dynamic_call: s = "dynamic"; break; |
aoqi@0 | 2013 | // LIR_OpArrayCopy |
aoqi@0 | 2014 | case lir_arraycopy: s = "arraycopy"; break; |
aoqi@0 | 2015 | // LIR_OpUpdateCRC32 |
aoqi@0 | 2016 | case lir_updatecrc32: s = "updatecrc32"; break; |
aoqi@0 | 2017 | // LIR_OpLock |
aoqi@0 | 2018 | case lir_lock: s = "lock"; break; |
aoqi@0 | 2019 | case lir_unlock: s = "unlock"; break; |
aoqi@0 | 2020 | // LIR_OpDelay |
aoqi@0 | 2021 | case lir_delay_slot: s = "delay"; break; |
aoqi@0 | 2022 | // LIR_OpTypeCheck |
aoqi@0 | 2023 | case lir_instanceof: s = "instanceof"; break; |
aoqi@0 | 2024 | case lir_checkcast: s = "checkcast"; break; |
aoqi@0 | 2025 | case lir_store_check: s = "store_check"; break; |
aoqi@0 | 2026 | // LIR_OpCompareAndSwap |
aoqi@0 | 2027 | case lir_cas_long: s = "cas_long"; break; |
aoqi@0 | 2028 | case lir_cas_obj: s = "cas_obj"; break; |
aoqi@0 | 2029 | case lir_cas_int: s = "cas_int"; break; |
aoqi@0 | 2030 | // LIR_OpProfileCall |
aoqi@0 | 2031 | case lir_profile_call: s = "profile_call"; break; |
aoqi@0 | 2032 | // LIR_OpProfileType |
aoqi@0 | 2033 | case lir_profile_type: s = "profile_type"; break; |
aoqi@0 | 2034 | // LIR_OpAssert |
aoqi@0 | 2035 | #ifdef ASSERT |
aoqi@0 | 2036 | case lir_assert: s = "assert"; break; |
aoqi@0 | 2037 | #endif |
aoqi@0 | 2038 | case lir_none: ShouldNotReachHere();break; |
aoqi@0 | 2039 | default: s = "illegal_op"; break; |
aoqi@0 | 2040 | } |
aoqi@0 | 2041 | return s; |
aoqi@0 | 2042 | } |
aoqi@0 | 2043 | |
aoqi@0 | 2044 | // LIR_OpJavaCall |
aoqi@0 | 2045 | void LIR_OpJavaCall::print_instr(outputStream* out) const { |
aoqi@0 | 2046 | out->print("call: "); |
aoqi@0 | 2047 | out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); |
aoqi@0 | 2048 | if (receiver()->is_valid()) { |
aoqi@0 | 2049 | out->print(" [recv: "); receiver()->print(out); out->print("]"); |
aoqi@0 | 2050 | } |
aoqi@0 | 2051 | if (result_opr()->is_valid()) { |
aoqi@0 | 2052 | out->print(" [result: "); result_opr()->print(out); out->print("]"); |
aoqi@0 | 2053 | } |
aoqi@0 | 2054 | } |
aoqi@0 | 2055 | |
aoqi@0 | 2056 | // LIR_OpLabel |
aoqi@0 | 2057 | void LIR_OpLabel::print_instr(outputStream* out) const { |
aoqi@0 | 2058 | out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); |
aoqi@0 | 2059 | } |
aoqi@0 | 2060 | |
aoqi@0 | 2061 | // LIR_OpArrayCopy |
aoqi@0 | 2062 | void LIR_OpArrayCopy::print_instr(outputStream* out) const { |
aoqi@0 | 2063 | src()->print(out); out->print(" "); |
aoqi@0 | 2064 | src_pos()->print(out); out->print(" "); |
aoqi@0 | 2065 | dst()->print(out); out->print(" "); |
aoqi@0 | 2066 | dst_pos()->print(out); out->print(" "); |
aoqi@0 | 2067 | length()->print(out); out->print(" "); |
aoqi@0 | 2068 | tmp()->print(out); out->print(" "); |
aoqi@0 | 2069 | } |
aoqi@0 | 2070 | |
aoqi@0 | 2071 | // LIR_OpUpdateCRC32 |
aoqi@0 | 2072 | void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { |
aoqi@0 | 2073 | crc()->print(out); out->print(" "); |
aoqi@0 | 2074 | val()->print(out); out->print(" "); |
aoqi@0 | 2075 | result_opr()->print(out); out->print(" "); |
aoqi@0 | 2076 | } |
aoqi@0 | 2077 | |
aoqi@0 | 2078 | // LIR_OpCompareAndSwap |
aoqi@0 | 2079 | void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { |
aoqi@0 | 2080 | addr()->print(out); out->print(" "); |
aoqi@0 | 2081 | cmp_value()->print(out); out->print(" "); |
aoqi@0 | 2082 | new_value()->print(out); out->print(" "); |
aoqi@0 | 2083 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2084 | tmp2()->print(out); out->print(" "); |
aoqi@0 | 2085 | |
aoqi@0 | 2086 | } |
aoqi@0 | 2087 | |
aoqi@0 | 2088 | // LIR_Op0 |
aoqi@0 | 2089 | void LIR_Op0::print_instr(outputStream* out) const { |
aoqi@0 | 2090 | result_opr()->print(out); |
aoqi@0 | 2091 | } |
aoqi@0 | 2092 | |
aoqi@0 | 2093 | // LIR_Op1 |
aoqi@0 | 2094 | const char * LIR_Op1::name() const { |
aoqi@0 | 2095 | if (code() == lir_move) { |
aoqi@0 | 2096 | switch (move_kind()) { |
aoqi@0 | 2097 | case lir_move_normal: |
aoqi@0 | 2098 | return "move"; |
aoqi@0 | 2099 | case lir_move_unaligned: |
aoqi@0 | 2100 | return "unaligned move"; |
aoqi@0 | 2101 | case lir_move_volatile: |
aoqi@0 | 2102 | return "volatile_move"; |
aoqi@0 | 2103 | case lir_move_wide: |
aoqi@0 | 2104 | return "wide_move"; |
aoqi@0 | 2105 | default: |
aoqi@0 | 2106 | ShouldNotReachHere(); |
aoqi@0 | 2107 | return "illegal_op"; |
aoqi@0 | 2108 | } |
aoqi@0 | 2109 | } else { |
aoqi@0 | 2110 | return LIR_Op::name(); |
aoqi@0 | 2111 | } |
aoqi@0 | 2112 | } |
aoqi@0 | 2113 | |
aoqi@0 | 2114 | |
aoqi@0 | 2115 | void LIR_Op1::print_instr(outputStream* out) const { |
aoqi@0 | 2116 | _opr->print(out); out->print(" "); |
aoqi@0 | 2117 | result_opr()->print(out); out->print(" "); |
aoqi@0 | 2118 | print_patch_code(out, patch_code()); |
aoqi@0 | 2119 | } |
aoqi@0 | 2120 | |
aoqi@0 | 2121 | |
aoqi@0 | 2122 | // LIR_Op1 |
aoqi@0 | 2123 | void LIR_OpRTCall::print_instr(outputStream* out) const { |
aoqi@0 | 2124 | intx a = (intx)addr(); |
aoqi@0 | 2125 | out->print("%s", Runtime1::name_for_address(addr())); |
aoqi@0 | 2126 | out->print(" "); |
aoqi@0 | 2127 | tmp()->print(out); |
aoqi@0 | 2128 | } |
aoqi@0 | 2129 | |
aoqi@0 | 2130 | void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { |
aoqi@0 | 2131 | switch(code) { |
aoqi@0 | 2132 | case lir_patch_none: break; |
aoqi@0 | 2133 | case lir_patch_low: out->print("[patch_low]"); break; |
aoqi@0 | 2134 | case lir_patch_high: out->print("[patch_high]"); break; |
aoqi@0 | 2135 | case lir_patch_normal: out->print("[patch_normal]"); break; |
aoqi@0 | 2136 | default: ShouldNotReachHere(); |
aoqi@0 | 2137 | } |
aoqi@0 | 2138 | } |
aoqi@0 | 2139 | |
aoqi@0 | 2140 | // LIR_OpBranch |
aoqi@0 | 2141 | void LIR_OpBranch::print_instr(outputStream* out) const { |
aoqi@0 | 2142 | print_condition(out, cond()); out->print(" "); |
aoqi@1 | 2143 | #ifdef MIPS64 |
aoqi@1 | 2144 | in_opr1()->print(out); out->print(" "); |
aoqi@1 | 2145 | in_opr2()->print(out); out->print(" "); |
aoqi@1 | 2146 | #endif |
aoqi@0 | 2147 | if (block() != NULL) { |
aoqi@0 | 2148 | out->print("[B%d] ", block()->block_id()); |
aoqi@0 | 2149 | } else if (stub() != NULL) { |
aoqi@0 | 2150 | out->print("["); |
aoqi@0 | 2151 | stub()->print_name(out); |
aoqi@0 | 2152 | out->print(": " INTPTR_FORMAT "]", p2i(stub())); |
aoqi@0 | 2153 | if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); |
aoqi@0 | 2154 | } else { |
aoqi@0 | 2155 | out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); |
aoqi@0 | 2156 | } |
aoqi@0 | 2157 | if (ublock() != NULL) { |
aoqi@0 | 2158 | out->print("unordered: [B%d] ", ublock()->block_id()); |
aoqi@0 | 2159 | } |
aoqi@0 | 2160 | } |
aoqi@0 | 2161 | |
aoqi@0 | 2162 | void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { |
aoqi@0 | 2163 | switch(cond) { |
aoqi@0 | 2164 | case lir_cond_equal: out->print("[EQ]"); break; |
aoqi@0 | 2165 | case lir_cond_notEqual: out->print("[NE]"); break; |
aoqi@0 | 2166 | case lir_cond_less: out->print("[LT]"); break; |
aoqi@0 | 2167 | case lir_cond_lessEqual: out->print("[LE]"); break; |
aoqi@0 | 2168 | case lir_cond_greaterEqual: out->print("[GE]"); break; |
aoqi@0 | 2169 | case lir_cond_greater: out->print("[GT]"); break; |
aoqi@0 | 2170 | case lir_cond_belowEqual: out->print("[BE]"); break; |
aoqi@0 | 2171 | case lir_cond_aboveEqual: out->print("[AE]"); break; |
aoqi@0 | 2172 | case lir_cond_always: out->print("[AL]"); break; |
aoqi@0 | 2173 | default: out->print("[%d]",cond); break; |
aoqi@0 | 2174 | } |
aoqi@0 | 2175 | } |
aoqi@0 | 2176 | |
aoqi@0 | 2177 | // LIR_OpConvert |
aoqi@0 | 2178 | void LIR_OpConvert::print_instr(outputStream* out) const { |
aoqi@0 | 2179 | print_bytecode(out, bytecode()); |
aoqi@0 | 2180 | in_opr()->print(out); out->print(" "); |
aoqi@0 | 2181 | result_opr()->print(out); out->print(" "); |
aoqi@0 | 2182 | #ifdef PPC |
aoqi@0 | 2183 | if(tmp1()->is_valid()) { |
aoqi@0 | 2184 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2185 | tmp2()->print(out); out->print(" "); |
aoqi@0 | 2186 | } |
aoqi@0 | 2187 | #endif |
aoqi@0 | 2188 | } |
aoqi@0 | 2189 | |
aoqi@0 | 2190 | void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { |
aoqi@0 | 2191 | switch(code) { |
aoqi@0 | 2192 | case Bytecodes::_d2f: out->print("[d2f] "); break; |
aoqi@0 | 2193 | case Bytecodes::_d2i: out->print("[d2i] "); break; |
aoqi@0 | 2194 | case Bytecodes::_d2l: out->print("[d2l] "); break; |
aoqi@0 | 2195 | case Bytecodes::_f2d: out->print("[f2d] "); break; |
aoqi@0 | 2196 | case Bytecodes::_f2i: out->print("[f2i] "); break; |
aoqi@0 | 2197 | case Bytecodes::_f2l: out->print("[f2l] "); break; |
aoqi@0 | 2198 | case Bytecodes::_i2b: out->print("[i2b] "); break; |
aoqi@0 | 2199 | case Bytecodes::_i2c: out->print("[i2c] "); break; |
aoqi@0 | 2200 | case Bytecodes::_i2d: out->print("[i2d] "); break; |
aoqi@0 | 2201 | case Bytecodes::_i2f: out->print("[i2f] "); break; |
aoqi@0 | 2202 | case Bytecodes::_i2l: out->print("[i2l] "); break; |
aoqi@0 | 2203 | case Bytecodes::_i2s: out->print("[i2s] "); break; |
aoqi@0 | 2204 | case Bytecodes::_l2i: out->print("[l2i] "); break; |
aoqi@0 | 2205 | case Bytecodes::_l2f: out->print("[l2f] "); break; |
aoqi@0 | 2206 | case Bytecodes::_l2d: out->print("[l2d] "); break; |
aoqi@0 | 2207 | default: |
aoqi@0 | 2208 | out->print("[?%d]",code); |
aoqi@0 | 2209 | break; |
aoqi@0 | 2210 | } |
aoqi@0 | 2211 | } |
aoqi@0 | 2212 | |
aoqi@0 | 2213 | void LIR_OpAllocObj::print_instr(outputStream* out) const { |
aoqi@0 | 2214 | klass()->print(out); out->print(" "); |
aoqi@0 | 2215 | obj()->print(out); out->print(" "); |
aoqi@0 | 2216 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2217 | tmp2()->print(out); out->print(" "); |
aoqi@0 | 2218 | tmp3()->print(out); out->print(" "); |
aoqi@0 | 2219 | tmp4()->print(out); out->print(" "); |
aoqi@1 | 2220 | #ifdef MIPS64 |
aoqi@1 | 2221 | tmp5()->print(out); out->print(" "); |
aoqi@1 | 2222 | tmp6()->print(out); out->print(" "); |
aoqi@1 | 2223 | #endif |
aoqi@0 | 2224 | out->print("[hdr:%d]", header_size()); out->print(" "); |
aoqi@0 | 2225 | out->print("[obj:%d]", object_size()); out->print(" "); |
aoqi@0 | 2226 | out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
aoqi@0 | 2227 | } |
aoqi@0 | 2228 | |
aoqi@0 | 2229 | void LIR_OpRoundFP::print_instr(outputStream* out) const { |
aoqi@0 | 2230 | _opr->print(out); out->print(" "); |
aoqi@0 | 2231 | tmp()->print(out); out->print(" "); |
aoqi@0 | 2232 | result_opr()->print(out); out->print(" "); |
aoqi@0 | 2233 | } |
aoqi@0 | 2234 | |
aoqi@0 | 2235 | // LIR_Op2 |
aoqi@0 | 2236 | void LIR_Op2::print_instr(outputStream* out) const { |
aoqi@1 | 2237 | #ifndef MIPS64 |
aoqi@0 | 2238 | if (code() == lir_cmove) { |
aoqi@0 | 2239 | print_condition(out, condition()); out->print(" "); |
aoqi@0 | 2240 | } |
aoqi@1 | 2241 | #endif |
aoqi@0 | 2242 | in_opr1()->print(out); out->print(" "); |
aoqi@0 | 2243 | in_opr2()->print(out); out->print(" "); |
aoqi@0 | 2244 | if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } |
aoqi@0 | 2245 | if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } |
aoqi@0 | 2246 | if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } |
aoqi@0 | 2247 | if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } |
aoqi@0 | 2248 | if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } |
aoqi@0 | 2249 | result_opr()->print(out); |
aoqi@0 | 2250 | } |
aoqi@0 | 2251 | |
aoqi@0 | 2252 | void LIR_OpAllocArray::print_instr(outputStream* out) const { |
aoqi@0 | 2253 | klass()->print(out); out->print(" "); |
aoqi@0 | 2254 | len()->print(out); out->print(" "); |
aoqi@0 | 2255 | obj()->print(out); out->print(" "); |
aoqi@0 | 2256 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2257 | tmp2()->print(out); out->print(" "); |
aoqi@0 | 2258 | tmp3()->print(out); out->print(" "); |
aoqi@0 | 2259 | tmp4()->print(out); out->print(" "); |
aoqi@1 | 2260 | #ifdef MIPS64 |
aoqi@1 | 2261 | tmp5()->print(out); out->print(" "); |
aoqi@1 | 2262 | #endif |
aoqi@0 | 2263 | out->print("[type:0x%x]", type()); out->print(" "); |
aoqi@0 | 2264 | out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
aoqi@0 | 2265 | } |
aoqi@0 | 2266 | |
aoqi@0 | 2267 | |
aoqi@0 | 2268 | void LIR_OpTypeCheck::print_instr(outputStream* out) const { |
aoqi@0 | 2269 | object()->print(out); out->print(" "); |
aoqi@0 | 2270 | if (code() == lir_store_check) { |
aoqi@0 | 2271 | array()->print(out); out->print(" "); |
aoqi@0 | 2272 | } |
aoqi@0 | 2273 | if (code() != lir_store_check) { |
aoqi@0 | 2274 | klass()->print_name_on(out); out->print(" "); |
aoqi@0 | 2275 | if (fast_check()) out->print("fast_check "); |
aoqi@0 | 2276 | } |
aoqi@0 | 2277 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2278 | tmp2()->print(out); out->print(" "); |
aoqi@0 | 2279 | tmp3()->print(out); out->print(" "); |
aoqi@0 | 2280 | result_opr()->print(out); out->print(" "); |
aoqi@0 | 2281 | if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); |
aoqi@0 | 2282 | } |
aoqi@0 | 2283 | |
aoqi@0 | 2284 | |
aoqi@0 | 2285 | // LIR_Op3 |
aoqi@0 | 2286 | void LIR_Op3::print_instr(outputStream* out) const { |
aoqi@0 | 2287 | in_opr1()->print(out); out->print(" "); |
aoqi@0 | 2288 | in_opr2()->print(out); out->print(" "); |
aoqi@0 | 2289 | in_opr3()->print(out); out->print(" "); |
aoqi@0 | 2290 | result_opr()->print(out); |
aoqi@0 | 2291 | } |
aoqi@0 | 2292 | |
aoqi@0 | 2293 | |
aoqi@0 | 2294 | void LIR_OpLock::print_instr(outputStream* out) const { |
aoqi@0 | 2295 | hdr_opr()->print(out); out->print(" "); |
aoqi@0 | 2296 | obj_opr()->print(out); out->print(" "); |
aoqi@0 | 2297 | lock_opr()->print(out); out->print(" "); |
aoqi@0 | 2298 | if (_scratch->is_valid()) { |
aoqi@0 | 2299 | _scratch->print(out); out->print(" "); |
aoqi@0 | 2300 | } |
aoqi@0 | 2301 | out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
aoqi@0 | 2302 | } |
aoqi@0 | 2303 | |
aoqi@0 | 2304 | #ifdef ASSERT |
aoqi@0 | 2305 | void LIR_OpAssert::print_instr(outputStream* out) const { |
aoqi@1 | 2306 | tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! "); |
aoqi@1 | 2307 | Unimplemented(); |
aoqi@1 | 2308 | /* |
aoqi@0 | 2309 | print_condition(out, condition()); out->print(" "); |
aoqi@0 | 2310 | in_opr1()->print(out); out->print(" "); |
aoqi@0 | 2311 | in_opr2()->print(out); out->print(", \""); |
aoqi@0 | 2312 | out->print("%s", msg()); out->print("\""); |
aoqi@1 | 2313 | */ |
aoqi@0 | 2314 | } |
aoqi@0 | 2315 | #endif |
aoqi@0 | 2316 | |
aoqi@0 | 2317 | |
aoqi@0 | 2318 | void LIR_OpDelay::print_instr(outputStream* out) const { |
aoqi@0 | 2319 | _op->print_on(out); |
aoqi@0 | 2320 | } |
aoqi@0 | 2321 | |
aoqi@0 | 2322 | |
aoqi@0 | 2323 | // LIR_OpProfileCall |
aoqi@0 | 2324 | void LIR_OpProfileCall::print_instr(outputStream* out) const { |
aoqi@0 | 2325 | profiled_method()->name()->print_symbol_on(out); |
aoqi@0 | 2326 | out->print("."); |
aoqi@0 | 2327 | profiled_method()->holder()->name()->print_symbol_on(out); |
aoqi@0 | 2328 | out->print(" @ %d ", profiled_bci()); |
aoqi@0 | 2329 | mdo()->print(out); out->print(" "); |
aoqi@0 | 2330 | recv()->print(out); out->print(" "); |
aoqi@0 | 2331 | tmp1()->print(out); out->print(" "); |
aoqi@0 | 2332 | } |
aoqi@0 | 2333 | |
aoqi@0 | 2334 | // LIR_OpProfileType |
aoqi@0 | 2335 | void LIR_OpProfileType::print_instr(outputStream* out) const { |
aoqi@0 | 2336 | out->print("exact = "); exact_klass()->print_name_on(out); |
aoqi@0 | 2337 | out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass()); |
aoqi@0 | 2338 | mdp()->print(out); out->print(" "); |
aoqi@0 | 2339 | obj()->print(out); out->print(" "); |
aoqi@0 | 2340 | tmp()->print(out); out->print(" "); |
aoqi@0 | 2341 | } |
aoqi@0 | 2342 | |
aoqi@0 | 2343 | #endif // PRODUCT |
aoqi@0 | 2344 | |
aoqi@0 | 2345 | // Implementation of LIR_InsertionBuffer |
aoqi@0 | 2346 | |
aoqi@0 | 2347 | void LIR_InsertionBuffer::append(int index, LIR_Op* op) { |
aoqi@0 | 2348 | assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); |
aoqi@0 | 2349 | |
aoqi@0 | 2350 | int i = number_of_insertion_points() - 1; |
aoqi@0 | 2351 | if (i < 0 || index_at(i) < index) { |
aoqi@0 | 2352 | append_new(index, 1); |
aoqi@0 | 2353 | } else { |
aoqi@0 | 2354 | assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); |
aoqi@0 | 2355 | assert(count_at(i) > 0, "check"); |
aoqi@0 | 2356 | set_count_at(i, count_at(i) + 1); |
aoqi@0 | 2357 | } |
aoqi@0 | 2358 | _ops.push(op); |
aoqi@0 | 2359 | |
aoqi@0 | 2360 | DEBUG_ONLY(verify()); |
aoqi@0 | 2361 | } |
aoqi@0 | 2362 | |
aoqi@0 | 2363 | #ifdef ASSERT |
aoqi@0 | 2364 | void LIR_InsertionBuffer::verify() { |
aoqi@0 | 2365 | int sum = 0; |
aoqi@0 | 2366 | int prev_idx = -1; |
aoqi@0 | 2367 | |
aoqi@0 | 2368 | for (int i = 0; i < number_of_insertion_points(); i++) { |
aoqi@0 | 2369 | assert(prev_idx < index_at(i), "index must be ordered ascending"); |
aoqi@0 | 2370 | sum += count_at(i); |
aoqi@0 | 2371 | } |
aoqi@0 | 2372 | assert(sum == number_of_ops(), "wrong total sum"); |
aoqi@0 | 2373 | } |
aoqi@0 | 2374 | #endif |