1.1 --- a/src/share/vm/c1/c1_LIR.cpp Thu Aug 06 00:08:57 2015 -0700
1.2 +++ b/src/share/vm/c1/c1_LIR.cpp Tue Oct 17 12:58:25 2017 +0800
1.3 @@ -22,6 +22,12 @@
1.4 *
1.5 */
1.6
1.7 +/*
1.8 + * This file has been modified by Loongson Technology in 2015. These
1.9 + * modifications are Copyright (c) 2015 Loongson Technology, and are made
1.10 + * available on the same license terms set forth above.
1.11 + */
1.12 +
1.13 #include "precompiled.hpp"
1.14 #include "c1/c1_InstructionPrinter.hpp"
1.15 #include "c1/c1_LIR.hpp"
1.16 @@ -66,6 +72,25 @@
1.17 }
1.18
1.19 #endif
1.20 +#ifdef MIPS64
1.21 +
1.22 +FloatRegister LIR_OprDesc::as_float_reg() const {
1.23 + return FrameMap::nr2floatreg(fpu_regnr());
1.24 +}
1.25 +
1.26 +FloatRegister LIR_OprDesc::as_double_reg() const {
1.27 + return FrameMap::nr2floatreg(fpu_regnrHi());
1.28 +}
1.29 +
1.30 +FloatRegister LIR_OprDesc::as_fpu_lo() const {
1.31 + return FrameMap::nr2floatreg(fpu_regnrLo());
1.32 +}
1.33 +
1.34 +FloatRegister LIR_OprDesc::as_fpu_hi() const {
1.35 + return FrameMap::nr2floatreg(fpu_regnrHi());
1.36 +}
1.37 +
1.38 +#endif
1.39
1.40 #ifdef ARM
1.41
1.42 @@ -150,8 +175,10 @@
1.43 #ifdef _LP64
1.44 assert(base()->is_cpu_register(), "wrong base operand");
1.45 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
1.46 +#ifndef MIPS64
1.47 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
1.48 "wrong type for addresses");
1.49 +#endif
1.50 #else
1.51 assert(base()->is_single_cpu(), "wrong base operand");
1.52 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
1.53 @@ -298,6 +325,7 @@
1.54 }
1.55
1.56
1.57 +#ifndef MIPS64
1.58 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
1.59 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
1.60 , _cond(cond)
1.61 @@ -329,6 +357,43 @@
1.62 {
1.63 }
1.64
1.65 +#else
1.66 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.67 + BlockBegin* block):
1.68 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.69 + _cond(cond),
1.70 + _type(type),
1.71 + _label(block->label()),
1.72 + _block(block),
1.73 + _ublock(NULL),
1.74 + _stub(NULL) {
1.75 +}
1.76 +
1.77 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.78 + CodeStub* stub):
1.79 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.80 + _cond(cond),
1.81 + _type(type),
1.82 + _label(stub->entry()),
1.83 + _block(NULL),
1.84 + _ublock(NULL),
1.85 + _stub(stub) {
1.86 +}
1.87 +
1.88 +
1.89 +LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.90 + BlockBegin *block, BlockBegin *ublock):
1.91 + LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
1.92 + _cond(cond),
1.93 + _type(type),
1.94 + _label(block->label()),
1.95 + _block(block),
1.96 + _ublock(ublock),
1.97 + _stub(NULL) {
1.98 +}
1.99 +
1.100 +#endif
1.101 +
1.102 void LIR_OpBranch::change_block(BlockBegin* b) {
1.103 assert(_block != NULL, "must have old block");
1.104 assert(_block->label() == label(), "must be equal");
1.105 @@ -572,6 +637,15 @@
1.106 assert(op->as_OpBranch() != NULL, "must be");
1.107 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
1.108
1.109 +#ifdef MIPS64
1.110 + if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
1.111 + if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
1.112 + if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
1.113 + if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
1.114 + if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
1.115 + if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
1.116 + if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
1.117 +#endif
1.118 if (opBranch->_info != NULL) do_info(opBranch->_info);
1.119 assert(opBranch->_result->is_illegal(), "not used");
1.120 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
1.121 @@ -594,6 +668,10 @@
1.122 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
1.123 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
1.124 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
1.125 +#ifdef MIPS64
1.126 + if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
1.127 + if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
1.128 +#endif
1.129 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
1.130 do_stub(opAllocObj->_stub);
1.131 break;
1.132 @@ -615,7 +693,11 @@
1.133
1.134
1.135 // LIR_Op2
1.136 +#ifdef MIPS64
1.137 + case lir_null_check_for_branch:
1.138 +#else
1.139 case lir_cmp:
1.140 +#endif
1.141 case lir_cmp_l2i:
1.142 case lir_ucmp_fd2i:
1.143 case lir_cmp_fd2i:
1.144 @@ -783,6 +865,9 @@
1.145 }
1.146
1.147 // LIR_Op3
1.148 +#ifdef MIPS64
1.149 + case lir_frem:
1.150 +#endif
1.151 case lir_idiv:
1.152 case lir_irem: {
1.153 assert(op->as_Op3() != NULL, "must be");
1.154 @@ -867,7 +952,9 @@
1.155 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
1.156 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
1.157 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
1.158 +#ifndef MIPS64
1.159 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
1.160 +#endif
1.161 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1.162
1.163 // the implementation of arraycopy always has a call into the runtime
1.164 @@ -982,6 +1069,9 @@
1.165 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1.166 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1.167 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1.168 +#ifdef MIPS64
1.169 + if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1.170 +#endif
1.171 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1.172 do_stub(opAllocArray->_stub);
1.173 break;
1.174 @@ -1252,6 +1342,7 @@
1.175 }
1.176
1.177 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.178 +#ifndef MIPS64
1.179 append(new LIR_Op1(
1.180 lir_move,
1.181 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1.182 @@ -1259,6 +1350,16 @@
1.183 type,
1.184 patch_code,
1.185 info, lir_move_volatile));
1.186 +#else
1.187 + add(base, offset, base);
1.188 + append(new LIR_Op1(
1.189 + lir_move,
1.190 + LIR_OprFact::address(new LIR_Address(base, 0, type)),
1.191 + dst,
1.192 + type,
1.193 + patch_code,
1.194 + info, lir_move_volatile));
1.195 +#endif
1.196 }
1.197
1.198
1.199 @@ -1314,6 +1415,7 @@
1.200 }
1.201
1.202 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1.203 +#ifndef MIPS64
1.204 append(new LIR_Op1(
1.205 lir_move,
1.206 src,
1.207 @@ -1321,8 +1423,31 @@
1.208 type,
1.209 patch_code,
1.210 info, lir_move_volatile));
1.211 +#else
1.212 + add(base, offset, base);
1.213 + append(new LIR_Op1(
1.214 + lir_move,
1.215 + src,
1.216 + LIR_OprFact::address(new LIR_Address(base, 0, type)),
1.217 + type,
1.218 + patch_code,
1.219 + info, lir_move_volatile));
1.220 +
1.221 +#endif
1.222 +
1.223 }
1.224
1.225 +#ifdef MIPS64
1.226 +void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1.227 + append(new LIR_Op3(
1.228 + lir_frem,
1.229 + left,
1.230 + right,
1.231 + tmp,
1.232 + res,
1.233 + info));
1.234 +}
1.235 +#endif
1.236
1.237 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1.238 append(new LIR_Op3(
1.239 @@ -1368,6 +1493,7 @@
1.240 }
1.241
1.242
1.243 +#ifndef MIPS64
1.244 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1.245 append(new LIR_Op2(
1.246 lir_cmp,
1.247 @@ -1414,6 +1540,39 @@
1.248 type,
1.249 stub));
1.250 }
1.251 +#else
1.252 + void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1.253 + int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1.254 + append(new LIR_OpAllocObj(
1.255 + klass,
1.256 + dst,
1.257 + t1,
1.258 + t2,
1.259 + t3,
1.260 + t4,
1.261 + t5,
1.262 + t6,
1.263 + header_size,
1.264 + object_size,
1.265 + init_check,
1.266 + stub));
1.267 +}
1.268 +void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1.269 + BasicType type, LIR_Opr klass, CodeStub* stub) {
1.270 + append(new LIR_OpAllocArray(
1.271 + klass,
1.272 + len,
1.273 + dst,
1.274 + t1,
1.275 + t2,
1.276 + t3,
1.277 + t4,
1.278 + t5,
1.279 + type,
1.280 + stub));
1.281 +}
1.282 +
1.283 +#endif
1.284
1.285 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1.286 append(new LIR_Op2(
1.287 @@ -1504,7 +1663,6 @@
1.288 append(c);
1.289 }
1.290
1.291 -
1.292 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1.293 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1.294 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1.295 @@ -1516,7 +1674,7 @@
1.296 append(c);
1.297 }
1.298
1.299 -
1.300 +#ifndef MIPS64
1.301 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.302 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.303 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1.304 @@ -1531,6 +1689,43 @@
1.305 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.306 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1.307 }
1.308 +#else
1.309 +void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.310 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.311 + // // implying successful swap of new_value into addr
1.312 + append(new LIR_OpCompareAndSwap(lir_cas_long,
1.313 + addr,
1.314 + cmp_value,
1.315 + new_value,
1.316 + t1,
1.317 + t2,
1.318 + result));
1.319 +}
1.320 +
1.321 +void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.322 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.323 + // // implying successful swap of new_value into addr
1.324 + append(new LIR_OpCompareAndSwap(lir_cas_obj,
1.325 + addr,
1.326 + cmp_value,
1.327 + new_value,
1.328 + t1,
1.329 + t2,
1.330 + result));
1.331 +}
1.332 +
1.333 +void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1.334 + // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1.335 + // // implying successful swap of new_value into addr
1.336 + append(new LIR_OpCompareAndSwap(lir_cas_int,
1.337 + addr,
1.338 + cmp_value,
1.339 + new_value,
1.340 + t1,
1.341 + t2,
1.342 + result));
1.343 +}
1.344 +#endif
1.345
1.346
1.347 #ifdef PRODUCT
1.348 @@ -1616,6 +1811,7 @@
1.349 // LIR_Address
1.350 void LIR_Address::print_value_on(outputStream* out) const {
1.351 out->print("Base:"); _base->print(out);
1.352 +#ifndef MIPS64
1.353 if (!_index->is_illegal()) {
1.354 out->print(" Index:"); _index->print(out);
1.355 switch (scale()) {
1.356 @@ -1625,6 +1821,7 @@
1.357 case times_8: out->print(" * 8"); break;
1.358 }
1.359 }
1.360 +#endif
1.361 out->print(" Disp: " INTX_FORMAT, _disp);
1.362 }
1.363
1.364 @@ -1756,7 +1953,11 @@
1.365 case lir_pack64: s = "pack64"; break;
1.366 case lir_unpack64: s = "unpack64"; break;
1.367 // LIR_Op2
1.368 +#ifdef MIPS64
1.369 + case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1.370 +#else
1.371 case lir_cmp: s = "cmp"; break;
1.372 +#endif
1.373 case lir_cmp_l2i: s = "cmp_l2i"; break;
1.374 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1.375 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1.376 @@ -1787,6 +1988,9 @@
1.377 case lir_xadd: s = "xadd"; break;
1.378 case lir_xchg: s = "xchg"; break;
1.379 // LIR_Op3
1.380 +#ifdef MIPS64
1.381 + case lir_frem: s = "frem"; break;
1.382 +#endif
1.383 case lir_idiv: s = "idiv"; break;
1.384 case lir_irem: s = "irem"; break;
1.385 // LIR_OpJavaCall
1.386 @@ -1925,6 +2129,10 @@
1.387 // LIR_OpBranch
1.388 void LIR_OpBranch::print_instr(outputStream* out) const {
1.389 print_condition(out, cond()); out->print(" ");
1.390 +#ifdef MIPS64
1.391 + in_opr1()->print(out); out->print(" ");
1.392 + in_opr2()->print(out); out->print(" ");
1.393 +#endif
1.394 if (block() != NULL) {
1.395 out->print("[B%d] ", block()->block_id());
1.396 } else if (stub() != NULL) {
1.397 @@ -1998,6 +2206,10 @@
1.398 tmp2()->print(out); out->print(" ");
1.399 tmp3()->print(out); out->print(" ");
1.400 tmp4()->print(out); out->print(" ");
1.401 +#ifdef MIPS64
1.402 + tmp5()->print(out); out->print(" ");
1.403 + tmp6()->print(out); out->print(" ");
1.404 +#endif
1.405 out->print("[hdr:%d]", header_size()); out->print(" ");
1.406 out->print("[obj:%d]", object_size()); out->print(" ");
1.407 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1.408 @@ -2011,9 +2223,11 @@
1.409
1.410 // LIR_Op2
1.411 void LIR_Op2::print_instr(outputStream* out) const {
1.412 +#ifndef MIPS64
1.413 if (code() == lir_cmove) {
1.414 print_condition(out, condition()); out->print(" ");
1.415 }
1.416 +#endif
1.417 in_opr1()->print(out); out->print(" ");
1.418 in_opr2()->print(out); out->print(" ");
1.419 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1.420 @@ -2032,6 +2246,9 @@
1.421 tmp2()->print(out); out->print(" ");
1.422 tmp3()->print(out); out->print(" ");
1.423 tmp4()->print(out); out->print(" ");
1.424 +#ifdef MIPS64
1.425 + tmp5()->print(out); out->print(" ");
1.426 +#endif
1.427 out->print("[type:0x%x]", type()); out->print(" ");
1.428 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1.429 }
1.430 @@ -2075,10 +2292,14 @@
1.431
1.432 #ifdef ASSERT
1.433 void LIR_OpAssert::print_instr(outputStream* out) const {
1.434 + tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
1.435 + Unimplemented();
1.436 + /*
1.437 print_condition(out, condition()); out->print(" ");
1.438 in_opr1()->print(out); out->print(" ");
1.439 in_opr2()->print(out); out->print(", \"");
1.440 out->print("%s", msg()); out->print("\"");
1.441 + */
1.442 }
1.443 #endif
1.444
