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src/cpu/mips/vm/c1_LinearScan_mips.hpp@ffcdff41a92f (annotated)
src/cpu/mips/vm/c1_LinearScan_mips.hpp
Thu, 24 May 2018 19:49:50 +0800
- author
- aoqi
- date
- Thu, 24 May 2018 19:49:50 +0800
- changeset 8865
- ffcdff41a92f
- parent 6880
- 52ea28d233d2
- child 9126
- bc5b8e3dcb6b
- permissions
- -rw-r--r--
some C1 fix
Contributed-by: chenhaoxuan, zhaixiang, aoqi
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@8865 | 26 | #ifndef CPU_MIPS_VM_C1_LINEARSCAN_MIPS_HPP |
| aoqi@8865 | 27 | #define CPU_MIPS_VM_C1_LINEARSCAN_MIPS_HPP |
| aoqi@8865 | 28 | |
| aoqi@1 | 29 | inline bool LinearScan::is_processed_reg_num(int reg_num) { |
| aoqi@6880 | 30 | return reg_num < 26 || reg_num > 30; |
| aoqi@1 | 31 | } |
| aoqi@1 | 32 | |
| aoqi@1 | 33 | inline int LinearScan::num_physical_regs(BasicType type) { |
| aoqi@6880 | 34 | if (type == T_LONG || type== T_DOUBLE || type == T_FLOAT) { |
| aoqi@6880 | 35 | return 2; |
| aoqi@6880 | 36 | } |
| aoqi@6880 | 37 | return 1; |
| aoqi@1 | 38 | } |
| aoqi@1 | 39 | |
| aoqi@1 | 40 | |
| aoqi@1 | 41 | inline bool LinearScan::requires_adjacent_regs(BasicType type) { |
| aoqi@6880 | 42 | return type == T_FLOAT || type == T_DOUBLE; |
| aoqi@1 | 43 | } |
| aoqi@1 | 44 | |
| aoqi@1 | 45 | inline bool LinearScan::is_caller_save(int assigned_reg) { |
| aoqi@6880 | 46 | assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); |
| aoqi@6880 | 47 | // return true; // no callee-saved registers on Intel |
| aoqi@6880 | 48 | //FIXME, here, MIPS indeed got callee-saved registers |
| aoqi@6880 | 49 | return true; |
| aoqi@1 | 50 | } |
| aoqi@1 | 51 | |
| aoqi@1 | 52 | |
| aoqi@1 | 53 | inline void LinearScan::pd_add_temps(LIR_Op* op) { |
| aoqi@1 | 54 | } |
| aoqi@1 | 55 | |
| aoqi@1 | 56 | |
| aoqi@1 | 57 | // Implementation of LinearScanWalker |
| aoqi@1 | 58 | |
| aoqi@1 | 59 | inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { |
| aoqi@6880 | 60 | if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) { |
| aoqi@6880 | 61 | assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); |
| aoqi@6880 | 62 | _first_reg = pd_first_callee_saved_reg; |
| aoqi@6880 | 63 | _last_reg = pd_last_callee_saved_reg; |
| aoqi@6880 | 64 | return true; |
| aoqi@8865 | 65 | } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || cur->type() == T_METADATA) { |
| aoqi@1 | 66 | #ifdef _LP64 |
| aoqi@6880 | 67 | _first_reg = 12; /* From T0 */ |
| aoqi@1 | 68 | #else |
| aoqi@6880 | 69 | _first_reg = 8; /* From T0 */ |
| aoqi@1 | 70 | #endif |
| aoqi@6880 | 71 | _last_reg = pd_last_allocatable_cpu_reg; |
| aoqi@6880 | 72 | return true; |
| aoqi@6880 | 73 | } |
| aoqi@6880 | 74 | return false; |
| aoqi@1 | 75 | } |
| aoqi@8865 | 76 | |
| aoqi@8865 | 77 | #endif // CPU_MIPS_VM_C1_LINEARSCAN_MIPS_HPP |
