Thu, 24 May 2018 19:49:50 +0800
some C1 fix
Contributed-by: chenhaoxuan, zhaixiang, aoqi
aoqi@1 | 1 | /* |
aoqi@1 | 2 | * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@1 | 5 | * |
aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@1 | 8 | * published by the Free Software Foundation. |
aoqi@1 | 9 | * |
aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@1 | 14 | * accompanied this code). |
aoqi@1 | 15 | * |
aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@1 | 19 | * |
aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
aoqi@1 | 22 | * questions. |
aoqi@1 | 23 | * |
aoqi@1 | 24 | */ |
aoqi@1 | 25 | |
aoqi@1 | 26 | #include "precompiled.hpp" |
aoqi@1 | 27 | #include "c1/c1_FrameMap.hpp" |
aoqi@1 | 28 | #include "c1/c1_LIR.hpp" |
aoqi@1 | 29 | #include "runtime/sharedRuntime.hpp" |
aoqi@1 | 30 | #include "vmreg_mips.inline.hpp" |
aoqi@1 | 31 | |
aoqi@1 | 32 | const int FrameMap::pd_c_runtime_reserved_arg_size = 0; |
aoqi@1 | 33 | |
aoqi@1 | 34 | FloatRegister FrameMap::_fpu_regs[32]; |
aoqi@1 | 35 | LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) { |
aoqi@6880 | 36 | LIR_Opr opr = LIR_OprFact::illegalOpr; |
aoqi@6880 | 37 | VMReg r_1 = reg->first(); |
aoqi@6880 | 38 | VMReg r_2 = reg->second(); |
aoqi@6880 | 39 | if (r_1->is_stack()) { |
aoqi@6880 | 40 | // Convert stack slot to an SP offset |
aoqi@6880 | 41 | // The calling convention does not count the |
aoqi@6880 | 42 | // SharedRuntime::out_preserve_stack_slots() value |
aoqi@6880 | 43 | // so we must add it in here. |
aoqi@6880 | 44 | int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) |
aoqi@6880 | 45 | * VMRegImpl::stack_slot_size; |
aoqi@6880 | 46 | opr = LIR_OprFact::address(new LIR_Address(_sp_opr, st_off, type)); |
aoqi@6880 | 47 | } else if (r_1->is_Register()) { |
aoqi@6880 | 48 | Register reg = r_1->as_Register(); |
aoqi@6880 | 49 | if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
aoqi@6880 | 50 | Register reg2 = r_2->as_Register(); |
aoqi@1 | 51 | #ifdef _LP64 |
aoqi@6880 | 52 | assert(reg2 == reg, "must be same register"); |
aoqi@1 | 53 | #endif |
aoqi@6880 | 54 | opr = as_long_opr(reg, reg2); |
aoqi@6880 | 55 | } else if (type == T_OBJECT || type == T_ARRAY) { |
aoqi@6880 | 56 | opr = as_oop_opr(reg); |
aoqi@6880 | 57 | } else { |
aoqi@6880 | 58 | opr = as_opr(reg); |
aoqi@6880 | 59 | } |
aoqi@6880 | 60 | } else if (r_1->is_FloatRegister()) { |
aoqi@6880 | 61 | assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
aoqi@6880 | 62 | int num = r_1->as_FloatRegister()->encoding(); |
aoqi@6880 | 63 | if (type == T_FLOAT) { |
aoqi@6880 | 64 | opr = LIR_OprFact::single_fpu(num); |
aoqi@6880 | 65 | } else { |
aoqi@6880 | 66 | opr = LIR_OprFact::double_fpu(num); |
aoqi@6880 | 67 | } |
aoqi@6880 | 68 | } else { |
aoqi@6880 | 69 | ShouldNotReachHere(); |
aoqi@6880 | 70 | } |
aoqi@6880 | 71 | return opr; |
aoqi@1 | 72 | } |
aoqi@1 | 73 | |
aoqi@1 | 74 | // some useful constant RInfo's: |
aoqi@1 | 75 | LIR_Opr FrameMap::_zero_opr; |
aoqi@1 | 76 | LIR_Opr FrameMap::_k0_opr; |
aoqi@1 | 77 | LIR_Opr FrameMap::_k1_opr; |
aoqi@1 | 78 | LIR_Opr FrameMap::_at_opr; |
aoqi@1 | 79 | LIR_Opr FrameMap::_v0_opr; |
aoqi@1 | 80 | LIR_Opr FrameMap::_v1_opr; |
aoqi@1 | 81 | LIR_Opr FrameMap::_a0_opr; |
aoqi@1 | 82 | LIR_Opr FrameMap::_a1_opr; |
aoqi@1 | 83 | LIR_Opr FrameMap::_a2_opr; |
aoqi@1 | 84 | LIR_Opr FrameMap::_a3_opr; |
aoqi@1 | 85 | LIR_Opr FrameMap::_t0_opr; |
aoqi@1 | 86 | LIR_Opr FrameMap::_t1_opr; |
aoqi@1 | 87 | LIR_Opr FrameMap::_t2_opr; |
aoqi@1 | 88 | LIR_Opr FrameMap::_t3_opr; |
aoqi@1 | 89 | #ifndef _LP64 |
aoqi@1 | 90 | LIR_Opr FrameMap::_t4_opr; |
aoqi@1 | 91 | LIR_Opr FrameMap::_t5_opr; |
aoqi@1 | 92 | LIR_Opr FrameMap::_t6_opr; |
aoqi@1 | 93 | LIR_Opr FrameMap::_t7_opr; |
aoqi@1 | 94 | #else |
aoqi@1 | 95 | LIR_Opr FrameMap::_a4_opr; |
aoqi@1 | 96 | LIR_Opr FrameMap::_a5_opr; |
aoqi@1 | 97 | LIR_Opr FrameMap::_a6_opr; |
aoqi@1 | 98 | LIR_Opr FrameMap::_a7_opr; |
aoqi@1 | 99 | #endif |
aoqi@1 | 100 | LIR_Opr FrameMap::_t8_opr; |
aoqi@1 | 101 | LIR_Opr FrameMap::_t9_opr; |
aoqi@1 | 102 | LIR_Opr FrameMap::_s0_opr; |
aoqi@1 | 103 | LIR_Opr FrameMap::_s1_opr; |
aoqi@1 | 104 | LIR_Opr FrameMap::_s2_opr; |
aoqi@1 | 105 | LIR_Opr FrameMap::_s3_opr; |
aoqi@1 | 106 | LIR_Opr FrameMap::_s4_opr; |
aoqi@1 | 107 | LIR_Opr FrameMap::_s5_opr; |
aoqi@1 | 108 | LIR_Opr FrameMap::_s6_opr; |
aoqi@1 | 109 | LIR_Opr FrameMap::_s7_opr; |
aoqi@1 | 110 | LIR_Opr FrameMap::_gp_opr; |
aoqi@1 | 111 | LIR_Opr FrameMap::_fp_opr; |
aoqi@1 | 112 | LIR_Opr FrameMap::_sp_opr; |
aoqi@1 | 113 | LIR_Opr FrameMap::_ra_opr; |
aoqi@1 | 114 | |
aoqi@1 | 115 | |
aoqi@6880 | 116 | |
aoqi@1 | 117 | LIR_Opr FrameMap::_a0_a1_opr; |
aoqi@1 | 118 | LIR_Opr FrameMap::_a2_a3_opr; |
aoqi@1 | 119 | LIR_Opr FrameMap::_v0_v1_opr; |
aoqi@1 | 120 | |
aoqi@1 | 121 | |
aoqi@1 | 122 | LIR_Opr FrameMap::_f0_opr; |
aoqi@1 | 123 | LIR_Opr FrameMap::_f12_opr; |
aoqi@1 | 124 | LIR_Opr FrameMap::_f14_opr; |
aoqi@1 | 125 | LIR_Opr FrameMap::_d0_opr; |
aoqi@1 | 126 | LIR_Opr FrameMap::_d12_opr; |
aoqi@1 | 127 | LIR_Opr FrameMap::_d14_opr; |
aoqi@1 | 128 | |
aoqi@1 | 129 | |
aoqi@1 | 130 | LIR_Opr FrameMap::receiver_opr; |
aoqi@1 | 131 | |
aoqi@1 | 132 | //caller saved register |
aoqi@1 | 133 | LIR_Opr FrameMap::_v0_oop_opr; |
aoqi@1 | 134 | LIR_Opr FrameMap::_v1_oop_opr; |
aoqi@1 | 135 | LIR_Opr FrameMap::_a0_oop_opr; |
aoqi@1 | 136 | LIR_Opr FrameMap::_a1_oop_opr; |
aoqi@1 | 137 | LIR_Opr FrameMap::_a2_oop_opr; |
aoqi@1 | 138 | LIR_Opr FrameMap::_a3_oop_opr; |
aoqi@1 | 139 | LIR_Opr FrameMap::_t0_oop_opr; |
aoqi@1 | 140 | LIR_Opr FrameMap::_t1_oop_opr; |
aoqi@1 | 141 | LIR_Opr FrameMap::_t2_oop_opr; |
aoqi@1 | 142 | LIR_Opr FrameMap::_t3_oop_opr; |
aoqi@1 | 143 | #ifndef _LP64 |
aoqi@1 | 144 | LIR_Opr FrameMap::_t4_oop_opr; |
aoqi@1 | 145 | LIR_Opr FrameMap::_t5_oop_opr; |
aoqi@1 | 146 | LIR_Opr FrameMap::_t6_oop_opr; |
aoqi@1 | 147 | LIR_Opr FrameMap::_t7_oop_opr; |
aoqi@1 | 148 | #else |
aoqi@1 | 149 | LIR_Opr FrameMap::_a4_oop_opr; |
aoqi@1 | 150 | LIR_Opr FrameMap::_a5_oop_opr; |
aoqi@1 | 151 | LIR_Opr FrameMap::_a6_oop_opr; |
aoqi@1 | 152 | LIR_Opr FrameMap::_a7_oop_opr; |
aoqi@1 | 153 | #endif |
aoqi@1 | 154 | LIR_Opr FrameMap::_t8_oop_opr; |
aoqi@1 | 155 | LIR_Opr FrameMap::_t9_oop_opr; |
aoqi@1 | 156 | LIR_Opr FrameMap::_s0_oop_opr; |
aoqi@1 | 157 | LIR_Opr FrameMap::_s1_oop_opr; |
aoqi@1 | 158 | LIR_Opr FrameMap::_s2_oop_opr; |
aoqi@1 | 159 | LIR_Opr FrameMap::_s3_oop_opr; |
aoqi@1 | 160 | LIR_Opr FrameMap::_s4_oop_opr; |
aoqi@1 | 161 | LIR_Opr FrameMap::_s5_oop_opr; |
aoqi@1 | 162 | LIR_Opr FrameMap::_s6_oop_opr; |
aoqi@1 | 163 | LIR_Opr FrameMap::_s7_oop_opr; |
aoqi@1 | 164 | |
aoqi@8865 | 165 | //add metadata_opr |
aoqi@8865 | 166 | LIR_Opr FrameMap::_v0_metadata_opr; |
aoqi@8865 | 167 | LIR_Opr FrameMap::_v1_metadata_opr; |
aoqi@8865 | 168 | LIR_Opr FrameMap::_a0_metadata_opr; |
aoqi@8865 | 169 | LIR_Opr FrameMap::_a1_metadata_opr; |
aoqi@8865 | 170 | LIR_Opr FrameMap::_a2_metadata_opr; |
aoqi@8865 | 171 | LIR_Opr FrameMap::_a3_metadata_opr; |
aoqi@8865 | 172 | LIR_Opr FrameMap::_t0_metadata_opr; |
aoqi@8865 | 173 | LIR_Opr FrameMap::_t1_metadata_opr; |
aoqi@8865 | 174 | LIR_Opr FrameMap::_t2_metadata_opr; |
aoqi@8865 | 175 | LIR_Opr FrameMap::_t3_metadata_opr; |
aoqi@8865 | 176 | LIR_Opr FrameMap::_a4_metadata_opr; |
aoqi@8865 | 177 | LIR_Opr FrameMap::_a5_metadata_opr; |
aoqi@8865 | 178 | LIR_Opr FrameMap::_a6_metadata_opr; |
aoqi@8865 | 179 | LIR_Opr FrameMap::_a7_metadata_opr; |
aoqi@8865 | 180 | LIR_Opr FrameMap::_t8_metadata_opr; |
aoqi@8865 | 181 | LIR_Opr FrameMap::_t9_metadata_opr; |
aoqi@8865 | 182 | LIR_Opr FrameMap::_s0_metadata_opr; |
aoqi@8865 | 183 | LIR_Opr FrameMap::_s1_metadata_opr; |
aoqi@8865 | 184 | LIR_Opr FrameMap::_s2_metadata_opr; |
aoqi@8865 | 185 | LIR_Opr FrameMap::_s3_metadata_opr; |
aoqi@8865 | 186 | LIR_Opr FrameMap::_s4_metadata_opr; |
aoqi@8865 | 187 | LIR_Opr FrameMap::_s5_metadata_opr; |
aoqi@8865 | 188 | LIR_Opr FrameMap::_s6_metadata_opr; |
aoqi@8865 | 189 | LIR_Opr FrameMap::_s7_metadata_opr; |
aoqi@1 | 190 | |
aoqi@1 | 191 | LIR_Opr FrameMap::_a0_a1_long_opr; |
aoqi@1 | 192 | LIR_Opr FrameMap::_a2_a3_long_opr; |
aoqi@1 | 193 | LIR_Opr FrameMap::_v0_v1_long_opr; |
aoqi@1 | 194 | LIR_Opr FrameMap::_f0_float_opr; |
aoqi@1 | 195 | LIR_Opr FrameMap::_f12_float_opr; |
aoqi@1 | 196 | LIR_Opr FrameMap::_f14_float_opr; |
aoqi@1 | 197 | LIR_Opr FrameMap::_d0_double_opr; |
aoqi@1 | 198 | LIR_Opr FrameMap::_d12_double_opr; |
aoqi@1 | 199 | LIR_Opr FrameMap::_d14_double_opr; |
aoqi@1 | 200 | |
aoqi@1 | 201 | |
aoqi@1 | 202 | |
aoqi@1 | 203 | |
aoqi@1 | 204 | LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
aoqi@1 | 205 | LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
aoqi@1 | 206 | |
aoqi@1 | 207 | |
aoqi@1 | 208 | //-------------------------------------------------------- |
aoqi@1 | 209 | // FrameMap |
aoqi@1 | 210 | //-------------------------------------------------------- |
aoqi@1 | 211 | FloatRegister FrameMap::nr2floatreg (int rnr) { |
aoqi@6880 | 212 | assert(_init_done, "tables not initialized"); |
aoqi@6880 | 213 | debug_only(fpu_range_check(rnr);) |
aoqi@6880 | 214 | return _fpu_regs[rnr]; |
aoqi@1 | 215 | } |
aoqi@1 | 216 | |
aoqi@1 | 217 | // returns true if reg could be smashed by a callee. |
aoqi@1 | 218 | bool FrameMap::is_caller_save_register (LIR_Opr reg) { |
aoqi@6880 | 219 | if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } |
aoqi@6880 | 220 | if (reg->is_double_cpu()) { |
aoqi@6880 | 221 | return is_caller_save_register(reg->as_register_lo()) || |
aoqi@6880 | 222 | is_caller_save_register(reg->as_register_hi()); |
aoqi@6880 | 223 | } |
aoqi@6880 | 224 | return is_caller_save_register(reg->as_register()); |
aoqi@1 | 225 | } |
aoqi@1 | 226 | |
aoqi@1 | 227 | //FIXME, why always ture? @jerome |
aoqi@1 | 228 | bool FrameMap::is_caller_save_register (Register r) { |
aoqi@6880 | 229 | //return (r>=V0 && r<=T7) || (r==T8) || (r==T9); |
aoqi@6880 | 230 | //return ((r>=V0) && (r<=T7)); |
aoqi@6880 | 231 | return true; |
aoqi@1 | 232 | } |
aoqi@1 | 233 | |
aoqi@1 | 234 | void FrameMap::initialize() { |
aoqi@1 | 235 | if (_init_done) return; |
aoqi@1 | 236 | |
aoqi@1 | 237 | assert(nof_cpu_regs == 32, "wrong number of CPU registers"); |
aoqi@1 | 238 | //init _cpu_regs for RegAlloc |
aoqi@1 | 239 | int i = 0; |
aoqi@1 | 240 | |
aoqi@6880 | 241 | map_register(0,R0); _zero_opr=LIR_OprFact::single_cpu(0); |
aoqi@1 | 242 | map_register(1,AT); |
aoqi@1 | 243 | #ifdef _LP64 |
aoqi@6880 | 244 | _at_opr=LIR_OprFact::double_cpu(1, 1); |
aoqi@1 | 245 | #else |
aoqi@6880 | 246 | _at_opr=LIR_OprFact::single_cpu(1); |
aoqi@1 | 247 | #endif |
aoqi@8865 | 248 | map_register(2,V0); _v0_opr=LIR_OprFact::single_cpu(2); _v0_oop_opr=LIR_OprFact::single_cpu_oop(2); _v0_metadata_opr=LIR_OprFact::single_cpu_metadata(2); |
aoqi@8865 | 249 | map_register(3,V1); _v1_opr=LIR_OprFact::single_cpu(3); _v1_oop_opr=LIR_OprFact::single_cpu_oop(3); _v1_metadata_opr=LIR_OprFact::single_cpu_metadata(3); |
aoqi@8865 | 250 | map_register(4,A0); _a0_opr=LIR_OprFact::single_cpu(4); _a0_oop_opr=LIR_OprFact::single_cpu_oop(4); _a0_metadata_opr=LIR_OprFact::single_cpu_metadata(4); |
aoqi@8865 | 251 | map_register(5,A1); _a1_opr=LIR_OprFact::single_cpu(5); _a1_oop_opr=LIR_OprFact::single_cpu_oop(5); _a1_metadata_opr=LIR_OprFact::single_cpu_metadata(5); |
aoqi@8865 | 252 | map_register(6,A2); _a2_opr=LIR_OprFact::single_cpu(6); _a2_oop_opr=LIR_OprFact::single_cpu_oop(6); _a2_metadata_opr=LIR_OprFact::single_cpu_metadata(6); |
aoqi@8865 | 253 | map_register(7,A3); _a3_opr=LIR_OprFact::single_cpu(7); _a3_oop_opr=LIR_OprFact::single_cpu_oop(7); _a3_metadata_opr=LIR_OprFact::single_cpu_metadata(7); |
aoqi@1 | 254 | #ifndef _LP64 |
aoqi@8865 | 255 | map_register(8,T0); _t0_opr=LIR_OprFact::single_cpu(8); _t0_oop_opr=LIR_OprFact::single_cpu_oop(8); |
aoqi@8865 | 256 | map_register(9,T1); _t1_opr=LIR_OprFact::single_cpu(9); _t1_oop_opr=LIR_OprFact::single_cpu_oop(9); |
aoqi@6880 | 257 | map_register(10,T2); _t2_opr=LIR_OprFact::single_cpu(10); _t2_oop_opr=LIR_OprFact::single_cpu_oop(10); |
aoqi@6880 | 258 | map_register(11,T3); _t3_opr=LIR_OprFact::single_cpu(11); _t3_oop_opr=LIR_OprFact::single_cpu_oop(11); |
aoqi@6880 | 259 | map_register(12,T4); _t4_opr=LIR_OprFact::single_cpu(12); _t4_oop_opr=LIR_OprFact::single_cpu_oop(12); |
aoqi@6880 | 260 | map_register(13,T5); _t5_opr=LIR_OprFact::single_cpu(13); _t5_oop_opr=LIR_OprFact::single_cpu_oop(13); |
aoqi@6880 | 261 | map_register(14,T6); _t6_opr=LIR_OprFact::single_cpu(14); _t6_oop_opr=LIR_OprFact::single_cpu_oop(14); |
aoqi@6880 | 262 | map_register(15,T7); _t7_opr=LIR_OprFact::single_cpu(15); _t7_oop_opr=LIR_OprFact::single_cpu_oop(15); |
aoqi@1 | 263 | #else |
aoqi@8865 | 264 | map_register(8,A4); _a4_opr=LIR_OprFact::single_cpu(8); _a4_oop_opr=LIR_OprFact::single_cpu_oop(8); _a4_metadata_opr=LIR_OprFact::single_cpu_metadata(8); |
aoqi@8865 | 265 | map_register(9,A5); _a5_opr=LIR_OprFact::single_cpu(9); _a5_oop_opr=LIR_OprFact::single_cpu_oop(9); _a5_metadata_opr=LIR_OprFact::single_cpu_metadata(9); |
aoqi@8865 | 266 | map_register(10,A6); _a6_opr=LIR_OprFact::single_cpu(10); _a6_oop_opr=LIR_OprFact::single_cpu_oop(10); _a6_metadata_opr=LIR_OprFact::single_cpu_metadata(10); |
aoqi@8865 | 267 | map_register(11,A7); _a7_opr=LIR_OprFact::single_cpu(11); _a7_oop_opr=LIR_OprFact::single_cpu_oop(11); _a7_metadata_opr=LIR_OprFact::single_cpu_metadata(11); |
aoqi@8865 | 268 | map_register(12,T0); _t0_opr=LIR_OprFact::single_cpu(12); _t0_oop_opr=LIR_OprFact::single_cpu_oop(12); _t0_metadata_opr=LIR_OprFact::single_cpu_metadata(12); |
aoqi@8865 | 269 | map_register(13,T1); _t1_opr=LIR_OprFact::single_cpu(13); _t1_oop_opr=LIR_OprFact::single_cpu_oop(13); _t1_metadata_opr=LIR_OprFact::single_cpu_metadata(13); |
aoqi@8865 | 270 | map_register(14,T2); _t2_opr=LIR_OprFact::single_cpu(14); _t2_oop_opr=LIR_OprFact::single_cpu_oop(14); _t2_metadata_opr=LIR_OprFact::single_cpu_metadata(14); |
aoqi@8865 | 271 | map_register(15,T3); _t3_opr=LIR_OprFact::single_cpu(15); _t3_oop_opr=LIR_OprFact::single_cpu_oop(15); _t3_metadata_opr=LIR_OprFact::single_cpu_metadata(15); |
aoqi@1 | 272 | #endif |
aoqi@8865 | 273 | map_register(16,S0); _s0_opr=LIR_OprFact::single_cpu(16); _s0_oop_opr=LIR_OprFact::single_cpu_oop(16); _s0_metadata_opr=LIR_OprFact::single_cpu_metadata(16); |
aoqi@8865 | 274 | map_register(17,S1); _s1_opr=LIR_OprFact::single_cpu(17); _s1_oop_opr=LIR_OprFact::single_cpu_oop(17); _s1_metadata_opr=LIR_OprFact::single_cpu_metadata(17); |
aoqi@8865 | 275 | map_register(18,S2); _s2_opr=LIR_OprFact::single_cpu(18); _s2_oop_opr=LIR_OprFact::single_cpu_oop(18); _s2_metadata_opr=LIR_OprFact::single_cpu_metadata(18); |
aoqi@8865 | 276 | map_register(19,S3); _s3_opr=LIR_OprFact::single_cpu(19); _s3_oop_opr=LIR_OprFact::single_cpu_oop(19); _s3_metadata_opr=LIR_OprFact::single_cpu_metadata(19); |
aoqi@8865 | 277 | map_register(20,S4); _s4_opr=LIR_OprFact::single_cpu(20); _s4_oop_opr=LIR_OprFact::single_cpu_oop(20); _s4_metadata_opr=LIR_OprFact::single_cpu_metadata(20); |
aoqi@8865 | 278 | map_register(21,S5); _s5_opr=LIR_OprFact::single_cpu(21); _s5_oop_opr=LIR_OprFact::single_cpu_oop(21); _s5_metadata_opr=LIR_OprFact::single_cpu_metadata(21); |
aoqi@8865 | 279 | map_register(22,S6); _s6_opr=LIR_OprFact::single_cpu(22); _s6_oop_opr=LIR_OprFact::single_cpu_oop(22); _s6_metadata_opr=LIR_OprFact::single_cpu_metadata(22); |
aoqi@8865 | 280 | map_register(23,S7); _s7_opr=LIR_OprFact::single_cpu(23); _s7_oop_opr=LIR_OprFact::single_cpu_oop(23); _s7_metadata_opr=LIR_OprFact::single_cpu_metadata(23); |
aoqi@6880 | 281 | map_register(24,T8); _t8_opr=LIR_OprFact::single_cpu(24); |
aoqi@6880 | 282 | map_register(25,T9); _t9_opr=LIR_OprFact::single_cpu(25); |
aoqi@6880 | 283 | map_register(26,K0); _k0_opr=LIR_OprFact::single_cpu(26); |
aoqi@6880 | 284 | map_register(27,K1); _k1_opr=LIR_OprFact::single_cpu(27); |
aoqi@6880 | 285 | map_register(28,GP); _gp_opr=LIR_OprFact::single_cpu(28); |
aoqi@6880 | 286 | map_register(29,SP); |
aoqi@1 | 287 | #ifdef _LP64 |
aoqi@6880 | 288 | _sp_opr=LIR_OprFact::double_cpu(29, 29); |
aoqi@1 | 289 | #else |
aoqi@6880 | 290 | _sp_opr=LIR_OprFact::single_cpu(29); |
aoqi@1 | 291 | #endif |
aoqi@1 | 292 | |
aoqi@6880 | 293 | map_register(30,FP); _fp_opr=LIR_OprFact::single_cpu(30); |
aoqi@6880 | 294 | map_register(31,RA); _ra_opr=LIR_OprFact::single_cpu(31); |
aoqi@1 | 295 | |
aoqi@1 | 296 | _caller_save_cpu_regs[0] = _t0_opr; |
aoqi@1 | 297 | _caller_save_cpu_regs[1] = _t1_opr; |
aoqi@1 | 298 | _caller_save_cpu_regs[2] = _t2_opr; |
aoqi@1 | 299 | _caller_save_cpu_regs[3] = _t3_opr; |
aoqi@1 | 300 | #ifndef _LP64 |
aoqi@1 | 301 | _caller_save_cpu_regs[4] = _t4_opr; |
aoqi@1 | 302 | _caller_save_cpu_regs[5] = _t5_opr; |
aoqi@1 | 303 | _caller_save_cpu_regs[6] = _t6_opr; |
aoqi@1 | 304 | _caller_save_cpu_regs[7] = _t7_opr; |
aoqi@1 | 305 | #else |
aoqi@1 | 306 | _caller_save_cpu_regs[4] = _a4_opr; |
aoqi@1 | 307 | _caller_save_cpu_regs[5] = _a5_opr; |
aoqi@1 | 308 | _caller_save_cpu_regs[6] = _a6_opr; |
aoqi@1 | 309 | _caller_save_cpu_regs[7] = _a7_opr; |
aoqi@1 | 310 | #endif |
aoqi@1 | 311 | _caller_save_cpu_regs[8] = _s0_opr; |
aoqi@1 | 312 | _caller_save_cpu_regs[9] = _s1_opr; |
aoqi@1 | 313 | _caller_save_cpu_regs[10] = _s2_opr; |
aoqi@1 | 314 | _caller_save_cpu_regs[11] = _s3_opr; |
aoqi@1 | 315 | _caller_save_cpu_regs[12] = _s4_opr; |
aoqi@1 | 316 | _caller_save_cpu_regs[13] = _s5_opr; |
aoqi@1 | 317 | _caller_save_cpu_regs[14] = _s6_opr; |
aoqi@1 | 318 | _caller_save_cpu_regs[15] = _s7_opr; |
aoqi@1 | 319 | _caller_save_cpu_regs[16] = _v0_opr; |
aoqi@1 | 320 | _caller_save_cpu_regs[17] = _v1_opr; |
aoqi@1 | 321 | |
aoqi@1 | 322 | |
aoqi@1 | 323 | _caller_save_fpu_regs[0] = LIR_OprFact::single_fpu(0); |
aoqi@1 | 324 | _caller_save_fpu_regs[1] = LIR_OprFact::single_fpu(1); |
aoqi@1 | 325 | _caller_save_fpu_regs[2] = LIR_OprFact::single_fpu(2); |
aoqi@1 | 326 | _caller_save_fpu_regs[3] = LIR_OprFact::single_fpu(3); |
aoqi@1 | 327 | _caller_save_fpu_regs[4] = LIR_OprFact::single_fpu(4); |
aoqi@1 | 328 | _caller_save_fpu_regs[5] = LIR_OprFact::single_fpu(5); |
aoqi@1 | 329 | _caller_save_fpu_regs[6] = LIR_OprFact::single_fpu(6); |
aoqi@1 | 330 | _caller_save_fpu_regs[7] = LIR_OprFact::single_fpu(7); |
aoqi@1 | 331 | _caller_save_fpu_regs[8] = LIR_OprFact::single_fpu(8); |
aoqi@1 | 332 | _caller_save_fpu_regs[9] = LIR_OprFact::single_fpu(9); |
aoqi@1 | 333 | _caller_save_fpu_regs[10] = LIR_OprFact::single_fpu(10); |
aoqi@1 | 334 | _caller_save_fpu_regs[11] = LIR_OprFact::single_fpu(11); |
aoqi@1 | 335 | _caller_save_fpu_regs[12] = LIR_OprFact::single_fpu(12); |
aoqi@1 | 336 | _caller_save_fpu_regs[13] = LIR_OprFact::single_fpu(13); |
aoqi@1 | 337 | _caller_save_fpu_regs[14] = LIR_OprFact::single_fpu(14); |
aoqi@1 | 338 | _caller_save_fpu_regs[15] = LIR_OprFact::single_fpu(15); |
aoqi@1 | 339 | #ifdef _LP64 |
aoqi@6880 | 340 | _caller_save_fpu_regs[16] = LIR_OprFact::single_fpu(16); |
aoqi@6880 | 341 | _caller_save_fpu_regs[17] = LIR_OprFact::single_fpu(17); |
aoqi@6880 | 342 | _caller_save_fpu_regs[18] = LIR_OprFact::single_fpu(18); |
aoqi@6880 | 343 | _caller_save_fpu_regs[19] = LIR_OprFact::single_fpu(19); |
aoqi@6880 | 344 | _caller_save_fpu_regs[20] = LIR_OprFact::single_fpu(20); |
aoqi@6880 | 345 | _caller_save_fpu_regs[21] = LIR_OprFact::single_fpu(21); |
aoqi@6880 | 346 | _caller_save_fpu_regs[22] = LIR_OprFact::single_fpu(22); |
aoqi@6880 | 347 | _caller_save_fpu_regs[23] = LIR_OprFact::single_fpu(23); |
aoqi@6880 | 348 | _caller_save_fpu_regs[24] = LIR_OprFact::single_fpu(24); |
aoqi@6880 | 349 | _caller_save_fpu_regs[25] = LIR_OprFact::single_fpu(25); |
aoqi@6880 | 350 | _caller_save_fpu_regs[26] = LIR_OprFact::single_fpu(26); |
aoqi@6880 | 351 | _caller_save_fpu_regs[27] = LIR_OprFact::single_fpu(27); |
aoqi@6880 | 352 | _caller_save_fpu_regs[28] = LIR_OprFact::single_fpu(28); |
aoqi@6880 | 353 | _caller_save_fpu_regs[29] = LIR_OprFact::single_fpu(29); |
aoqi@6880 | 354 | _caller_save_fpu_regs[30] = LIR_OprFact::single_fpu(30); |
aoqi@6880 | 355 | _caller_save_fpu_regs[31] = LIR_OprFact::single_fpu(31); |
aoqi@1 | 356 | #endif |
aoqi@1 | 357 | |
aoqi@1 | 358 | for (int i = 0; i < 32; i++) { |
aoqi@1 | 359 | _fpu_regs[i] = as_FloatRegister(i); |
aoqi@1 | 360 | } |
aoqi@1 | 361 | |
aoqi@1 | 362 | #ifndef _LP64 |
aoqi@1 | 363 | _a0_a1_long_opr=LIR_OprFact::double_cpu(4/*a0*/,5/*a1*/); |
aoqi@1 | 364 | _a2_a3_long_opr=LIR_OprFact::double_cpu(6/*a2*/,7/*a3*/); |
aoqi@1 | 365 | _v0_v1_long_opr=LIR_OprFact::double_cpu(2/*v0*/,3/*v1*/); |
aoqi@1 | 366 | #else |
aoqi@1 | 367 | _a0_a1_long_opr=LIR_OprFact::double_cpu(4/*a0*/,4/*a0*/); |
aoqi@1 | 368 | _a2_a3_long_opr=LIR_OprFact::double_cpu(6/*a2*/,6/*a2*/); |
aoqi@1 | 369 | _v0_v1_long_opr=LIR_OprFact::double_cpu(2/*v0*/,2/*v0*/); |
aoqi@1 | 370 | #endif |
aoqi@1 | 371 | _f0_float_opr =LIR_OprFact::single_fpu(0/*f0*/); |
aoqi@1 | 372 | _f12_float_opr =LIR_OprFact::single_fpu(12/*f12*/); |
aoqi@1 | 373 | _f14_float_opr =LIR_OprFact::single_fpu(14/*f14*/); |
aoqi@1 | 374 | _d0_double_opr =LIR_OprFact::double_fpu(0/*f0*/); |
aoqi@1 | 375 | _d12_double_opr=LIR_OprFact::double_fpu(12/*f12*/); |
aoqi@1 | 376 | _d14_double_opr=LIR_OprFact::double_fpu(14/*f14*/); |
aoqi@1 | 377 | |
aoqi@1 | 378 | |
aoqi@1 | 379 | _init_done = true; |
aoqi@1 | 380 | |
aoqi@1 | 381 | VMRegPair regs; |
aoqi@1 | 382 | BasicType sig_bt = T_OBJECT; |
aoqi@1 | 383 | SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true); |
aoqi@1 | 384 | |
aoqi@6880 | 385 | receiver_opr = as_oop_opr(regs.first()->as_Register()); |
aoqi@6880 | 386 | assert(receiver_opr == _t0_oop_opr, "rcvr ought to be t0"); |
aoqi@1 | 387 | |
aoqi@1 | 388 | } |
aoqi@1 | 389 | |
aoqi@1 | 390 | |
aoqi@1 | 391 | Address FrameMap::make_new_address(ByteSize sp_offset) const { |
aoqi@1 | 392 | return Address(SP, in_bytes(sp_offset)); |
aoqi@1 | 393 | } |
aoqi@1 | 394 | |
aoqi@1 | 395 | |
aoqi@1 | 396 | // ----------------mapping----------------------- |
aoqi@1 | 397 | // all mapping is based on rbp, addressing, except for simple leaf methods where we access |
aoqi@1 | 398 | // the locals rsp based (and no frame is built) |
aoqi@1 | 399 | |
aoqi@1 | 400 | |
aoqi@1 | 401 | // Frame for simple leaf methods (quick entries) |
aoqi@1 | 402 | // |
aoqi@1 | 403 | // +----------+ |
aoqi@1 | 404 | // | ret addr | <- TOS |
aoqi@1 | 405 | // +----------+ |
aoqi@1 | 406 | // | args | |
aoqi@1 | 407 | // | ...... | |
aoqi@1 | 408 | |
aoqi@1 | 409 | // Frame for standard methods |
aoqi@1 | 410 | // |
aoqi@1 | 411 | // | .........| <- TOS |
aoqi@1 | 412 | // | locals | |
aoqi@1 | 413 | // +----------+ |
aoqi@1 | 414 | // | old rbp, | <- EBP |
aoqi@1 | 415 | // +----------+ |
aoqi@1 | 416 | // | ret addr | |
aoqi@1 | 417 | // +----------+ |
aoqi@1 | 418 | // | args | |
aoqi@1 | 419 | // | .........| |
aoqi@1 | 420 | |
aoqi@1 | 421 | |
aoqi@1 | 422 | // For OopMaps, map a local variable or spill index to an VMRegImpl name. |
aoqi@1 | 423 | // This is the offset from sp() in the frame of the slot for the index, |
aoqi@1 | 424 | // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.) |
aoqi@1 | 425 | // |
aoqi@1 | 426 | // framesize + |
aoqi@1 | 427 | // stack0 stack0 0 <- VMReg |
aoqi@1 | 428 | // | | <registers> | |
aoqi@1 | 429 | // ...........|..............|.............| |
aoqi@1 | 430 | // 0 1 2 3 x x 4 5 6 ... | <- local indices |
aoqi@1 | 431 | // ^ ^ sp() ( x x indicate link |
aoqi@1 | 432 | // | | and return addr) |
aoqi@1 | 433 | // arguments non-argument locals |
aoqi@1 | 434 | |
aoqi@1 | 435 | VMReg FrameMap::fpu_regname (int n) { |
aoqi@1 | 436 | // Return the OptoReg name for the fpu stack slot "n" |
aoqi@1 | 437 | // A spilled fpu stack slot comprises to two single-word OptoReg's. |
aoqi@1 | 438 | return as_FloatRegister(n)->as_VMReg(); |
aoqi@1 | 439 | } |
aoqi@1 | 440 | |
aoqi@1 | 441 | LIR_Opr FrameMap::stack_pointer() { |
aoqi@1 | 442 | return FrameMap::_sp_opr; |
aoqi@1 | 443 | } |
aoqi@1 | 444 | |
aoqi@1 | 445 | // JSR 292 |
aoqi@1 | 446 | LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
aoqi@1 | 447 | assert(SP == mh_SP_save, "must be same register"); |
aoqi@1 | 448 | return _sp_opr; |
aoqi@1 | 449 | } |
aoqi@1 | 450 | |
aoqi@1 | 451 | bool FrameMap::validate_frame() { |
aoqi@1 | 452 | return true; |
aoqi@1 | 453 | } |