Thu, 24 May 2018 19:49:50 +0800
some C1 fix
Contributed-by: chenhaoxuan, zhaixiang, aoqi
1 /*
2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_LIR.hpp"
29 #include "runtime/sharedRuntime.hpp"
30 #include "vmreg_mips.inline.hpp"
32 const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
34 FloatRegister FrameMap::_fpu_regs[32];
35 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
36 LIR_Opr opr = LIR_OprFact::illegalOpr;
37 VMReg r_1 = reg->first();
38 VMReg r_2 = reg->second();
39 if (r_1->is_stack()) {
40 // Convert stack slot to an SP offset
41 // The calling convention does not count the
42 // SharedRuntime::out_preserve_stack_slots() value
43 // so we must add it in here.
44 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots())
45 * VMRegImpl::stack_slot_size;
46 opr = LIR_OprFact::address(new LIR_Address(_sp_opr, st_off, type));
47 } else if (r_1->is_Register()) {
48 Register reg = r_1->as_Register();
49 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
50 Register reg2 = r_2->as_Register();
51 #ifdef _LP64
52 assert(reg2 == reg, "must be same register");
53 #endif
54 opr = as_long_opr(reg, reg2);
55 } else if (type == T_OBJECT || type == T_ARRAY) {
56 opr = as_oop_opr(reg);
57 } else {
58 opr = as_opr(reg);
59 }
60 } else if (r_1->is_FloatRegister()) {
61 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
62 int num = r_1->as_FloatRegister()->encoding();
63 if (type == T_FLOAT) {
64 opr = LIR_OprFact::single_fpu(num);
65 } else {
66 opr = LIR_OprFact::double_fpu(num);
67 }
68 } else {
69 ShouldNotReachHere();
70 }
71 return opr;
72 }
74 // some useful constant RInfo's:
75 LIR_Opr FrameMap::_zero_opr;
76 LIR_Opr FrameMap::_k0_opr;
77 LIR_Opr FrameMap::_k1_opr;
78 LIR_Opr FrameMap::_at_opr;
79 LIR_Opr FrameMap::_v0_opr;
80 LIR_Opr FrameMap::_v1_opr;
81 LIR_Opr FrameMap::_a0_opr;
82 LIR_Opr FrameMap::_a1_opr;
83 LIR_Opr FrameMap::_a2_opr;
84 LIR_Opr FrameMap::_a3_opr;
85 LIR_Opr FrameMap::_t0_opr;
86 LIR_Opr FrameMap::_t1_opr;
87 LIR_Opr FrameMap::_t2_opr;
88 LIR_Opr FrameMap::_t3_opr;
89 #ifndef _LP64
90 LIR_Opr FrameMap::_t4_opr;
91 LIR_Opr FrameMap::_t5_opr;
92 LIR_Opr FrameMap::_t6_opr;
93 LIR_Opr FrameMap::_t7_opr;
94 #else
95 LIR_Opr FrameMap::_a4_opr;
96 LIR_Opr FrameMap::_a5_opr;
97 LIR_Opr FrameMap::_a6_opr;
98 LIR_Opr FrameMap::_a7_opr;
99 #endif
100 LIR_Opr FrameMap::_t8_opr;
101 LIR_Opr FrameMap::_t9_opr;
102 LIR_Opr FrameMap::_s0_opr;
103 LIR_Opr FrameMap::_s1_opr;
104 LIR_Opr FrameMap::_s2_opr;
105 LIR_Opr FrameMap::_s3_opr;
106 LIR_Opr FrameMap::_s4_opr;
107 LIR_Opr FrameMap::_s5_opr;
108 LIR_Opr FrameMap::_s6_opr;
109 LIR_Opr FrameMap::_s7_opr;
110 LIR_Opr FrameMap::_gp_opr;
111 LIR_Opr FrameMap::_fp_opr;
112 LIR_Opr FrameMap::_sp_opr;
113 LIR_Opr FrameMap::_ra_opr;
117 LIR_Opr FrameMap::_a0_a1_opr;
118 LIR_Opr FrameMap::_a2_a3_opr;
119 LIR_Opr FrameMap::_v0_v1_opr;
122 LIR_Opr FrameMap::_f0_opr;
123 LIR_Opr FrameMap::_f12_opr;
124 LIR_Opr FrameMap::_f14_opr;
125 LIR_Opr FrameMap::_d0_opr;
126 LIR_Opr FrameMap::_d12_opr;
127 LIR_Opr FrameMap::_d14_opr;
130 LIR_Opr FrameMap::receiver_opr;
132 //caller saved register
133 LIR_Opr FrameMap::_v0_oop_opr;
134 LIR_Opr FrameMap::_v1_oop_opr;
135 LIR_Opr FrameMap::_a0_oop_opr;
136 LIR_Opr FrameMap::_a1_oop_opr;
137 LIR_Opr FrameMap::_a2_oop_opr;
138 LIR_Opr FrameMap::_a3_oop_opr;
139 LIR_Opr FrameMap::_t0_oop_opr;
140 LIR_Opr FrameMap::_t1_oop_opr;
141 LIR_Opr FrameMap::_t2_oop_opr;
142 LIR_Opr FrameMap::_t3_oop_opr;
143 #ifndef _LP64
144 LIR_Opr FrameMap::_t4_oop_opr;
145 LIR_Opr FrameMap::_t5_oop_opr;
146 LIR_Opr FrameMap::_t6_oop_opr;
147 LIR_Opr FrameMap::_t7_oop_opr;
148 #else
149 LIR_Opr FrameMap::_a4_oop_opr;
150 LIR_Opr FrameMap::_a5_oop_opr;
151 LIR_Opr FrameMap::_a6_oop_opr;
152 LIR_Opr FrameMap::_a7_oop_opr;
153 #endif
154 LIR_Opr FrameMap::_t8_oop_opr;
155 LIR_Opr FrameMap::_t9_oop_opr;
156 LIR_Opr FrameMap::_s0_oop_opr;
157 LIR_Opr FrameMap::_s1_oop_opr;
158 LIR_Opr FrameMap::_s2_oop_opr;
159 LIR_Opr FrameMap::_s3_oop_opr;
160 LIR_Opr FrameMap::_s4_oop_opr;
161 LIR_Opr FrameMap::_s5_oop_opr;
162 LIR_Opr FrameMap::_s6_oop_opr;
163 LIR_Opr FrameMap::_s7_oop_opr;
165 //add metadata_opr
166 LIR_Opr FrameMap::_v0_metadata_opr;
167 LIR_Opr FrameMap::_v1_metadata_opr;
168 LIR_Opr FrameMap::_a0_metadata_opr;
169 LIR_Opr FrameMap::_a1_metadata_opr;
170 LIR_Opr FrameMap::_a2_metadata_opr;
171 LIR_Opr FrameMap::_a3_metadata_opr;
172 LIR_Opr FrameMap::_t0_metadata_opr;
173 LIR_Opr FrameMap::_t1_metadata_opr;
174 LIR_Opr FrameMap::_t2_metadata_opr;
175 LIR_Opr FrameMap::_t3_metadata_opr;
176 LIR_Opr FrameMap::_a4_metadata_opr;
177 LIR_Opr FrameMap::_a5_metadata_opr;
178 LIR_Opr FrameMap::_a6_metadata_opr;
179 LIR_Opr FrameMap::_a7_metadata_opr;
180 LIR_Opr FrameMap::_t8_metadata_opr;
181 LIR_Opr FrameMap::_t9_metadata_opr;
182 LIR_Opr FrameMap::_s0_metadata_opr;
183 LIR_Opr FrameMap::_s1_metadata_opr;
184 LIR_Opr FrameMap::_s2_metadata_opr;
185 LIR_Opr FrameMap::_s3_metadata_opr;
186 LIR_Opr FrameMap::_s4_metadata_opr;
187 LIR_Opr FrameMap::_s5_metadata_opr;
188 LIR_Opr FrameMap::_s6_metadata_opr;
189 LIR_Opr FrameMap::_s7_metadata_opr;
191 LIR_Opr FrameMap::_a0_a1_long_opr;
192 LIR_Opr FrameMap::_a2_a3_long_opr;
193 LIR_Opr FrameMap::_v0_v1_long_opr;
194 LIR_Opr FrameMap::_f0_float_opr;
195 LIR_Opr FrameMap::_f12_float_opr;
196 LIR_Opr FrameMap::_f14_float_opr;
197 LIR_Opr FrameMap::_d0_double_opr;
198 LIR_Opr FrameMap::_d12_double_opr;
199 LIR_Opr FrameMap::_d14_double_opr;
204 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
205 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
208 //--------------------------------------------------------
209 // FrameMap
210 //--------------------------------------------------------
211 FloatRegister FrameMap::nr2floatreg (int rnr) {
212 assert(_init_done, "tables not initialized");
213 debug_only(fpu_range_check(rnr);)
214 return _fpu_regs[rnr];
215 }
217 // returns true if reg could be smashed by a callee.
218 bool FrameMap::is_caller_save_register (LIR_Opr reg) {
219 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
220 if (reg->is_double_cpu()) {
221 return is_caller_save_register(reg->as_register_lo()) ||
222 is_caller_save_register(reg->as_register_hi());
223 }
224 return is_caller_save_register(reg->as_register());
225 }
227 //FIXME, why always ture? @jerome
228 bool FrameMap::is_caller_save_register (Register r) {
229 //return (r>=V0 && r<=T7) || (r==T8) || (r==T9);
230 //return ((r>=V0) && (r<=T7));
231 return true;
232 }
234 void FrameMap::initialize() {
235 if (_init_done) return;
237 assert(nof_cpu_regs == 32, "wrong number of CPU registers");
238 //init _cpu_regs for RegAlloc
239 int i = 0;
241 map_register(0,R0); _zero_opr=LIR_OprFact::single_cpu(0);
242 map_register(1,AT);
243 #ifdef _LP64
244 _at_opr=LIR_OprFact::double_cpu(1, 1);
245 #else
246 _at_opr=LIR_OprFact::single_cpu(1);
247 #endif
248 map_register(2,V0); _v0_opr=LIR_OprFact::single_cpu(2); _v0_oop_opr=LIR_OprFact::single_cpu_oop(2); _v0_metadata_opr=LIR_OprFact::single_cpu_metadata(2);
249 map_register(3,V1); _v1_opr=LIR_OprFact::single_cpu(3); _v1_oop_opr=LIR_OprFact::single_cpu_oop(3); _v1_metadata_opr=LIR_OprFact::single_cpu_metadata(3);
250 map_register(4,A0); _a0_opr=LIR_OprFact::single_cpu(4); _a0_oop_opr=LIR_OprFact::single_cpu_oop(4); _a0_metadata_opr=LIR_OprFact::single_cpu_metadata(4);
251 map_register(5,A1); _a1_opr=LIR_OprFact::single_cpu(5); _a1_oop_opr=LIR_OprFact::single_cpu_oop(5); _a1_metadata_opr=LIR_OprFact::single_cpu_metadata(5);
252 map_register(6,A2); _a2_opr=LIR_OprFact::single_cpu(6); _a2_oop_opr=LIR_OprFact::single_cpu_oop(6); _a2_metadata_opr=LIR_OprFact::single_cpu_metadata(6);
253 map_register(7,A3); _a3_opr=LIR_OprFact::single_cpu(7); _a3_oop_opr=LIR_OprFact::single_cpu_oop(7); _a3_metadata_opr=LIR_OprFact::single_cpu_metadata(7);
254 #ifndef _LP64
255 map_register(8,T0); _t0_opr=LIR_OprFact::single_cpu(8); _t0_oop_opr=LIR_OprFact::single_cpu_oop(8);
256 map_register(9,T1); _t1_opr=LIR_OprFact::single_cpu(9); _t1_oop_opr=LIR_OprFact::single_cpu_oop(9);
257 map_register(10,T2); _t2_opr=LIR_OprFact::single_cpu(10); _t2_oop_opr=LIR_OprFact::single_cpu_oop(10);
258 map_register(11,T3); _t3_opr=LIR_OprFact::single_cpu(11); _t3_oop_opr=LIR_OprFact::single_cpu_oop(11);
259 map_register(12,T4); _t4_opr=LIR_OprFact::single_cpu(12); _t4_oop_opr=LIR_OprFact::single_cpu_oop(12);
260 map_register(13,T5); _t5_opr=LIR_OprFact::single_cpu(13); _t5_oop_opr=LIR_OprFact::single_cpu_oop(13);
261 map_register(14,T6); _t6_opr=LIR_OprFact::single_cpu(14); _t6_oop_opr=LIR_OprFact::single_cpu_oop(14);
262 map_register(15,T7); _t7_opr=LIR_OprFact::single_cpu(15); _t7_oop_opr=LIR_OprFact::single_cpu_oop(15);
263 #else
264 map_register(8,A4); _a4_opr=LIR_OprFact::single_cpu(8); _a4_oop_opr=LIR_OprFact::single_cpu_oop(8); _a4_metadata_opr=LIR_OprFact::single_cpu_metadata(8);
265 map_register(9,A5); _a5_opr=LIR_OprFact::single_cpu(9); _a5_oop_opr=LIR_OprFact::single_cpu_oop(9); _a5_metadata_opr=LIR_OprFact::single_cpu_metadata(9);
266 map_register(10,A6); _a6_opr=LIR_OprFact::single_cpu(10); _a6_oop_opr=LIR_OprFact::single_cpu_oop(10); _a6_metadata_opr=LIR_OprFact::single_cpu_metadata(10);
267 map_register(11,A7); _a7_opr=LIR_OprFact::single_cpu(11); _a7_oop_opr=LIR_OprFact::single_cpu_oop(11); _a7_metadata_opr=LIR_OprFact::single_cpu_metadata(11);
268 map_register(12,T0); _t0_opr=LIR_OprFact::single_cpu(12); _t0_oop_opr=LIR_OprFact::single_cpu_oop(12); _t0_metadata_opr=LIR_OprFact::single_cpu_metadata(12);
269 map_register(13,T1); _t1_opr=LIR_OprFact::single_cpu(13); _t1_oop_opr=LIR_OprFact::single_cpu_oop(13); _t1_metadata_opr=LIR_OprFact::single_cpu_metadata(13);
270 map_register(14,T2); _t2_opr=LIR_OprFact::single_cpu(14); _t2_oop_opr=LIR_OprFact::single_cpu_oop(14); _t2_metadata_opr=LIR_OprFact::single_cpu_metadata(14);
271 map_register(15,T3); _t3_opr=LIR_OprFact::single_cpu(15); _t3_oop_opr=LIR_OprFact::single_cpu_oop(15); _t3_metadata_opr=LIR_OprFact::single_cpu_metadata(15);
272 #endif
273 map_register(16,S0); _s0_opr=LIR_OprFact::single_cpu(16); _s0_oop_opr=LIR_OprFact::single_cpu_oop(16); _s0_metadata_opr=LIR_OprFact::single_cpu_metadata(16);
274 map_register(17,S1); _s1_opr=LIR_OprFact::single_cpu(17); _s1_oop_opr=LIR_OprFact::single_cpu_oop(17); _s1_metadata_opr=LIR_OprFact::single_cpu_metadata(17);
275 map_register(18,S2); _s2_opr=LIR_OprFact::single_cpu(18); _s2_oop_opr=LIR_OprFact::single_cpu_oop(18); _s2_metadata_opr=LIR_OprFact::single_cpu_metadata(18);
276 map_register(19,S3); _s3_opr=LIR_OprFact::single_cpu(19); _s3_oop_opr=LIR_OprFact::single_cpu_oop(19); _s3_metadata_opr=LIR_OprFact::single_cpu_metadata(19);
277 map_register(20,S4); _s4_opr=LIR_OprFact::single_cpu(20); _s4_oop_opr=LIR_OprFact::single_cpu_oop(20); _s4_metadata_opr=LIR_OprFact::single_cpu_metadata(20);
278 map_register(21,S5); _s5_opr=LIR_OprFact::single_cpu(21); _s5_oop_opr=LIR_OprFact::single_cpu_oop(21); _s5_metadata_opr=LIR_OprFact::single_cpu_metadata(21);
279 map_register(22,S6); _s6_opr=LIR_OprFact::single_cpu(22); _s6_oop_opr=LIR_OprFact::single_cpu_oop(22); _s6_metadata_opr=LIR_OprFact::single_cpu_metadata(22);
280 map_register(23,S7); _s7_opr=LIR_OprFact::single_cpu(23); _s7_oop_opr=LIR_OprFact::single_cpu_oop(23); _s7_metadata_opr=LIR_OprFact::single_cpu_metadata(23);
281 map_register(24,T8); _t8_opr=LIR_OprFact::single_cpu(24);
282 map_register(25,T9); _t9_opr=LIR_OprFact::single_cpu(25);
283 map_register(26,K0); _k0_opr=LIR_OprFact::single_cpu(26);
284 map_register(27,K1); _k1_opr=LIR_OprFact::single_cpu(27);
285 map_register(28,GP); _gp_opr=LIR_OprFact::single_cpu(28);
286 map_register(29,SP);
287 #ifdef _LP64
288 _sp_opr=LIR_OprFact::double_cpu(29, 29);
289 #else
290 _sp_opr=LIR_OprFact::single_cpu(29);
291 #endif
293 map_register(30,FP); _fp_opr=LIR_OprFact::single_cpu(30);
294 map_register(31,RA); _ra_opr=LIR_OprFact::single_cpu(31);
296 _caller_save_cpu_regs[0] = _t0_opr;
297 _caller_save_cpu_regs[1] = _t1_opr;
298 _caller_save_cpu_regs[2] = _t2_opr;
299 _caller_save_cpu_regs[3] = _t3_opr;
300 #ifndef _LP64
301 _caller_save_cpu_regs[4] = _t4_opr;
302 _caller_save_cpu_regs[5] = _t5_opr;
303 _caller_save_cpu_regs[6] = _t6_opr;
304 _caller_save_cpu_regs[7] = _t7_opr;
305 #else
306 _caller_save_cpu_regs[4] = _a4_opr;
307 _caller_save_cpu_regs[5] = _a5_opr;
308 _caller_save_cpu_regs[6] = _a6_opr;
309 _caller_save_cpu_regs[7] = _a7_opr;
310 #endif
311 _caller_save_cpu_regs[8] = _s0_opr;
312 _caller_save_cpu_regs[9] = _s1_opr;
313 _caller_save_cpu_regs[10] = _s2_opr;
314 _caller_save_cpu_regs[11] = _s3_opr;
315 _caller_save_cpu_regs[12] = _s4_opr;
316 _caller_save_cpu_regs[13] = _s5_opr;
317 _caller_save_cpu_regs[14] = _s6_opr;
318 _caller_save_cpu_regs[15] = _s7_opr;
319 _caller_save_cpu_regs[16] = _v0_opr;
320 _caller_save_cpu_regs[17] = _v1_opr;
323 _caller_save_fpu_regs[0] = LIR_OprFact::single_fpu(0);
324 _caller_save_fpu_regs[1] = LIR_OprFact::single_fpu(1);
325 _caller_save_fpu_regs[2] = LIR_OprFact::single_fpu(2);
326 _caller_save_fpu_regs[3] = LIR_OprFact::single_fpu(3);
327 _caller_save_fpu_regs[4] = LIR_OprFact::single_fpu(4);
328 _caller_save_fpu_regs[5] = LIR_OprFact::single_fpu(5);
329 _caller_save_fpu_regs[6] = LIR_OprFact::single_fpu(6);
330 _caller_save_fpu_regs[7] = LIR_OprFact::single_fpu(7);
331 _caller_save_fpu_regs[8] = LIR_OprFact::single_fpu(8);
332 _caller_save_fpu_regs[9] = LIR_OprFact::single_fpu(9);
333 _caller_save_fpu_regs[10] = LIR_OprFact::single_fpu(10);
334 _caller_save_fpu_regs[11] = LIR_OprFact::single_fpu(11);
335 _caller_save_fpu_regs[12] = LIR_OprFact::single_fpu(12);
336 _caller_save_fpu_regs[13] = LIR_OprFact::single_fpu(13);
337 _caller_save_fpu_regs[14] = LIR_OprFact::single_fpu(14);
338 _caller_save_fpu_regs[15] = LIR_OprFact::single_fpu(15);
339 #ifdef _LP64
340 _caller_save_fpu_regs[16] = LIR_OprFact::single_fpu(16);
341 _caller_save_fpu_regs[17] = LIR_OprFact::single_fpu(17);
342 _caller_save_fpu_regs[18] = LIR_OprFact::single_fpu(18);
343 _caller_save_fpu_regs[19] = LIR_OprFact::single_fpu(19);
344 _caller_save_fpu_regs[20] = LIR_OprFact::single_fpu(20);
345 _caller_save_fpu_regs[21] = LIR_OprFact::single_fpu(21);
346 _caller_save_fpu_regs[22] = LIR_OprFact::single_fpu(22);
347 _caller_save_fpu_regs[23] = LIR_OprFact::single_fpu(23);
348 _caller_save_fpu_regs[24] = LIR_OprFact::single_fpu(24);
349 _caller_save_fpu_regs[25] = LIR_OprFact::single_fpu(25);
350 _caller_save_fpu_regs[26] = LIR_OprFact::single_fpu(26);
351 _caller_save_fpu_regs[27] = LIR_OprFact::single_fpu(27);
352 _caller_save_fpu_regs[28] = LIR_OprFact::single_fpu(28);
353 _caller_save_fpu_regs[29] = LIR_OprFact::single_fpu(29);
354 _caller_save_fpu_regs[30] = LIR_OprFact::single_fpu(30);
355 _caller_save_fpu_regs[31] = LIR_OprFact::single_fpu(31);
356 #endif
358 for (int i = 0; i < 32; i++) {
359 _fpu_regs[i] = as_FloatRegister(i);
360 }
362 #ifndef _LP64
363 _a0_a1_long_opr=LIR_OprFact::double_cpu(4/*a0*/,5/*a1*/);
364 _a2_a3_long_opr=LIR_OprFact::double_cpu(6/*a2*/,7/*a3*/);
365 _v0_v1_long_opr=LIR_OprFact::double_cpu(2/*v0*/,3/*v1*/);
366 #else
367 _a0_a1_long_opr=LIR_OprFact::double_cpu(4/*a0*/,4/*a0*/);
368 _a2_a3_long_opr=LIR_OprFact::double_cpu(6/*a2*/,6/*a2*/);
369 _v0_v1_long_opr=LIR_OprFact::double_cpu(2/*v0*/,2/*v0*/);
370 #endif
371 _f0_float_opr =LIR_OprFact::single_fpu(0/*f0*/);
372 _f12_float_opr =LIR_OprFact::single_fpu(12/*f12*/);
373 _f14_float_opr =LIR_OprFact::single_fpu(14/*f14*/);
374 _d0_double_opr =LIR_OprFact::double_fpu(0/*f0*/);
375 _d12_double_opr=LIR_OprFact::double_fpu(12/*f12*/);
376 _d14_double_opr=LIR_OprFact::double_fpu(14/*f14*/);
379 _init_done = true;
381 VMRegPair regs;
382 BasicType sig_bt = T_OBJECT;
383 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
385 receiver_opr = as_oop_opr(regs.first()->as_Register());
386 assert(receiver_opr == _t0_oop_opr, "rcvr ought to be t0");
388 }
391 Address FrameMap::make_new_address(ByteSize sp_offset) const {
392 return Address(SP, in_bytes(sp_offset));
393 }
396 // ----------------mapping-----------------------
397 // all mapping is based on rbp, addressing, except for simple leaf methods where we access
398 // the locals rsp based (and no frame is built)
401 // Frame for simple leaf methods (quick entries)
402 //
403 // +----------+
404 // | ret addr | <- TOS
405 // +----------+
406 // | args |
407 // | ...... |
409 // Frame for standard methods
410 //
411 // | .........| <- TOS
412 // | locals |
413 // +----------+
414 // | old rbp, | <- EBP
415 // +----------+
416 // | ret addr |
417 // +----------+
418 // | args |
419 // | .........|
422 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
423 // This is the offset from sp() in the frame of the slot for the index,
424 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
425 //
426 // framesize +
427 // stack0 stack0 0 <- VMReg
428 // | | <registers> |
429 // ...........|..............|.............|
430 // 0 1 2 3 x x 4 5 6 ... | <- local indices
431 // ^ ^ sp() ( x x indicate link
432 // | | and return addr)
433 // arguments non-argument locals
435 VMReg FrameMap::fpu_regname (int n) {
436 // Return the OptoReg name for the fpu stack slot "n"
437 // A spilled fpu stack slot comprises to two single-word OptoReg's.
438 return as_FloatRegister(n)->as_VMReg();
439 }
441 LIR_Opr FrameMap::stack_pointer() {
442 return FrameMap::_sp_opr;
443 }
445 // JSR 292
446 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
447 assert(SP == mh_SP_save, "must be same register");
448 return _sp_opr;
449 }
451 bool FrameMap::validate_frame() {
452 return true;
453 }