Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/x86/vm/icache_x86.hpp@f90c822e73f8 (annotated)
src/cpu/x86/vm/icache_x86.hpp
Wed, 27 Apr 2016 01:25:04 +0800
- author
- aoqi
- date
- Wed, 27 Apr 2016 01:25:04 +0800
- changeset 0
- f90c822e73f8
- child 6876
- 710a3c8b516e
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http://hg.openjdk.java.net/jdk8u/jdk8u/hotspot/
changeset: 6782:28b50d07f6f8
tag: jdk8u25-b17
| aoqi@0 | 1 | /* |
| aoqi@0 | 2 | * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@0 | 4 | * |
| aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@0 | 7 | * published by the Free Software Foundation. |
| aoqi@0 | 8 | * |
| aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@0 | 13 | * accompanied this code). |
| aoqi@0 | 14 | * |
| aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
| aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@0 | 18 | * |
| aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@0 | 21 | * questions. |
| aoqi@0 | 22 | * |
| aoqi@0 | 23 | */ |
| aoqi@0 | 24 | |
| aoqi@0 | 25 | #ifndef CPU_X86_VM_ICACHE_X86_HPP |
| aoqi@0 | 26 | #define CPU_X86_VM_ICACHE_X86_HPP |
| aoqi@0 | 27 | |
| aoqi@0 | 28 | // Interface for updating the instruction cache. Whenever the VM modifies |
| aoqi@0 | 29 | // code, part of the processor instruction cache potentially has to be flushed. |
| aoqi@0 | 30 | |
| aoqi@0 | 31 | // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent |
| aoqi@0 | 32 | // after the next jump, and the VM never modifies instructions directly ahead |
| aoqi@0 | 33 | // of the instruction fetch path. |
| aoqi@0 | 34 | |
| aoqi@0 | 35 | // [phh] It's not clear that the above comment is correct, because on an MP |
| aoqi@0 | 36 | // system where the dcaches are not snooped, only the thread doing the invalidate |
| aoqi@0 | 37 | // will see the update. Even in the snooped case, a memory fence would be |
| aoqi@0 | 38 | // necessary if stores weren't ordered. Fortunately, they are on all known |
| aoqi@0 | 39 | // x86 implementations. |
| aoqi@0 | 40 | |
| aoqi@0 | 41 | class ICache : public AbstractICache { |
| aoqi@0 | 42 | public: |
| aoqi@0 | 43 | #ifdef AMD64 |
| aoqi@0 | 44 | enum { |
| aoqi@0 | 45 | stub_size = 64, // Size of the icache flush stub in bytes |
| aoqi@0 | 46 | line_size = 64, // Icache line size in bytes |
| aoqi@0 | 47 | log2_line_size = 6 // log2(line_size) |
| aoqi@0 | 48 | }; |
| aoqi@0 | 49 | |
| aoqi@0 | 50 | // Use default implementation |
| aoqi@0 | 51 | #else |
| aoqi@0 | 52 | enum { |
| aoqi@0 | 53 | stub_size = 16, // Size of the icache flush stub in bytes |
| aoqi@0 | 54 | line_size = BytesPerWord, // conservative |
| aoqi@0 | 55 | log2_line_size = LogBytesPerWord // log2(line_size) |
| aoqi@0 | 56 | }; |
| aoqi@0 | 57 | #endif // AMD64 |
| aoqi@0 | 58 | }; |
| aoqi@0 | 59 | |
| aoqi@0 | 60 | #endif // CPU_X86_VM_ICACHE_X86_HPP |
