aoqi@0: /*
aoqi@0:  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
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aoqi@0:  */
aoqi@0: 
aoqi@0: #ifndef CPU_X86_VM_ICACHE_X86_HPP
aoqi@0: #define CPU_X86_VM_ICACHE_X86_HPP
aoqi@0: 
aoqi@0: // Interface for updating the instruction cache.  Whenever the VM modifies
aoqi@0: // code, part of the processor instruction cache potentially has to be flushed.
aoqi@0: 
aoqi@0: // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
aoqi@0: // after the next jump, and the VM never modifies instructions directly ahead
aoqi@0: // of the instruction fetch path.
aoqi@0: 
aoqi@0: // [phh] It's not clear that the above comment is correct, because on an MP
aoqi@0: // system where the dcaches are not snooped, only the thread doing the invalidate
aoqi@0: // will see the update.  Even in the snooped case, a memory fence would be
aoqi@0: // necessary if stores weren't ordered.  Fortunately, they are on all known
aoqi@0: // x86 implementations.
aoqi@0: 
aoqi@0: class ICache : public AbstractICache {
aoqi@0:  public:
aoqi@0: #ifdef AMD64
aoqi@0:   enum {
aoqi@0:     stub_size      = 64, // Size of the icache flush stub in bytes
aoqi@0:     line_size      = 64, // Icache line size in bytes
aoqi@0:     log2_line_size = 6   // log2(line_size)
aoqi@0:   };
aoqi@0: 
aoqi@0:   // Use default implementation
aoqi@0: #else
aoqi@0:   enum {
aoqi@0:     stub_size      = 16,                 // Size of the icache flush stub in bytes
aoqi@0:     line_size      = BytesPerWord,      // conservative
aoqi@0:     log2_line_size = LogBytesPerWord    // log2(line_size)
aoqi@0:   };
aoqi@0: #endif // AMD64
aoqi@0: };
aoqi@0: 
aoqi@0: #endif // CPU_X86_VM_ICACHE_X86_HPP