1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/icache_x86.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,60 @@
1.4 +/*
1.5 + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef CPU_X86_VM_ICACHE_X86_HPP
1.29 +#define CPU_X86_VM_ICACHE_X86_HPP
1.30 +
1.31 +// Interface for updating the instruction cache. Whenever the VM modifies
1.32 +// code, part of the processor instruction cache potentially has to be flushed.
1.33 +
1.34 +// On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
1.35 +// after the next jump, and the VM never modifies instructions directly ahead
1.36 +// of the instruction fetch path.
1.37 +
1.38 +// [phh] It's not clear that the above comment is correct, because on an MP
1.39 +// system where the dcaches are not snooped, only the thread doing the invalidate
1.40 +// will see the update. Even in the snooped case, a memory fence would be
1.41 +// necessary if stores weren't ordered. Fortunately, they are on all known
1.42 +// x86 implementations.
1.43 +
1.44 +class ICache : public AbstractICache {
1.45 + public:
1.46 +#ifdef AMD64
1.47 + enum {
1.48 + stub_size = 64, // Size of the icache flush stub in bytes
1.49 + line_size = 64, // Icache line size in bytes
1.50 + log2_line_size = 6 // log2(line_size)
1.51 + };
1.52 +
1.53 + // Use default implementation
1.54 +#else
1.55 + enum {
1.56 + stub_size = 16, // Size of the icache flush stub in bytes
1.57 + line_size = BytesPerWord, // conservative
1.58 + log2_line_size = LogBytesPerWord // log2(line_size)
1.59 + };
1.60 +#endif // AMD64
1.61 +};
1.62 +
1.63 +#endif // CPU_X86_VM_ICACHE_X86_HPP
