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src/cpu/sparc/vm/vm_version_sparc.hpp@f90c822e73f8 (annotated)

src/cpu/sparc/vm/vm_version_sparc.hpp

Wed, 27 Apr 2016 01:25:04 +0800

author
aoqi
date
Wed, 27 Apr 2016 01:25:04 +0800
changeset 0
f90c822e73f8
child 6876
710a3c8b516e
permissions
-rw-r--r--

Initial load
http://hg.openjdk.java.net/jdk8u/jdk8u/hotspot/
changeset: 6782:28b50d07f6f8
tag: jdk8u25-b17

aoqi@0 1 /*
aoqi@0 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 4 *
aoqi@0 5 * This code is free software; you can redistribute it and/or modify it
aoqi@0 6 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 7 * published by the Free Software Foundation.
aoqi@0 8 *
aoqi@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 12 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 13 * accompanied this code).
aoqi@0 14 *
aoqi@0 15 * You should have received a copy of the GNU General Public License version
aoqi@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 18 *
aoqi@0 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 20 * or visit www.oracle.com if you need additional information or have any
aoqi@0 21 * questions.
aoqi@0 22 *
aoqi@0 23 */
aoqi@0 24
aoqi@0 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0 27
aoqi@0 28 #include "runtime/globals_extension.hpp"
aoqi@0 29 #include "runtime/vm_version.hpp"
aoqi@0 30
aoqi@0 31 class VM_Version: public Abstract_VM_Version {
aoqi@0 32 protected:
aoqi@0 33 enum Feature_Flag {
aoqi@0 34 v8_instructions = 0,
aoqi@0 35 hardware_mul32 = 1,
aoqi@0 36 hardware_div32 = 2,
aoqi@0 37 hardware_fsmuld = 3,
aoqi@0 38 hardware_popc = 4,
aoqi@0 39 v9_instructions = 5,
aoqi@0 40 vis1_instructions = 6,
aoqi@0 41 vis2_instructions = 7,
aoqi@0 42 sun4v_instructions = 8,
aoqi@0 43 blk_init_instructions = 9,
aoqi@0 44 fmaf_instructions = 10,
aoqi@0 45 fmau_instructions = 11,
aoqi@0 46 vis3_instructions = 12,
aoqi@0 47 cbcond_instructions = 13,
aoqi@0 48 sparc64_family = 14,
aoqi@0 49 M_family = 15,
aoqi@0 50 T_family = 16,
aoqi@0 51 T1_model = 17,
aoqi@0 52 sparc5_instructions = 18,
aoqi@0 53 aes_instructions = 19
aoqi@0 54 };
aoqi@0 55
aoqi@0 56 enum Feature_Flag_Set {
aoqi@0 57 unknown_m = 0,
aoqi@0 58 all_features_m = -1,
aoqi@0 59
aoqi@0 60 v8_instructions_m = 1 << v8_instructions,
aoqi@0 61 hardware_mul32_m = 1 << hardware_mul32,
aoqi@0 62 hardware_div32_m = 1 << hardware_div32,
aoqi@0 63 hardware_fsmuld_m = 1 << hardware_fsmuld,
aoqi@0 64 hardware_popc_m = 1 << hardware_popc,
aoqi@0 65 v9_instructions_m = 1 << v9_instructions,
aoqi@0 66 vis1_instructions_m = 1 << vis1_instructions,
aoqi@0 67 vis2_instructions_m = 1 << vis2_instructions,
aoqi@0 68 sun4v_m = 1 << sun4v_instructions,
aoqi@0 69 blk_init_instructions_m = 1 << blk_init_instructions,
aoqi@0 70 fmaf_instructions_m = 1 << fmaf_instructions,
aoqi@0 71 fmau_instructions_m = 1 << fmau_instructions,
aoqi@0 72 vis3_instructions_m = 1 << vis3_instructions,
aoqi@0 73 cbcond_instructions_m = 1 << cbcond_instructions,
aoqi@0 74 sparc64_family_m = 1 << sparc64_family,
aoqi@0 75 M_family_m = 1 << M_family,
aoqi@0 76 T_family_m = 1 << T_family,
aoqi@0 77 T1_model_m = 1 << T1_model,
aoqi@0 78 sparc5_instructions_m = 1 << sparc5_instructions,
aoqi@0 79 aes_instructions_m = 1 << aes_instructions,
aoqi@0 80
aoqi@0 81 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
aoqi@0 82 generic_v9_m = generic_v8_m | v9_instructions_m,
aoqi@0 83 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
aoqi@0 84
aoqi@0 85 // Temporary until we have something more accurate
aoqi@0 86 niagara1_unique_m = sun4v_m,
aoqi@0 87 niagara1_m = generic_v9_m | niagara1_unique_m
aoqi@0 88 };
aoqi@0 89
aoqi@0 90 static int _features;
aoqi@0 91 static const char* _features_str;
aoqi@0 92
aoqi@0 93 static void print_features();
aoqi@0 94 static int determine_features();
aoqi@0 95 static int platform_features(int features);
aoqi@0 96
aoqi@0 97 // Returns true if the platform is in the niagara line (T series)
aoqi@0 98 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
aoqi@0 99 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
aoqi@0 100 static bool is_niagara() { return is_T_family(_features); }
aoqi@0 101 #ifdef ASSERT
aoqi@0 102 static bool is_niagara(int features) {
aoqi@0 103 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
aoqi@0 104 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
aoqi@0 105 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
aoqi@0 106 }
aoqi@0 107 #endif
aoqi@0 108
aoqi@0 109 // Returns true if it is niagara1 (T1).
aoqi@0 110 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
aoqi@0 111
aoqi@0 112 static int maximum_niagara1_processor_count() { return 32; }
aoqi@0 113
aoqi@0 114 public:
aoqi@0 115 // Initialization
aoqi@0 116 static void initialize();
aoqi@0 117
aoqi@0 118 // Instruction support
aoqi@0 119 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
aoqi@0 120 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
aoqi@0 121 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
aoqi@0 122 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
aoqi@0 123 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
aoqi@0 124 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
aoqi@0 125 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
aoqi@0 126 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
aoqi@0 127 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
aoqi@0 128 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
aoqi@0 129 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
aoqi@0 130 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
aoqi@0 131 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
aoqi@0 132
aoqi@0 133 static bool supports_compare_and_exchange()
aoqi@0 134 { return has_v9(); }
aoqi@0 135
aoqi@0 136 // Returns true if the platform is in the niagara line (T series)
aoqi@0 137 // and newer than the niagara1.
aoqi@0 138 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
aoqi@0 139
aoqi@0 140 static bool is_M_series() { return is_M_family(_features); }
aoqi@0 141 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
aoqi@0 142 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
aoqi@0 143
aoqi@0 144 // Fujitsu SPARC64
aoqi@0 145 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
aoqi@0 146
aoqi@0 147 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
aoqi@0 148 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
aoqi@0 149
aoqi@0 150 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
aoqi@0 151 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
aoqi@0 152
aoqi@0 153 // T4 and newer Sparc have fast RDPC instruction.
aoqi@0 154 static bool has_fast_rdpc() { return is_T4(); }
aoqi@0 155
aoqi@0 156 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
aoqi@0 157 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
aoqi@0 158
aoqi@0 159 static const char* cpu_features() { return _features_str; }
aoqi@0 160
aoqi@0 161 static intx prefetch_data_size() {
aoqi@0 162 return is_T4() && !is_T7() ? 32 : 64; // default prefetch block size on sparc
aoqi@0 163 }
aoqi@0 164
aoqi@0 165 // Prefetch
aoqi@0 166 static intx prefetch_copy_interval_in_bytes() {
aoqi@0 167 intx interval = PrefetchCopyIntervalInBytes;
aoqi@0 168 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0 169 }
aoqi@0 170 static intx prefetch_scan_interval_in_bytes() {
aoqi@0 171 intx interval = PrefetchScanIntervalInBytes;
aoqi@0 172 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0 173 }
aoqi@0 174 static intx prefetch_fields_ahead() {
aoqi@0 175 intx count = PrefetchFieldsAhead;
aoqi@0 176 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
aoqi@0 177 }
aoqi@0 178
aoqi@0 179 static intx allocate_prefetch_distance() {
aoqi@0 180 // This method should be called before allocate_prefetch_style().
aoqi@0 181 intx count = AllocatePrefetchDistance;
aoqi@0 182 if (count < 0) { // default is not defined ?
aoqi@0 183 count = 512;
aoqi@0 184 }
aoqi@0 185 return count;
aoqi@0 186 }
aoqi@0 187 static intx allocate_prefetch_style() {
aoqi@0 188 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
aoqi@0 189 // Return 0 if AllocatePrefetchDistance was not defined.
aoqi@0 190 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
aoqi@0 191 }
aoqi@0 192
aoqi@0 193 // Assembler testing
aoqi@0 194 static void allow_all();
aoqi@0 195 static void revert();
aoqi@0 196
aoqi@0 197 // Override the Abstract_VM_Version implementation.
aoqi@0 198 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
aoqi@0 199
aoqi@0 200 // Calculates the number of parallel threads
aoqi@0 201 static unsigned int calc_parallel_worker_threads();
aoqi@0 202 };
aoqi@0 203
aoqi@0 204 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP

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