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src/cpu/sparc/vm/vm_version_sparc.hpp@f90c822e73f8
src/cpu/sparc/vm/vm_version_sparc.hpp
Wed, 27 Apr 2016 01:25:04 +0800
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- aoqi
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- Wed, 27 Apr 2016 01:25:04 +0800
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changeset: 6782:28b50d07f6f8
tag: jdk8u25-b17
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
31 class VM_Version: public Abstract_VM_Version {
32 protected:
33 enum Feature_Flag {
34 v8_instructions = 0,
35 hardware_mul32 = 1,
36 hardware_div32 = 2,
37 hardware_fsmuld = 3,
38 hardware_popc = 4,
39 v9_instructions = 5,
40 vis1_instructions = 6,
41 vis2_instructions = 7,
42 sun4v_instructions = 8,
43 blk_init_instructions = 9,
44 fmaf_instructions = 10,
45 fmau_instructions = 11,
46 vis3_instructions = 12,
47 cbcond_instructions = 13,
48 sparc64_family = 14,
49 M_family = 15,
50 T_family = 16,
51 T1_model = 17,
52 sparc5_instructions = 18,
53 aes_instructions = 19
54 };
56 enum Feature_Flag_Set {
57 unknown_m = 0,
58 all_features_m = -1,
60 v8_instructions_m = 1 << v8_instructions,
61 hardware_mul32_m = 1 << hardware_mul32,
62 hardware_div32_m = 1 << hardware_div32,
63 hardware_fsmuld_m = 1 << hardware_fsmuld,
64 hardware_popc_m = 1 << hardware_popc,
65 v9_instructions_m = 1 << v9_instructions,
66 vis1_instructions_m = 1 << vis1_instructions,
67 vis2_instructions_m = 1 << vis2_instructions,
68 sun4v_m = 1 << sun4v_instructions,
69 blk_init_instructions_m = 1 << blk_init_instructions,
70 fmaf_instructions_m = 1 << fmaf_instructions,
71 fmau_instructions_m = 1 << fmau_instructions,
72 vis3_instructions_m = 1 << vis3_instructions,
73 cbcond_instructions_m = 1 << cbcond_instructions,
74 sparc64_family_m = 1 << sparc64_family,
75 M_family_m = 1 << M_family,
76 T_family_m = 1 << T_family,
77 T1_model_m = 1 << T1_model,
78 sparc5_instructions_m = 1 << sparc5_instructions,
79 aes_instructions_m = 1 << aes_instructions,
81 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
82 generic_v9_m = generic_v8_m | v9_instructions_m,
83 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
85 // Temporary until we have something more accurate
86 niagara1_unique_m = sun4v_m,
87 niagara1_m = generic_v9_m | niagara1_unique_m
88 };
90 static int _features;
91 static const char* _features_str;
93 static void print_features();
94 static int determine_features();
95 static int platform_features(int features);
97 // Returns true if the platform is in the niagara line (T series)
98 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
99 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
100 static bool is_niagara() { return is_T_family(_features); }
101 #ifdef ASSERT
102 static bool is_niagara(int features) {
103 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
104 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
105 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
106 }
107 #endif
109 // Returns true if it is niagara1 (T1).
110 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
112 static int maximum_niagara1_processor_count() { return 32; }
114 public:
115 // Initialization
116 static void initialize();
118 // Instruction support
119 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
120 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
121 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
122 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
123 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
124 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
125 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
126 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
127 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
128 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
129 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
130 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
131 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
133 static bool supports_compare_and_exchange()
134 { return has_v9(); }
136 // Returns true if the platform is in the niagara line (T series)
137 // and newer than the niagara1.
138 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
140 static bool is_M_series() { return is_M_family(_features); }
141 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
142 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
144 // Fujitsu SPARC64
145 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
147 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
148 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
150 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
151 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
153 // T4 and newer Sparc have fast RDPC instruction.
154 static bool has_fast_rdpc() { return is_T4(); }
156 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
157 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
159 static const char* cpu_features() { return _features_str; }
161 static intx prefetch_data_size() {
162 return is_T4() && !is_T7() ? 32 : 64; // default prefetch block size on sparc
163 }
165 // Prefetch
166 static intx prefetch_copy_interval_in_bytes() {
167 intx interval = PrefetchCopyIntervalInBytes;
168 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
169 }
170 static intx prefetch_scan_interval_in_bytes() {
171 intx interval = PrefetchScanIntervalInBytes;
172 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
173 }
174 static intx prefetch_fields_ahead() {
175 intx count = PrefetchFieldsAhead;
176 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
177 }
179 static intx allocate_prefetch_distance() {
180 // This method should be called before allocate_prefetch_style().
181 intx count = AllocatePrefetchDistance;
182 if (count < 0) { // default is not defined ?
183 count = 512;
184 }
185 return count;
186 }
187 static intx allocate_prefetch_style() {
188 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
189 // Return 0 if AllocatePrefetchDistance was not defined.
190 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
191 }
193 // Assembler testing
194 static void allow_all();
195 static void revert();
197 // Override the Abstract_VM_Version implementation.
198 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
200 // Calculates the number of parallel threads
201 static unsigned int calc_parallel_worker_threads();
202 };
204 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP
