aoqi@0: /*
aoqi@0:  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
aoqi@0:  *
aoqi@0:  */
aoqi@0: 
aoqi@0: #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0: #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0: 
aoqi@0: #include "runtime/globals_extension.hpp"
aoqi@0: #include "runtime/vm_version.hpp"
aoqi@0: 
aoqi@0: class VM_Version: public Abstract_VM_Version {
aoqi@0: protected:
aoqi@0:   enum Feature_Flag {
aoqi@0:     v8_instructions      = 0,
aoqi@0:     hardware_mul32       = 1,
aoqi@0:     hardware_div32       = 2,
aoqi@0:     hardware_fsmuld      = 3,
aoqi@0:     hardware_popc        = 4,
aoqi@0:     v9_instructions      = 5,
aoqi@0:     vis1_instructions    = 6,
aoqi@0:     vis2_instructions    = 7,
aoqi@0:     sun4v_instructions   = 8,
aoqi@0:     blk_init_instructions = 9,
aoqi@0:     fmaf_instructions    = 10,
aoqi@0:     fmau_instructions    = 11,
aoqi@0:     vis3_instructions    = 12,
aoqi@0:     cbcond_instructions  = 13,
aoqi@0:     sparc64_family       = 14,
aoqi@0:     M_family             = 15,
aoqi@0:     T_family             = 16,
aoqi@0:     T1_model             = 17,
aoqi@0:     sparc5_instructions  = 18,
aoqi@0:     aes_instructions     = 19
aoqi@0:   };
aoqi@0: 
aoqi@0:   enum Feature_Flag_Set {
aoqi@0:     unknown_m           = 0,
aoqi@0:     all_features_m      = -1,
aoqi@0: 
aoqi@0:     v8_instructions_m       = 1 << v8_instructions,
aoqi@0:     hardware_mul32_m        = 1 << hardware_mul32,
aoqi@0:     hardware_div32_m        = 1 << hardware_div32,
aoqi@0:     hardware_fsmuld_m       = 1 << hardware_fsmuld,
aoqi@0:     hardware_popc_m         = 1 << hardware_popc,
aoqi@0:     v9_instructions_m       = 1 << v9_instructions,
aoqi@0:     vis1_instructions_m     = 1 << vis1_instructions,
aoqi@0:     vis2_instructions_m     = 1 << vis2_instructions,
aoqi@0:     sun4v_m                 = 1 << sun4v_instructions,
aoqi@0:     blk_init_instructions_m = 1 << blk_init_instructions,
aoqi@0:     fmaf_instructions_m     = 1 << fmaf_instructions,
aoqi@0:     fmau_instructions_m     = 1 << fmau_instructions,
aoqi@0:     vis3_instructions_m     = 1 << vis3_instructions,
aoqi@0:     cbcond_instructions_m   = 1 << cbcond_instructions,
aoqi@0:     sparc64_family_m        = 1 << sparc64_family,
aoqi@0:     M_family_m              = 1 << M_family,
aoqi@0:     T_family_m              = 1 << T_family,
aoqi@0:     T1_model_m              = 1 << T1_model,
aoqi@0:     sparc5_instructions_m   = 1 << sparc5_instructions,
aoqi@0:     aes_instructions_m      = 1 << aes_instructions,
aoqi@0: 
aoqi@0:     generic_v8_m        = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
aoqi@0:     generic_v9_m        = generic_v8_m | v9_instructions_m,
aoqi@0:     ultra3_m            = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
aoqi@0: 
aoqi@0:     // Temporary until we have something more accurate
aoqi@0:     niagara1_unique_m   = sun4v_m,
aoqi@0:     niagara1_m          = generic_v9_m | niagara1_unique_m
aoqi@0:   };
aoqi@0: 
aoqi@0:   static int  _features;
aoqi@0:   static const char* _features_str;
aoqi@0: 
aoqi@0:   static void print_features();
aoqi@0:   static int  determine_features();
aoqi@0:   static int  platform_features(int features);
aoqi@0: 
aoqi@0:   // Returns true if the platform is in the niagara line (T series)
aoqi@0:   static bool is_M_family(int features) { return (features & M_family_m) != 0; }
aoqi@0:   static bool is_T_family(int features) { return (features & T_family_m) != 0; }
aoqi@0:   static bool is_niagara() { return is_T_family(_features); }
aoqi@0: #ifdef ASSERT
aoqi@0:   static bool is_niagara(int features)  {
aoqi@0:     // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
aoqi@0:     // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
aoqi@0:     return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
aoqi@0:   }
aoqi@0: #endif
aoqi@0: 
aoqi@0:   // Returns true if it is niagara1 (T1).
aoqi@0:   static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
aoqi@0: 
aoqi@0:   static int maximum_niagara1_processor_count() { return 32; }
aoqi@0: 
aoqi@0: public:
aoqi@0:   // Initialization
aoqi@0:   static void initialize();
aoqi@0: 
aoqi@0:   // Instruction support
aoqi@0:   static bool has_v8()                  { return (_features & v8_instructions_m) != 0; }
aoqi@0:   static bool has_v9()                  { return (_features & v9_instructions_m) != 0; }
aoqi@0:   static bool has_hardware_mul32()      { return (_features & hardware_mul32_m) != 0; }
aoqi@0:   static bool has_hardware_div32()      { return (_features & hardware_div32_m) != 0; }
aoqi@0:   static bool has_hardware_fsmuld()     { return (_features & hardware_fsmuld_m) != 0; }
aoqi@0:   static bool has_hardware_popc()       { return (_features & hardware_popc_m) != 0; }
aoqi@0:   static bool has_vis1()                { return (_features & vis1_instructions_m) != 0; }
aoqi@0:   static bool has_vis2()                { return (_features & vis2_instructions_m) != 0; }
aoqi@0:   static bool has_vis3()                { return (_features & vis3_instructions_m) != 0; }
aoqi@0:   static bool has_blk_init()            { return (_features & blk_init_instructions_m) != 0; }
aoqi@0:   static bool has_cbcond()              { return (_features & cbcond_instructions_m) != 0; }
aoqi@0:   static bool has_sparc5_instr()        { return (_features & sparc5_instructions_m) != 0; }
aoqi@0:   static bool has_aes()                 { return (_features & aes_instructions_m) != 0; }
aoqi@0: 
aoqi@0:   static bool supports_compare_and_exchange()
aoqi@0:                                         { return has_v9(); }
aoqi@0: 
aoqi@0:   // Returns true if the platform is in the niagara line (T series)
aoqi@0:   // and newer than the niagara1.
aoqi@0:   static bool is_niagara_plus()         { return is_T_family(_features) && !is_T1_model(_features); }
aoqi@0: 
aoqi@0:   static bool is_M_series()             { return is_M_family(_features); }
aoqi@0:   static bool is_T4()                   { return is_T_family(_features) && has_cbcond(); }
aoqi@0:   static bool is_T7()                   { return is_T_family(_features) && has_sparc5_instr(); }
aoqi@0: 
aoqi@0:   // Fujitsu SPARC64
aoqi@0:   static bool is_sparc64()              { return (_features & sparc64_family_m) != 0; }
aoqi@0: 
aoqi@0:   static bool is_sun4v()                { return (_features & sun4v_m) != 0; }
aoqi@0:   static bool is_ultra3()               { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
aoqi@0: 
aoqi@0:   static bool has_fast_fxtof()          { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
aoqi@0:   static bool has_fast_idiv()           { return is_niagara_plus() || is_sparc64(); }
aoqi@0: 
aoqi@0:   // T4 and newer Sparc have fast RDPC instruction.
aoqi@0:   static bool has_fast_rdpc()           { return is_T4(); }
aoqi@0: 
aoqi@0:   // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
aoqi@0:   static bool has_block_zeroing()       { return has_blk_init() && is_T4(); }
aoqi@0: 
aoqi@0:   static const char* cpu_features()     { return _features_str; }
aoqi@0: 
aoqi@0:   static intx prefetch_data_size()  {
aoqi@0:     return is_T4() && !is_T7() ? 32 : 64;  // default prefetch block size on sparc
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Prefetch
aoqi@0:   static intx prefetch_copy_interval_in_bytes() {
aoqi@0:     intx interval = PrefetchCopyIntervalInBytes;
aoqi@0:     return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0:   }
aoqi@0:   static intx prefetch_scan_interval_in_bytes() {
aoqi@0:     intx interval = PrefetchScanIntervalInBytes;
aoqi@0:     return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0:   }
aoqi@0:   static intx prefetch_fields_ahead() {
aoqi@0:     intx count = PrefetchFieldsAhead;
aoqi@0:     return count >= 0 ? count : (is_ultra3() ? 1 : 0);
aoqi@0:   }
aoqi@0: 
aoqi@0:   static intx allocate_prefetch_distance() {
aoqi@0:     // This method should be called before allocate_prefetch_style().
aoqi@0:     intx count = AllocatePrefetchDistance;
aoqi@0:     if (count < 0) { // default is not defined ?
aoqi@0:       count = 512;
aoqi@0:     }
aoqi@0:     return count;
aoqi@0:   }
aoqi@0:   static intx allocate_prefetch_style() {
aoqi@0:     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
aoqi@0:     // Return 0 if AllocatePrefetchDistance was not defined.
aoqi@0:     return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Assembler testing
aoqi@0:   static void allow_all();
aoqi@0:   static void revert();
aoqi@0: 
aoqi@0:   // Override the Abstract_VM_Version implementation.
aoqi@0:   static uint page_size_count() { return is_sun4v() ? 4 : 2; }
aoqi@0: 
aoqi@0:   // Calculates the number of parallel threads
aoqi@0:   static unsigned int calc_parallel_worker_threads();
aoqi@0: };
aoqi@0: 
aoqi@0: #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP