Fri, 20 Mar 2009 23:19:36 -0700
6814659: separable cleanups and subroutines for 6655638
Summary: preparatory but separable changes for method handles
Reviewed-by: kvn, never
duke@435 | 1 | /* |
jrose@1100 | 2 | * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | inline void MacroAssembler::pd_patch_instruction(address branch, address target) { |
duke@435 | 26 | jint& stub_inst = *(jint*) branch; |
duke@435 | 27 | stub_inst = patched_branch(target - branch, stub_inst, 0); |
duke@435 | 28 | } |
duke@435 | 29 | |
duke@435 | 30 | #ifndef PRODUCT |
duke@435 | 31 | inline void MacroAssembler::pd_print_patched_instruction(address branch) { |
duke@435 | 32 | jint stub_inst = *(jint*) branch; |
duke@435 | 33 | print_instruction(stub_inst); |
duke@435 | 34 | ::tty->print("%s", " (unresolved)"); |
duke@435 | 35 | } |
duke@435 | 36 | #endif // PRODUCT |
duke@435 | 37 | |
duke@435 | 38 | inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); } |
duke@435 | 39 | |
duke@435 | 40 | |
duke@435 | 41 | // inlines for SPARC assembler -- dmu 5/97 |
duke@435 | 42 | |
duke@435 | 43 | inline void Assembler::check_delay() { |
duke@435 | 44 | # ifdef CHECK_DELAY |
duke@435 | 45 | guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot"); |
duke@435 | 46 | delay_state = no_delay; |
duke@435 | 47 | # endif |
duke@435 | 48 | } |
duke@435 | 49 | |
duke@435 | 50 | inline void Assembler::emit_long(int x) { |
duke@435 | 51 | check_delay(); |
duke@435 | 52 | AbstractAssembler::emit_long(x); |
duke@435 | 53 | } |
duke@435 | 54 | |
duke@435 | 55 | inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { |
duke@435 | 56 | relocate(rtype); |
duke@435 | 57 | emit_long(x); |
duke@435 | 58 | } |
duke@435 | 59 | |
duke@435 | 60 | inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { |
duke@435 | 61 | relocate(rspec); |
duke@435 | 62 | emit_long(x); |
duke@435 | 63 | } |
duke@435 | 64 | |
duke@435 | 65 | |
duke@435 | 66 | inline void Assembler::add( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 67 | inline void Assembler::add( Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); } |
duke@435 | 68 | inline void Assembler::add( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); } |
duke@435 | 69 | inline void Assembler::add( const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); } |
duke@435 | 70 | |
duke@435 | 71 | inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); } |
duke@435 | 72 | inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); } |
duke@435 | 73 | |
duke@435 | 74 | inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 75 | inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); } |
duke@435 | 76 | |
duke@435 | 77 | inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } |
duke@435 | 78 | inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); } |
duke@435 | 79 | |
duke@435 | 80 | inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 81 | inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); } |
duke@435 | 82 | |
duke@435 | 83 | inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } |
duke@435 | 84 | inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); } |
duke@435 | 85 | |
duke@435 | 86 | inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } |
duke@435 | 87 | inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); } |
duke@435 | 88 | |
duke@435 | 89 | inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); } |
duke@435 | 90 | inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); } |
duke@435 | 91 | |
duke@435 | 92 | inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); } |
duke@435 | 93 | inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 94 | |
duke@435 | 95 | inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } |
duke@435 | 96 | inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); } |
duke@435 | 97 | |
duke@435 | 98 | inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); } |
duke@435 | 99 | |
duke@435 | 100 | |
duke@435 | 101 | inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); } |
duke@435 | 102 | inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 103 | |
duke@435 | 104 | inline void Assembler::ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); } |
duke@435 | 105 | |
duke@435 | 106 | inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 107 | inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 108 | inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 109 | inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 110 | |
duke@435 | 111 | inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 112 | inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 113 | inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 114 | inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 115 | inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 116 | inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 117 | |
duke@435 | 118 | inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 119 | inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 120 | |
duke@435 | 121 | inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 122 | inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 123 | inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 124 | inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 125 | inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 126 | inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 127 | inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 128 | inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 129 | inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 130 | inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 131 | |
duke@435 | 132 | inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 133 | inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 134 | inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 135 | inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 136 | |
duke@435 | 137 | #ifdef _LP64 |
duke@435 | 138 | // Make all 32 bit loads signed so 64 bit registers maintain proper sign |
duke@435 | 139 | inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); } |
duke@435 | 140 | inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); } |
duke@435 | 141 | #else |
duke@435 | 142 | inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); } |
duke@435 | 143 | inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); } |
duke@435 | 144 | #endif |
duke@435 | 145 | |
jrose@1100 | 146 | inline void Assembler::ldub( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 147 | if (s2.is_register()) ldsb(s1, s2.as_register(), d); |
jrose@1057 | 148 | else ldsb(s1, s2.as_constant(), d); |
jrose@1057 | 149 | } |
jrose@1100 | 150 | inline void Assembler::ldsb( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 151 | if (s2.is_register()) ldsb(s1, s2.as_register(), d); |
jrose@1057 | 152 | else ldsb(s1, s2.as_constant(), d); |
jrose@1057 | 153 | } |
jrose@1100 | 154 | inline void Assembler::lduh( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 155 | if (s2.is_register()) ldsh(s1, s2.as_register(), d); |
jrose@1057 | 156 | else ldsh(s1, s2.as_constant(), d); |
jrose@1057 | 157 | } |
jrose@1100 | 158 | inline void Assembler::ldsh( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 159 | if (s2.is_register()) ldsh(s1, s2.as_register(), d); |
jrose@1057 | 160 | else ldsh(s1, s2.as_constant(), d); |
jrose@1057 | 161 | } |
jrose@1100 | 162 | inline void Assembler::lduw( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 163 | if (s2.is_register()) ldsw(s1, s2.as_register(), d); |
jrose@1057 | 164 | else ldsw(s1, s2.as_constant(), d); |
jrose@1057 | 165 | } |
jrose@1100 | 166 | inline void Assembler::ldsw( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 167 | if (s2.is_register()) ldsw(s1, s2.as_register(), d); |
jrose@1057 | 168 | else ldsw(s1, s2.as_constant(), d); |
jrose@1057 | 169 | } |
jrose@1100 | 170 | inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 171 | if (s2.is_register()) ldx(s1, s2.as_register(), d); |
jrose@1057 | 172 | else ldx(s1, s2.as_constant(), d); |
jrose@1057 | 173 | } |
jrose@1100 | 174 | inline void Assembler::ld( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 175 | if (s2.is_register()) ld(s1, s2.as_register(), d); |
jrose@1057 | 176 | else ld(s1, s2.as_constant(), d); |
jrose@1057 | 177 | } |
jrose@1100 | 178 | inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { |
jrose@1057 | 179 | if (s2.is_register()) ldd(s1, s2.as_register(), d); |
jrose@1057 | 180 | else ldd(s1, s2.as_constant(), d); |
jrose@1057 | 181 | } |
jrose@1057 | 182 | |
jrose@1057 | 183 | // form effective addresses this way: |
jrose@1100 | 184 | inline void Assembler::add( Register s1, RegisterOrConstant s2, Register d, int offset) { |
jrose@1057 | 185 | if (s2.is_register()) add(s1, s2.as_register(), d); |
jrose@1057 | 186 | else { add(s1, s2.as_constant() + offset, d); offset = 0; } |
jrose@1057 | 187 | if (offset != 0) add(d, offset, d); |
jrose@1057 | 188 | } |
duke@435 | 189 | |
duke@435 | 190 | inline void Assembler::ld( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld( a.base(), a.disp() + offset, d ); } |
duke@435 | 191 | inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); } |
duke@435 | 192 | inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); } |
duke@435 | 193 | inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); } |
duke@435 | 194 | inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); } |
duke@435 | 195 | inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); } |
duke@435 | 196 | inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); } |
duke@435 | 197 | inline void Assembler::ldd( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd( a.base(), a.disp() + offset, d ); } |
duke@435 | 198 | inline void Assembler::ldx( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx( a.base(), a.disp() + offset, d ); } |
duke@435 | 199 | |
duke@435 | 200 | |
duke@435 | 201 | inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 202 | inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 203 | |
duke@435 | 204 | |
duke@435 | 205 | inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 206 | inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 207 | |
duke@435 | 208 | inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); } |
duke@435 | 209 | |
duke@435 | 210 | |
duke@435 | 211 | inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } |
duke@435 | 212 | inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); } |
duke@435 | 213 | |
duke@435 | 214 | inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); } |
duke@435 | 215 | |
duke@435 | 216 | // pp 222 |
duke@435 | 217 | |
duke@435 | 218 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); } |
duke@435 | 219 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 220 | |
duke@435 | 221 | inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); } |
duke@435 | 222 | |
duke@435 | 223 | inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 224 | inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 225 | inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 226 | inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 227 | |
duke@435 | 228 | // p 226 |
duke@435 | 229 | |
duke@435 | 230 | inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 231 | inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 232 | inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 233 | inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 234 | inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 235 | inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 236 | |
duke@435 | 237 | |
duke@435 | 238 | inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 239 | inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 240 | inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 241 | inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 242 | |
duke@435 | 243 | inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); } |
duke@435 | 244 | inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); } |
duke@435 | 245 | |
jrose@1100 | 246 | inline void Assembler::stb( Register d, Register s1, RegisterOrConstant s2) { |
jrose@1057 | 247 | if (s2.is_register()) stb(d, s1, s2.as_register()); |
jrose@1057 | 248 | else stb(d, s1, s2.as_constant()); |
jrose@1057 | 249 | } |
jrose@1100 | 250 | inline void Assembler::sth( Register d, Register s1, RegisterOrConstant s2) { |
jrose@1057 | 251 | if (s2.is_register()) sth(d, s1, s2.as_register()); |
jrose@1057 | 252 | else sth(d, s1, s2.as_constant()); |
jrose@1057 | 253 | } |
jrose@1100 | 254 | inline void Assembler::stx( Register d, Register s1, RegisterOrConstant s2) { |
jrose@1057 | 255 | if (s2.is_register()) stx(d, s1, s2.as_register()); |
jrose@1057 | 256 | else stx(d, s1, s2.as_constant()); |
jrose@1057 | 257 | } |
jrose@1100 | 258 | inline void Assembler::std( Register d, Register s1, RegisterOrConstant s2) { |
jrose@1057 | 259 | if (s2.is_register()) std(d, s1, s2.as_register()); |
jrose@1057 | 260 | else std(d, s1, s2.as_constant()); |
jrose@1057 | 261 | } |
jrose@1100 | 262 | inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { |
jrose@1057 | 263 | if (s2.is_register()) st(d, s1, s2.as_register()); |
jrose@1057 | 264 | else st(d, s1, s2.as_constant()); |
jrose@1057 | 265 | } |
jrose@1057 | 266 | |
duke@435 | 267 | inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); } |
duke@435 | 268 | inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); } |
duke@435 | 269 | inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); } |
duke@435 | 270 | inline void Assembler::st( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st( d, a.base(), a.disp() + offset); } |
duke@435 | 271 | inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); } |
duke@435 | 272 | inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); } |
duke@435 | 273 | |
duke@435 | 274 | // v8 p 99 |
duke@435 | 275 | |
duke@435 | 276 | inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); } |
duke@435 | 277 | inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 278 | inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 279 | inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 280 | inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 281 | inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 282 | inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 283 | inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 284 | |
duke@435 | 285 | |
duke@435 | 286 | // pp 231 |
duke@435 | 287 | |
duke@435 | 288 | inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); } |
duke@435 | 289 | inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 290 | |
duke@435 | 291 | inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); } |
duke@435 | 292 | |
duke@435 | 293 | |
duke@435 | 294 | // Use the right loads/stores for the platform |
duke@435 | 295 | inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 296 | #ifdef _LP64 |
duke@435 | 297 | Assembler::ldx( s1, s2, d); |
duke@435 | 298 | #else |
duke@435 | 299 | Assembler::ld( s1, s2, d); |
duke@435 | 300 | #endif |
duke@435 | 301 | } |
duke@435 | 302 | |
duke@435 | 303 | inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) { |
duke@435 | 304 | #ifdef _LP64 |
duke@435 | 305 | Assembler::ldx( s1, simm13a, d); |
duke@435 | 306 | #else |
duke@435 | 307 | Assembler::ld( s1, simm13a, d); |
duke@435 | 308 | #endif |
duke@435 | 309 | } |
duke@435 | 310 | |
jrose@1100 | 311 | inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1057 | 312 | #ifdef _LP64 |
jrose@1057 | 313 | Assembler::ldx( s1, s2, d); |
jrose@1057 | 314 | #else |
jrose@1057 | 315 | Assembler::ld( s1, s2, d); |
jrose@1057 | 316 | #endif |
jrose@1057 | 317 | } |
jrose@1057 | 318 | |
duke@435 | 319 | inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) { |
duke@435 | 320 | #ifdef _LP64 |
duke@435 | 321 | Assembler::ldx( a, d, offset ); |
duke@435 | 322 | #else |
duke@435 | 323 | Assembler::ld( a, d, offset ); |
duke@435 | 324 | #endif |
duke@435 | 325 | } |
duke@435 | 326 | |
duke@435 | 327 | inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) { |
duke@435 | 328 | #ifdef _LP64 |
duke@435 | 329 | Assembler::stx( d, s1, s2); |
duke@435 | 330 | #else |
duke@435 | 331 | Assembler::st( d, s1, s2); |
duke@435 | 332 | #endif |
duke@435 | 333 | } |
duke@435 | 334 | |
duke@435 | 335 | inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) { |
duke@435 | 336 | #ifdef _LP64 |
duke@435 | 337 | Assembler::stx( d, s1, simm13a); |
duke@435 | 338 | #else |
duke@435 | 339 | Assembler::st( d, s1, simm13a); |
duke@435 | 340 | #endif |
duke@435 | 341 | } |
duke@435 | 342 | |
jrose@1100 | 343 | inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) { |
jrose@1057 | 344 | #ifdef _LP64 |
jrose@1057 | 345 | Assembler::stx( d, s1, s2); |
jrose@1057 | 346 | #else |
jrose@1057 | 347 | Assembler::st( d, s1, s2); |
jrose@1057 | 348 | #endif |
jrose@1057 | 349 | } |
jrose@1057 | 350 | |
duke@435 | 351 | inline void MacroAssembler::st_ptr( Register d, const Address& a, int offset) { |
duke@435 | 352 | #ifdef _LP64 |
duke@435 | 353 | Assembler::stx( d, a, offset); |
duke@435 | 354 | #else |
duke@435 | 355 | Assembler::st( d, a, offset); |
duke@435 | 356 | #endif |
duke@435 | 357 | } |
duke@435 | 358 | |
duke@435 | 359 | // Use the right loads/stores for the platform |
duke@435 | 360 | inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) { |
duke@435 | 361 | #ifdef _LP64 |
duke@435 | 362 | Assembler::ldx(s1, s2, d); |
duke@435 | 363 | #else |
duke@435 | 364 | Assembler::ldd(s1, s2, d); |
duke@435 | 365 | #endif |
duke@435 | 366 | } |
duke@435 | 367 | |
duke@435 | 368 | inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) { |
duke@435 | 369 | #ifdef _LP64 |
duke@435 | 370 | Assembler::ldx(s1, simm13a, d); |
duke@435 | 371 | #else |
duke@435 | 372 | Assembler::ldd(s1, simm13a, d); |
duke@435 | 373 | #endif |
duke@435 | 374 | } |
duke@435 | 375 | |
jrose@1100 | 376 | inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1057 | 377 | #ifdef _LP64 |
jrose@1057 | 378 | Assembler::ldx(s1, s2, d); |
jrose@1057 | 379 | #else |
jrose@1057 | 380 | Assembler::ldd(s1, s2, d); |
jrose@1057 | 381 | #endif |
jrose@1057 | 382 | } |
jrose@1057 | 383 | |
duke@435 | 384 | inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) { |
duke@435 | 385 | #ifdef _LP64 |
duke@435 | 386 | Assembler::ldx(a, d, offset ); |
duke@435 | 387 | #else |
duke@435 | 388 | Assembler::ldd(a, d, offset ); |
duke@435 | 389 | #endif |
duke@435 | 390 | } |
duke@435 | 391 | |
duke@435 | 392 | inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) { |
duke@435 | 393 | #ifdef _LP64 |
duke@435 | 394 | Assembler::stx(d, s1, s2); |
duke@435 | 395 | #else |
duke@435 | 396 | Assembler::std(d, s1, s2); |
duke@435 | 397 | #endif |
duke@435 | 398 | } |
duke@435 | 399 | |
duke@435 | 400 | inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) { |
duke@435 | 401 | #ifdef _LP64 |
duke@435 | 402 | Assembler::stx(d, s1, simm13a); |
duke@435 | 403 | #else |
duke@435 | 404 | Assembler::std(d, s1, simm13a); |
duke@435 | 405 | #endif |
duke@435 | 406 | } |
duke@435 | 407 | |
jrose@1100 | 408 | inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) { |
jrose@1057 | 409 | #ifdef _LP64 |
jrose@1057 | 410 | Assembler::stx(d, s1, s2); |
jrose@1057 | 411 | #else |
jrose@1057 | 412 | Assembler::std(d, s1, s2); |
jrose@1057 | 413 | #endif |
jrose@1057 | 414 | } |
jrose@1057 | 415 | |
duke@435 | 416 | inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) { |
duke@435 | 417 | #ifdef _LP64 |
duke@435 | 418 | Assembler::stx(d, a, offset); |
duke@435 | 419 | #else |
duke@435 | 420 | Assembler::std(d, a, offset); |
duke@435 | 421 | #endif |
duke@435 | 422 | } |
duke@435 | 423 | |
duke@435 | 424 | // Functions for isolating 64 bit shifts for LP64 |
duke@435 | 425 | |
duke@435 | 426 | inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 427 | #ifdef _LP64 |
duke@435 | 428 | Assembler::sllx(s1, s2, d); |
duke@435 | 429 | #else |
duke@435 | 430 | Assembler::sll(s1, s2, d); |
duke@435 | 431 | #endif |
duke@435 | 432 | } |
duke@435 | 433 | |
duke@435 | 434 | inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) { |
duke@435 | 435 | #ifdef _LP64 |
duke@435 | 436 | Assembler::sllx(s1, imm6a, d); |
duke@435 | 437 | #else |
duke@435 | 438 | Assembler::sll(s1, imm6a, d); |
duke@435 | 439 | #endif |
duke@435 | 440 | } |
duke@435 | 441 | |
duke@435 | 442 | inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) { |
duke@435 | 443 | #ifdef _LP64 |
duke@435 | 444 | Assembler::srlx(s1, s2, d); |
duke@435 | 445 | #else |
duke@435 | 446 | Assembler::srl(s1, s2, d); |
duke@435 | 447 | #endif |
duke@435 | 448 | } |
duke@435 | 449 | |
duke@435 | 450 | inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) { |
duke@435 | 451 | #ifdef _LP64 |
duke@435 | 452 | Assembler::srlx(s1, imm6a, d); |
duke@435 | 453 | #else |
duke@435 | 454 | Assembler::srl(s1, imm6a, d); |
duke@435 | 455 | #endif |
duke@435 | 456 | } |
duke@435 | 457 | |
jrose@1100 | 458 | inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) { |
jrose@1058 | 459 | if (s2.is_register()) sll_ptr(s1, s2.as_register(), d); |
jrose@1058 | 460 | else sll_ptr(s1, s2.as_constant(), d); |
jrose@1058 | 461 | } |
jrose@1058 | 462 | |
duke@435 | 463 | // Use the right branch for the platform |
duke@435 | 464 | |
duke@435 | 465 | inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 466 | if (VM_Version::v9_instructions_work()) |
duke@435 | 467 | Assembler::bp(c, a, icc, p, d, rt); |
duke@435 | 468 | else |
duke@435 | 469 | Assembler::br(c, a, d, rt); |
duke@435 | 470 | } |
duke@435 | 471 | |
duke@435 | 472 | inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 473 | br(c, a, p, target(L)); |
duke@435 | 474 | } |
duke@435 | 475 | |
duke@435 | 476 | |
duke@435 | 477 | // Branch that tests either xcc or icc depending on the |
duke@435 | 478 | // architecture compiled (LP64 or not) |
duke@435 | 479 | inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 480 | #ifdef _LP64 |
duke@435 | 481 | Assembler::bp(c, a, xcc, p, d, rt); |
duke@435 | 482 | #else |
duke@435 | 483 | MacroAssembler::br(c, a, p, d, rt); |
duke@435 | 484 | #endif |
duke@435 | 485 | } |
duke@435 | 486 | |
duke@435 | 487 | inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 488 | brx(c, a, p, target(L)); |
duke@435 | 489 | } |
duke@435 | 490 | |
duke@435 | 491 | inline void MacroAssembler::ba( bool a, Label& L ) { |
duke@435 | 492 | br(always, a, pt, L); |
duke@435 | 493 | } |
duke@435 | 494 | |
duke@435 | 495 | // Warning: V9 only functions |
duke@435 | 496 | inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 497 | Assembler::bp(c, a, cc, p, d, rt); |
duke@435 | 498 | } |
duke@435 | 499 | |
duke@435 | 500 | inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { |
duke@435 | 501 | Assembler::bp(c, a, cc, p, L); |
duke@435 | 502 | } |
duke@435 | 503 | |
duke@435 | 504 | inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 505 | if (VM_Version::v9_instructions_work()) |
duke@435 | 506 | fbp(c, a, fcc0, p, d, rt); |
duke@435 | 507 | else |
duke@435 | 508 | Assembler::fb(c, a, d, rt); |
duke@435 | 509 | } |
duke@435 | 510 | |
duke@435 | 511 | inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) { |
duke@435 | 512 | fb(c, a, p, target(L)); |
duke@435 | 513 | } |
duke@435 | 514 | |
duke@435 | 515 | inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { |
duke@435 | 516 | Assembler::fbp(c, a, cc, p, d, rt); |
duke@435 | 517 | } |
duke@435 | 518 | |
duke@435 | 519 | inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { |
duke@435 | 520 | Assembler::fbp(c, a, cc, p, L); |
duke@435 | 521 | } |
duke@435 | 522 | |
duke@435 | 523 | inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); } |
duke@435 | 524 | inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); } |
duke@435 | 525 | |
duke@435 | 526 | // Call with a check to see if we need to deal with the added |
duke@435 | 527 | // expense of relocation and if we overflow the displacement |
duke@435 | 528 | // of the quick call instruction./ |
duke@435 | 529 | // Check to see if we have to deal with relocations |
duke@435 | 530 | inline void MacroAssembler::call( address d, relocInfo::relocType rt ) { |
duke@435 | 531 | #ifdef _LP64 |
duke@435 | 532 | intptr_t disp; |
duke@435 | 533 | // NULL is ok because it will be relocated later. |
duke@435 | 534 | // Must change NULL to a reachable address in order to |
duke@435 | 535 | // pass asserts here and in wdisp. |
duke@435 | 536 | if ( d == NULL ) |
duke@435 | 537 | d = pc(); |
duke@435 | 538 | |
duke@435 | 539 | // Is this address within range of the call instruction? |
duke@435 | 540 | // If not, use the expensive instruction sequence |
duke@435 | 541 | disp = (intptr_t)d - (intptr_t)pc(); |
duke@435 | 542 | if ( disp != (intptr_t)(int32_t)disp ) { |
duke@435 | 543 | relocate(rt); |
duke@435 | 544 | Address dest(O7, (address)d); |
duke@435 | 545 | sethi(dest, /*ForceRelocatable=*/ true); |
duke@435 | 546 | jmpl(dest, O7); |
duke@435 | 547 | } |
duke@435 | 548 | else { |
duke@435 | 549 | Assembler::call( d, rt ); |
duke@435 | 550 | } |
duke@435 | 551 | #else |
duke@435 | 552 | Assembler::call( d, rt ); |
duke@435 | 553 | #endif |
duke@435 | 554 | } |
duke@435 | 555 | |
duke@435 | 556 | inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) { |
duke@435 | 557 | MacroAssembler::call( target(L), rt); |
duke@435 | 558 | } |
duke@435 | 559 | |
duke@435 | 560 | |
duke@435 | 561 | |
duke@435 | 562 | inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); } |
duke@435 | 563 | inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); } |
duke@435 | 564 | |
duke@435 | 565 | // prefetch instruction |
duke@435 | 566 | inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) { |
duke@435 | 567 | if (VM_Version::v9_instructions_work()) |
duke@435 | 568 | Assembler::bp( never, true, xcc, pt, d, rt ); |
duke@435 | 569 | } |
duke@435 | 570 | inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); } |
duke@435 | 571 | |
duke@435 | 572 | |
duke@435 | 573 | // clobbers o7 on V8!! |
duke@435 | 574 | // returns delta from gotten pc to addr after |
duke@435 | 575 | inline int MacroAssembler::get_pc( Register d ) { |
duke@435 | 576 | int x = offset(); |
duke@435 | 577 | if (VM_Version::v9_instructions_work()) |
duke@435 | 578 | rdpc(d); |
duke@435 | 579 | else { |
duke@435 | 580 | Label lbl; |
duke@435 | 581 | Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8 |
duke@435 | 582 | if (d == O7) delayed()->nop(); |
duke@435 | 583 | else delayed()->mov(O7, d); |
duke@435 | 584 | bind(lbl); |
duke@435 | 585 | } |
duke@435 | 586 | return offset() - x; |
duke@435 | 587 | } |
duke@435 | 588 | |
duke@435 | 589 | |
duke@435 | 590 | // Note: All MacroAssembler::set_foo functions are defined out-of-line. |
duke@435 | 591 | |
duke@435 | 592 | |
duke@435 | 593 | // Loads the current PC of the following instruction as an immediate value in |
duke@435 | 594 | // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other. |
duke@435 | 595 | inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) { |
duke@435 | 596 | intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip; |
duke@435 | 597 | #ifdef _LP64 |
duke@435 | 598 | Unimplemented(); |
duke@435 | 599 | #else |
duke@435 | 600 | Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc)); |
duke@435 | 601 | Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc)); |
duke@435 | 602 | #endif |
duke@435 | 603 | return thepc; |
duke@435 | 604 | } |
duke@435 | 605 | |
duke@435 | 606 | inline void MacroAssembler::load_address( Address& a, int offset ) { |
duke@435 | 607 | assert_not_delayed(); |
duke@435 | 608 | #ifdef _LP64 |
duke@435 | 609 | sethi(a); |
duke@435 | 610 | add(a, a.base(), offset); |
duke@435 | 611 | #else |
duke@435 | 612 | if (a.hi() == 0 && a.rtype() == relocInfo::none) { |
duke@435 | 613 | set(a.disp() + offset, a.base()); |
duke@435 | 614 | } |
duke@435 | 615 | else { |
duke@435 | 616 | sethi(a); |
duke@435 | 617 | add(a, a.base(), offset); |
duke@435 | 618 | } |
duke@435 | 619 | #endif |
duke@435 | 620 | } |
duke@435 | 621 | |
duke@435 | 622 | |
duke@435 | 623 | inline void MacroAssembler::split_disp( Address& a, Register temp ) { |
duke@435 | 624 | assert_not_delayed(); |
duke@435 | 625 | a = a.split_disp(); |
duke@435 | 626 | Assembler::sethi(a.hi(), temp, a.rspec()); |
duke@435 | 627 | add(a.base(), temp, a.base()); |
duke@435 | 628 | } |
duke@435 | 629 | |
duke@435 | 630 | |
duke@435 | 631 | inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) { |
duke@435 | 632 | assert_not_delayed(); |
duke@435 | 633 | sethi(a); |
duke@435 | 634 | ld(a, d, offset); |
duke@435 | 635 | } |
duke@435 | 636 | |
duke@435 | 637 | |
duke@435 | 638 | inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) { |
duke@435 | 639 | assert_not_delayed(); |
duke@435 | 640 | sethi(a); |
duke@435 | 641 | ld_ptr(a, d, offset); |
duke@435 | 642 | } |
duke@435 | 643 | |
duke@435 | 644 | |
duke@435 | 645 | inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) { |
duke@435 | 646 | assert_not_delayed(); |
duke@435 | 647 | sethi(a); |
duke@435 | 648 | st(s, a, offset); |
duke@435 | 649 | } |
duke@435 | 650 | |
duke@435 | 651 | |
duke@435 | 652 | inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) { |
duke@435 | 653 | assert_not_delayed(); |
duke@435 | 654 | sethi(a); |
duke@435 | 655 | st_ptr(s, a, offset); |
duke@435 | 656 | } |
duke@435 | 657 | |
duke@435 | 658 | |
duke@435 | 659 | // This code sequence is relocatable to any address, even on LP64. |
duke@435 | 660 | inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) { |
duke@435 | 661 | assert_not_delayed(); |
duke@435 | 662 | // Force fixed length sethi because NativeJump and NativeFarCall don't handle |
duke@435 | 663 | // variable length instruction streams. |
duke@435 | 664 | sethi(a, /*ForceRelocatable=*/ true); |
duke@435 | 665 | jmpl(a, d, offset); |
duke@435 | 666 | } |
duke@435 | 667 | |
duke@435 | 668 | |
duke@435 | 669 | inline void MacroAssembler::jump_to( Address& a, int offset ) { |
duke@435 | 670 | jumpl_to( a, G0, offset ); |
duke@435 | 671 | } |
duke@435 | 672 | |
duke@435 | 673 | |
duke@435 | 674 | inline void MacroAssembler::set_oop( jobject obj, Register d ) { |
duke@435 | 675 | set_oop(allocate_oop_address(obj, d)); |
duke@435 | 676 | } |
duke@435 | 677 | |
duke@435 | 678 | |
duke@435 | 679 | inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) { |
duke@435 | 680 | set_oop(constant_oop_address(obj, d)); |
duke@435 | 681 | } |
duke@435 | 682 | |
duke@435 | 683 | |
duke@435 | 684 | inline void MacroAssembler::set_oop( Address obj_addr ) { |
duke@435 | 685 | assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc"); |
duke@435 | 686 | load_address(obj_addr); |
duke@435 | 687 | } |
duke@435 | 688 | |
duke@435 | 689 | |
duke@435 | 690 | inline void MacroAssembler::load_argument( Argument& a, Register d ) { |
duke@435 | 691 | if (a.is_register()) |
duke@435 | 692 | mov(a.as_register(), d); |
duke@435 | 693 | else |
duke@435 | 694 | ld (a.as_address(), d); |
duke@435 | 695 | } |
duke@435 | 696 | |
duke@435 | 697 | inline void MacroAssembler::store_argument( Register s, Argument& a ) { |
duke@435 | 698 | if (a.is_register()) |
duke@435 | 699 | mov(s, a.as_register()); |
duke@435 | 700 | else |
duke@435 | 701 | st_ptr (s, a.as_address()); // ABI says everything is right justified. |
duke@435 | 702 | } |
duke@435 | 703 | |
duke@435 | 704 | inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) { |
duke@435 | 705 | if (a.is_register()) |
duke@435 | 706 | mov(s, a.as_register()); |
duke@435 | 707 | else |
duke@435 | 708 | st_ptr (s, a.as_address()); |
duke@435 | 709 | } |
duke@435 | 710 | |
duke@435 | 711 | |
duke@435 | 712 | #ifdef _LP64 |
duke@435 | 713 | inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) { |
duke@435 | 714 | if (a.is_float_register()) |
duke@435 | 715 | // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2 |
duke@435 | 716 | fmov(FloatRegisterImpl::S, s, a.as_float_register() ); |
duke@435 | 717 | else |
duke@435 | 718 | // Floats are stored in the high half of the stack entry |
duke@435 | 719 | // The low half is undefined per the ABI. |
duke@435 | 720 | stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat)); |
duke@435 | 721 | } |
duke@435 | 722 | |
duke@435 | 723 | inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) { |
duke@435 | 724 | if (a.is_float_register()) |
duke@435 | 725 | // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2 |
duke@435 | 726 | fmov(FloatRegisterImpl::D, s, a.as_double_register() ); |
duke@435 | 727 | else |
duke@435 | 728 | stf(FloatRegisterImpl::D, s, a.as_address()); |
duke@435 | 729 | } |
duke@435 | 730 | |
duke@435 | 731 | inline void MacroAssembler::store_long_argument( Register s, Argument& a ) { |
duke@435 | 732 | if (a.is_register()) |
duke@435 | 733 | mov(s, a.as_register()); |
duke@435 | 734 | else |
duke@435 | 735 | stx(s, a.as_address()); |
duke@435 | 736 | } |
duke@435 | 737 | #endif |
duke@435 | 738 | |
duke@435 | 739 | inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); } |
duke@435 | 740 | inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); } |
duke@435 | 741 | inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); } |
duke@435 | 742 | inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); } |
duke@435 | 743 | |
duke@435 | 744 | inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); } |
duke@435 | 745 | inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); } |
duke@435 | 746 | inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); } |
duke@435 | 747 | inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); } |
duke@435 | 748 | |
duke@435 | 749 | // returns if membar generates anything, obviously this code should mirror |
duke@435 | 750 | // membar below. |
duke@435 | 751 | inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) { |
duke@435 | 752 | if( !os::is_MP() ) return false; // Not needed on single CPU |
duke@435 | 753 | if( VM_Version::v9_instructions_work() ) { |
duke@435 | 754 | const Membar_mask_bits effective_mask = |
duke@435 | 755 | Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); |
duke@435 | 756 | return (effective_mask != 0); |
duke@435 | 757 | } else { |
duke@435 | 758 | return true; |
duke@435 | 759 | } |
duke@435 | 760 | } |
duke@435 | 761 | |
duke@435 | 762 | inline void MacroAssembler::membar( Membar_mask_bits const7a ) { |
duke@435 | 763 | // Uniprocessors do not need memory barriers |
duke@435 | 764 | if (!os::is_MP()) return; |
duke@435 | 765 | // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3, |
duke@435 | 766 | // 8.4.4.3, a.31 and a.50. |
duke@435 | 767 | if( VM_Version::v9_instructions_work() ) { |
duke@435 | 768 | // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value |
duke@435 | 769 | // of the mmask subfield of const7a that does anything that isn't done |
duke@435 | 770 | // implicitly is StoreLoad. |
duke@435 | 771 | const Membar_mask_bits effective_mask = |
duke@435 | 772 | Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); |
duke@435 | 773 | if ( effective_mask != 0 ) { |
duke@435 | 774 | Assembler::membar( effective_mask ); |
duke@435 | 775 | } |
duke@435 | 776 | } else { |
duke@435 | 777 | // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We |
duke@435 | 778 | // do not issue the stbar because to my knowledge all v8 machines implement TSO, |
duke@435 | 779 | // which guarantees that all stores behave as if an stbar were issued just after |
duke@435 | 780 | // each one of them. On these machines, stbar ought to be a nop. There doesn't |
duke@435 | 781 | // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it, |
duke@435 | 782 | // it can't be specified by stbar, nor have I come up with a way to simulate it. |
duke@435 | 783 | // |
duke@435 | 784 | // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent |
duke@435 | 785 | // space. Put one here to be on the safe side. |
duke@435 | 786 | Assembler::ldstub(SP, 0, G0); |
duke@435 | 787 | } |
duke@435 | 788 | } |