duke@435: /*
jrose@1100:  * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
duke@435:   jint& stub_inst = *(jint*) branch;
duke@435:   stub_inst = patched_branch(target - branch, stub_inst, 0);
duke@435: }
duke@435: 
duke@435: #ifndef PRODUCT
duke@435: inline void MacroAssembler::pd_print_patched_instruction(address branch) {
duke@435:   jint stub_inst = *(jint*) branch;
duke@435:   print_instruction(stub_inst);
duke@435:   ::tty->print("%s", " (unresolved)");
duke@435: }
duke@435: #endif // PRODUCT
duke@435: 
duke@435: inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
duke@435: 
duke@435: 
duke@435: // inlines for SPARC assembler -- dmu 5/97
duke@435: 
duke@435: inline void Assembler::check_delay() {
duke@435: # ifdef CHECK_DELAY
duke@435:   guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
duke@435:   delay_state = no_delay;
duke@435: # endif
duke@435: }
duke@435: 
duke@435: inline void Assembler::emit_long(int x) {
duke@435:   check_delay();
duke@435:   AbstractAssembler::emit_long(x);
duke@435: }
duke@435: 
duke@435: inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
duke@435:   relocate(rtype);
duke@435:   emit_long(x);
duke@435: }
duke@435: 
duke@435: inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
duke@435:   relocate(rspec);
duke@435:   emit_long(x);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void Assembler::add(    Register s1, Register s2, Register d )                             { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::add(    Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
duke@435: inline void Assembler::add(    Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
duke@435: inline void Assembler::add(    const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
duke@435: 
duke@435: inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }
duke@435: inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
duke@435: 
duke@435: inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
duke@435: inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
duke@435: 
duke@435: inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
duke@435: inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
duke@435: 
duke@435: inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
duke@435: inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
duke@435: 
duke@435: inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
duke@435: inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
duke@435: 
duke@435: inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
duke@435: inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
duke@435: 
duke@435: inline void Assembler::call( address d,  relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
duke@435: inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }
duke@435: 
duke@435: inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
duke@435: inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::jmpl( Register s1, Register s2, Register d                          ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
duke@435: inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }
duke@435: 
duke@435: inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); }
duke@435: 
duke@435: 
duke@435: inline void Assembler::ldf(    FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldf(    FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::ldf(    FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
duke@435: 
duke@435: inline void Assembler::ldfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::ldc(   Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldc(   Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::lddc(  Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::lddc(  Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::ldsb(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldsb(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::ldsh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldsh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::ldsw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldsw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::ldub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::lduh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::lduh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::lduw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::lduw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::ldx(   Register s1, Register s2, Register d) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldx(   Register s1, int simm13a, Register d) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::ldd(   Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldd(   Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: #ifdef _LP64
duke@435: // Make all 32 bit loads signed so 64 bit registers maintain proper sign
duke@435: inline void Assembler::ld(  Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
duke@435: inline void Assembler::ld(  Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
duke@435: #else
duke@435: inline void Assembler::ld(  Register s1, Register s2, Register d) { lduw( s1, s2, d); }
duke@435: inline void Assembler::ld(  Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
duke@435: #endif
duke@435: 
jrose@1100: inline void Assembler::ldub(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsb(s1, s2.as_register(), d);
jrose@1057:   else                   ldsb(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ldsb(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsb(s1, s2.as_register(), d);
jrose@1057:   else                   ldsb(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::lduh(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsh(s1, s2.as_register(), d);
jrose@1057:   else                   ldsh(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ldsh(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsh(s1, s2.as_register(), d);
jrose@1057:   else                   ldsh(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::lduw(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsw(s1, s2.as_register(), d);
jrose@1057:   else                   ldsw(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ldsw(  Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldsw(s1, s2.as_register(), d);
jrose@1057:   else                   ldsw(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ldx(   Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldx(s1, s2.as_register(), d);
jrose@1057:   else                   ldx(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ld(    Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ld(s1, s2.as_register(), d);
jrose@1057:   else                   ld(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1100: inline void Assembler::ldd(   Register s1, RegisterOrConstant s2, Register d) {
jrose@1057:   if (s2.is_register())  ldd(s1, s2.as_register(), d);
jrose@1057:   else                   ldd(s1, s2.as_constant(), d);
jrose@1057: }
jrose@1057: 
jrose@1057: // form effective addresses this way:
jrose@1100: inline void Assembler::add(   Register s1, RegisterOrConstant s2, Register d, int offset) {
jrose@1057:   if (s2.is_register())  add(s1, s2.as_register(), d);
jrose@1057:   else                 { add(s1, s2.as_constant() + offset, d); offset = 0; }
jrose@1057:   if (offset != 0)       add(d,  offset,                    d);
jrose@1057: }
duke@435: 
duke@435: inline void Assembler::ld(   const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld(   a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldd(  const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd(  a.base(), a.disp() + offset, d ); }
duke@435: inline void Assembler::ldx(  const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx(  a.base(), a.disp() + offset, d ); }
duke@435: 
duke@435: 
duke@435: inline void Assembler::ldstub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::ldstub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: 
duke@435: inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
duke@435: 
duke@435: 
duke@435: inline void Assembler::rett( Register s1, Register s2                         ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
duke@435: inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt);  has_delay_slot(); }
duke@435: 
duke@435: inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
duke@435: 
duke@435:   // pp 222
duke@435: 
duke@435: inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
duke@435: 
duke@435: inline void Assembler::stfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::stxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435:   // p 226
duke@435: 
duke@435: inline void Assembler::stb(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stb(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::sth(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::sth(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::stw(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stw(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: 
duke@435: inline void Assembler::stx(  Register d, Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stx(  Register d, Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::std(  Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::std(  Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::st(  Register d, Register s1, Register s2) { stw(d, s1, s2); }
duke@435: inline void Assembler::st(  Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
duke@435: 
jrose@1100: inline void Assembler::stb(  Register d, Register s1, RegisterOrConstant s2) {
jrose@1057:   if (s2.is_register())  stb(d, s1, s2.as_register());
jrose@1057:   else                   stb(d, s1, s2.as_constant());
jrose@1057: }
jrose@1100: inline void Assembler::sth(  Register d, Register s1, RegisterOrConstant s2) {
jrose@1057:   if (s2.is_register())  sth(d, s1, s2.as_register());
jrose@1057:   else                   sth(d, s1, s2.as_constant());
jrose@1057: }
jrose@1100: inline void Assembler::stx(  Register d, Register s1, RegisterOrConstant s2) {
jrose@1057:   if (s2.is_register())  stx(d, s1, s2.as_register());
jrose@1057:   else                   stx(d, s1, s2.as_constant());
jrose@1057: }
jrose@1100: inline void Assembler::std( Register d, Register s1, RegisterOrConstant s2) {
jrose@1057:   if (s2.is_register())  std(d, s1, s2.as_register());
jrose@1057:   else                   std(d, s1, s2.as_constant());
jrose@1057: }
jrose@1100: inline void Assembler::st(  Register d, Register s1, RegisterOrConstant s2) {
jrose@1057:   if (s2.is_register())  st(d, s1, s2.as_register());
jrose@1057:   else                   st(d, s1, s2.as_constant());
jrose@1057: }
jrose@1057: 
duke@435: inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); }
duke@435: inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); }
duke@435: inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); }
duke@435: inline void Assembler::st(  Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st(  d, a.base(), a.disp() + offset); }
duke@435: inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); }
duke@435: inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); }
duke@435: 
duke@435: // v8 p 99
duke@435: 
duke@435: inline void Assembler::stc(    int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stc(    int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::stdc(   int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stdc(   int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::stcsr(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stcsr(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: inline void Assembler::stdcq(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::stdcq(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: 
duke@435: // pp 231
duke@435: 
duke@435: inline void Assembler::swap(    Register s1, Register s2, Register d) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
duke@435: inline void Assembler::swap(    Register s1, int simm13a, Register d) { v9_dep();  emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@435: 
duke@435: inline void Assembler::swap(    Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap(  a.base(), a.disp() + offset, d ); }
duke@435: 
duke@435: 
duke@435: // Use the right loads/stores for the platform
duke@435: inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx( s1, s2, d);
duke@435: #else
duke@435:   Assembler::ld(  s1, s2, d);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx( s1, simm13a, d);
duke@435: #else
duke@435:   Assembler::ld(  s1, simm13a, d);
duke@435: #endif
duke@435: }
duke@435: 
jrose@1100: inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
jrose@1057: #ifdef _LP64
jrose@1057:   Assembler::ldx( s1, s2, d);
jrose@1057: #else
jrose@1057:   Assembler::ld(  s1, s2, d);
jrose@1057: #endif
jrose@1057: }
jrose@1057: 
duke@435: inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx(  a, d, offset );
duke@435: #else
duke@435:   Assembler::ld(   a, d, offset );
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx( d, s1, s2);
duke@435: #else
duke@435:   Assembler::st( d, s1, s2);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx( d, s1, simm13a);
duke@435: #else
duke@435:   Assembler::st( d, s1, simm13a);
duke@435: #endif
duke@435: }
duke@435: 
jrose@1100: inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
jrose@1057: #ifdef _LP64
jrose@1057:   Assembler::stx( d, s1, s2);
jrose@1057: #else
jrose@1057:   Assembler::st( d, s1, s2);
jrose@1057: #endif
jrose@1057: }
jrose@1057: 
duke@435: inline void MacroAssembler::st_ptr(  Register d, const Address& a, int offset) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx(  d, a, offset);
duke@435: #else
duke@435:   Assembler::st(  d, a, offset);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: // Use the right loads/stores for the platform
duke@435: inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx(s1, s2, d);
duke@435: #else
duke@435:   Assembler::ldd(s1, s2, d);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx(s1, simm13a, d);
duke@435: #else
duke@435:   Assembler::ldd(s1, simm13a, d);
duke@435: #endif
duke@435: }
duke@435: 
jrose@1100: inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
jrose@1057: #ifdef _LP64
jrose@1057:   Assembler::ldx(s1, s2, d);
jrose@1057: #else
jrose@1057:   Assembler::ldd(s1, s2, d);
jrose@1057: #endif
jrose@1057: }
jrose@1057: 
duke@435: inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::ldx(a, d, offset );
duke@435: #else
duke@435:   Assembler::ldd(a, d, offset );
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx(d, s1, s2);
duke@435: #else
duke@435:   Assembler::std(d, s1, s2);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx(d, s1, simm13a);
duke@435: #else
duke@435:   Assembler::std(d, s1, simm13a);
duke@435: #endif
duke@435: }
duke@435: 
jrose@1100: inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
jrose@1057: #ifdef _LP64
jrose@1057:   Assembler::stx(d, s1, s2);
jrose@1057: #else
jrose@1057:   Assembler::std(d, s1, s2);
jrose@1057: #endif
jrose@1057: }
jrose@1057: 
duke@435: inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::stx(d, a, offset);
duke@435: #else
duke@435:   Assembler::std(d, a, offset);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: // Functions for isolating 64 bit shifts for LP64
duke@435: 
duke@435: inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::sllx(s1, s2, d);
duke@435: #else
duke@435:   Assembler::sll(s1, s2, d);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::sll_ptr( Register s1, int imm6a,   Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::sllx(s1, imm6a, d);
duke@435: #else
duke@435:   Assembler::sll(s1, imm6a, d);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::srlx(s1, s2, d);
duke@435: #else
duke@435:   Assembler::srl(s1, s2, d);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::srl_ptr( Register s1, int imm6a,   Register d ) {
duke@435: #ifdef _LP64
duke@435:   Assembler::srlx(s1, imm6a, d);
duke@435: #else
duke@435:   Assembler::srl(s1, imm6a, d);
duke@435: #endif
duke@435: }
duke@435: 
jrose@1100: inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
jrose@1058:   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);
jrose@1058:   else                   sll_ptr(s1, s2.as_constant(), d);
jrose@1058: }
jrose@1058: 
duke@435: // Use the right branch for the platform
duke@435: 
duke@435: inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@435:   if (VM_Version::v9_instructions_work())
duke@435:     Assembler::bp(c, a, icc, p, d, rt);
duke@435:   else
duke@435:     Assembler::br(c, a, d, rt);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
duke@435:   br(c, a, p, target(L));
duke@435: }
duke@435: 
duke@435: 
duke@435: // Branch that tests either xcc or icc depending on the
duke@435: // architecture compiled (LP64 or not)
duke@435: inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@435: #ifdef _LP64
duke@435:     Assembler::bp(c, a, xcc, p, d, rt);
duke@435: #else
duke@435:     MacroAssembler::br(c, a, p, d, rt);
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
duke@435:   brx(c, a, p, target(L));
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::ba( bool a, Label& L ) {
duke@435:   br(always, a, pt, L);
duke@435: }
duke@435: 
duke@435: // Warning: V9 only functions
duke@435: inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
duke@435:   Assembler::bp(c, a, cc, p, d, rt);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
duke@435:   Assembler::bp(c, a, cc, p, L);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@435:   if (VM_Version::v9_instructions_work())
duke@435:     fbp(c, a, fcc0, p, d, rt);
duke@435:   else
duke@435:     Assembler::fb(c, a, d, rt);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
duke@435:   fb(c, a, p, target(L));
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
duke@435:   Assembler::fbp(c, a, cc, p, d, rt);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
duke@435:   Assembler::fbp(c, a, cc, p, L);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
duke@435: inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
duke@435: 
duke@435: // Call with a check to see if we need to deal with the added
duke@435: // expense of relocation and if we overflow the displacement
duke@435: // of the quick call instruction./
duke@435: // Check to see if we have to deal with relocations
duke@435: inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
duke@435: #ifdef _LP64
duke@435:   intptr_t disp;
duke@435:   // NULL is ok because it will be relocated later.
duke@435:   // Must change NULL to a reachable address in order to
duke@435:   // pass asserts here and in wdisp.
duke@435:   if ( d == NULL )
duke@435:     d = pc();
duke@435: 
duke@435:   // Is this address within range of the call instruction?
duke@435:   // If not, use the expensive instruction sequence
duke@435:   disp = (intptr_t)d - (intptr_t)pc();
duke@435:   if ( disp != (intptr_t)(int32_t)disp ) {
duke@435:     relocate(rt);
duke@435:     Address dest(O7, (address)d);
duke@435:     sethi(dest, /*ForceRelocatable=*/ true);
duke@435:     jmpl(dest, O7);
duke@435:   }
duke@435:   else {
duke@435:     Assembler::call( d, rt );
duke@435:   }
duke@435: #else
duke@435:   Assembler::call( d, rt );
duke@435: #endif
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::call( Label& L,   relocInfo::relocType rt ) {
duke@435:   MacroAssembler::call( target(L), rt);
duke@435: }
duke@435: 
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
duke@435: inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
duke@435: 
duke@435: // prefetch instruction
duke@435: inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
duke@435:   if (VM_Version::v9_instructions_work())
duke@435:     Assembler::bp( never, true, xcc, pt, d, rt );
duke@435: }
duke@435: inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
duke@435: 
duke@435: 
duke@435: // clobbers o7 on V8!!
duke@435: // returns delta from gotten pc to addr after
duke@435: inline int MacroAssembler::get_pc( Register d ) {
duke@435:   int x = offset();
duke@435:   if (VM_Version::v9_instructions_work())
duke@435:     rdpc(d);
duke@435:   else {
duke@435:     Label lbl;
duke@435:     Assembler::call(lbl, relocInfo::none);  // No relocation as this is call to pc+0x8
duke@435:     if (d == O7)  delayed()->nop();
duke@435:     else          delayed()->mov(O7, d);
duke@435:     bind(lbl);
duke@435:   }
duke@435:   return offset() - x;
duke@435: }
duke@435: 
duke@435: 
duke@435: // Note:  All MacroAssembler::set_foo functions are defined out-of-line.
duke@435: 
duke@435: 
duke@435: // Loads the current PC of the following instruction as an immediate value in
duke@435: // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.
duke@435: inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
duke@435:   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
duke@435: #ifdef _LP64
duke@435:   Unimplemented();
duke@435: #else
duke@435:   Assembler::sethi(  thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
duke@435:   Assembler::add(reg,thepc &  0x3ff, reg, internal_word_Relocation::spec((address)thepc));
duke@435: #endif
duke@435:   return thepc;
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::load_address( Address& a, int offset ) {
duke@435:   assert_not_delayed();
duke@435: #ifdef _LP64
duke@435:   sethi(a);
duke@435:   add(a, a.base(), offset);
duke@435: #else
duke@435:   if (a.hi() == 0 && a.rtype() == relocInfo::none) {
duke@435:     set(a.disp() + offset, a.base());
duke@435:   }
duke@435:   else {
duke@435:     sethi(a);
duke@435:     add(a, a.base(), offset);
duke@435:   }
duke@435: #endif
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::split_disp( Address& a, Register temp ) {
duke@435:   assert_not_delayed();
duke@435:   a = a.split_disp();
duke@435:   Assembler::sethi(a.hi(), temp, a.rspec());
duke@435:   add(a.base(), temp, a.base());
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) {
duke@435:   assert_not_delayed();
duke@435:   sethi(a);
duke@435:   ld(a, d, offset);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) {
duke@435:   assert_not_delayed();
duke@435:   sethi(a);
duke@435:   ld_ptr(a, d, offset);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) {
duke@435:   assert_not_delayed();
duke@435:   sethi(a);
duke@435:   st(s, a, offset);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) {
duke@435:   assert_not_delayed();
duke@435:   sethi(a);
duke@435:   st_ptr(s, a, offset);
duke@435: }
duke@435: 
duke@435: 
duke@435: // This code sequence is relocatable to any address, even on LP64.
duke@435: inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) {
duke@435:   assert_not_delayed();
duke@435:   // Force fixed length sethi because NativeJump and NativeFarCall don't handle
duke@435:   // variable length instruction streams.
duke@435:   sethi(a, /*ForceRelocatable=*/ true);
duke@435:   jmpl(a, d, offset);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::jump_to( Address& a, int offset ) {
duke@435:   jumpl_to( a, G0, offset );
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::set_oop( jobject obj, Register d ) {
duke@435:   set_oop(allocate_oop_address(obj, d));
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) {
duke@435:   set_oop(constant_oop_address(obj, d));
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::set_oop( Address obj_addr ) {
duke@435:   assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc");
duke@435:   load_address(obj_addr);
duke@435: }
duke@435: 
duke@435: 
duke@435: inline void MacroAssembler::load_argument( Argument& a, Register  d ) {
duke@435:   if (a.is_register())
duke@435:     mov(a.as_register(), d);
duke@435:   else
duke@435:     ld (a.as_address(),  d);
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::store_argument( Register s, Argument& a ) {
duke@435:   if (a.is_register())
duke@435:     mov(s, a.as_register());
duke@435:   else
duke@435:     st_ptr (s, a.as_address());         // ABI says everything is right justified.
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
duke@435:   if (a.is_register())
duke@435:     mov(s, a.as_register());
duke@435:   else
duke@435:     st_ptr (s, a.as_address());
duke@435: }
duke@435: 
duke@435: 
duke@435: #ifdef _LP64
duke@435: inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
duke@435:   if (a.is_float_register())
duke@435: // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
duke@435:     fmov(FloatRegisterImpl::S, s, a.as_float_register() );
duke@435:   else
duke@435:     // Floats are stored in the high half of the stack entry
duke@435:     // The low half is undefined per the ABI.
duke@435:     stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
duke@435:   if (a.is_float_register())
duke@435: // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
duke@435:     fmov(FloatRegisterImpl::D, s, a.as_double_register() );
duke@435:   else
duke@435:     stf(FloatRegisterImpl::D, s, a.as_address());
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
duke@435:   if (a.is_register())
duke@435:     mov(s, a.as_register());
duke@435:   else
duke@435:     stx(s, a.as_address());
duke@435: }
duke@435: #endif
duke@435: 
duke@435: inline void MacroAssembler::clrb( Register s1, Register s2) {  stb( G0, s1, s2 ); }
duke@435: inline void MacroAssembler::clrh( Register s1, Register s2) {  sth( G0, s1, s2 ); }
duke@435: inline void MacroAssembler::clr(  Register s1, Register s2) {  stw( G0, s1, s2 ); }
duke@435: inline void MacroAssembler::clrx( Register s1, Register s2) {  stx( G0, s1, s2 ); }
duke@435: 
duke@435: inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
duke@435: inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
duke@435: inline void MacroAssembler::clr(  Register s1, int simm13a) { stw( G0, s1, simm13a); }
duke@435: inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
duke@435: 
duke@435: // returns if membar generates anything, obviously this code should mirror
duke@435: // membar below.
duke@435: inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
duke@435:   if( !os::is_MP() ) return false;  // Not needed on single CPU
duke@435:   if( VM_Version::v9_instructions_work() ) {
duke@435:     const Membar_mask_bits effective_mask =
duke@435:         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
duke@435:     return (effective_mask != 0);
duke@435:   } else {
duke@435:     return true;
duke@435:   }
duke@435: }
duke@435: 
duke@435: inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
duke@435:   // Uniprocessors do not need memory barriers
duke@435:   if (!os::is_MP()) return;
duke@435:   // Weakened for current Sparcs and TSO.  See the v9 manual, sections 8.4.3,
duke@435:   // 8.4.4.3, a.31 and a.50.
duke@435:   if( VM_Version::v9_instructions_work() ) {
duke@435:     // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
duke@435:     // of the mmask subfield of const7a that does anything that isn't done
duke@435:     // implicitly is StoreLoad.
duke@435:     const Membar_mask_bits effective_mask =
duke@435:         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
duke@435:     if ( effective_mask != 0 ) {
duke@435:       Assembler::membar( effective_mask );
duke@435:     }
duke@435:   } else {
duke@435:     // stbar is the closest there is on v8.  Equivalent to membar(StoreStore).  We
duke@435:     // do not issue the stbar because to my knowledge all v8 machines implement TSO,
duke@435:     // which guarantees that all stores behave as if an stbar were issued just after
duke@435:     // each one of them.  On these machines, stbar ought to be a nop.  There doesn't
duke@435:     // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
duke@435:     // it can't be specified by stbar, nor have I come up with a way to simulate it.
duke@435:     //
duke@435:     // Addendum.  Dave says that ldstub guarantees a write buffer flush to coherent
duke@435:     // space.  Put one here to be on the safe side.
duke@435:     Assembler::ldstub(SP, 0, G0);
duke@435:   }
duke@435: }