Wed, 21 May 2008 13:46:23 -0700
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
Summary: Add LoadNKlass and CMoveN nodes, use CmpN and ConN nodes to generate narrow oops compare instructions.
Reviewed-by: never, rasbold
duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | class BiasedLockingCounters; |
duke@435 | 26 | |
duke@435 | 27 | // Contains all the definitions needed for amd64 assembly code generation. |
duke@435 | 28 | |
duke@435 | 29 | #ifdef _LP64 |
duke@435 | 30 | // Calling convention |
duke@435 | 31 | class Argument VALUE_OBJ_CLASS_SPEC { |
duke@435 | 32 | public: |
duke@435 | 33 | enum { |
duke@435 | 34 | #ifdef _WIN64 |
duke@435 | 35 | n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 36 | n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
duke@435 | 37 | #else |
duke@435 | 38 | n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 39 | n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
coleenp@548 | 40 | #endif // _WIN64 |
duke@435 | 41 | n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
duke@435 | 42 | n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
duke@435 | 43 | }; |
duke@435 | 44 | }; |
duke@435 | 45 | |
duke@435 | 46 | |
duke@435 | 47 | // Symbolically name the register arguments used by the c calling convention. |
duke@435 | 48 | // Windows is different from linux/solaris. So much for standards... |
duke@435 | 49 | |
duke@435 | 50 | #ifdef _WIN64 |
duke@435 | 51 | |
duke@435 | 52 | REGISTER_DECLARATION(Register, c_rarg0, rcx); |
duke@435 | 53 | REGISTER_DECLARATION(Register, c_rarg1, rdx); |
duke@435 | 54 | REGISTER_DECLARATION(Register, c_rarg2, r8); |
duke@435 | 55 | REGISTER_DECLARATION(Register, c_rarg3, r9); |
duke@435 | 56 | |
duke@435 | 57 | REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
duke@435 | 58 | REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
duke@435 | 59 | REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
duke@435 | 60 | REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
duke@435 | 61 | |
duke@435 | 62 | #else |
duke@435 | 63 | |
duke@435 | 64 | REGISTER_DECLARATION(Register, c_rarg0, rdi); |
duke@435 | 65 | REGISTER_DECLARATION(Register, c_rarg1, rsi); |
duke@435 | 66 | REGISTER_DECLARATION(Register, c_rarg2, rdx); |
duke@435 | 67 | REGISTER_DECLARATION(Register, c_rarg3, rcx); |
duke@435 | 68 | REGISTER_DECLARATION(Register, c_rarg4, r8); |
duke@435 | 69 | REGISTER_DECLARATION(Register, c_rarg5, r9); |
duke@435 | 70 | |
duke@435 | 71 | REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
duke@435 | 72 | REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
duke@435 | 73 | REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
duke@435 | 74 | REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
duke@435 | 75 | REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
duke@435 | 76 | REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
duke@435 | 77 | REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
duke@435 | 78 | REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
duke@435 | 79 | |
coleenp@548 | 80 | #endif // _WIN64 |
duke@435 | 81 | |
duke@435 | 82 | // Symbolically name the register arguments used by the Java calling convention. |
duke@435 | 83 | // We have control over the convention for java so we can do what we please. |
duke@435 | 84 | // What pleases us is to offset the java calling convention so that when |
duke@435 | 85 | // we call a suitable jni method the arguments are lined up and we don't |
duke@435 | 86 | // have to do little shuffling. A suitable jni method is non-static and a |
duke@435 | 87 | // small number of arguments (two fewer args on windows) |
duke@435 | 88 | // |
duke@435 | 89 | // |-------------------------------------------------------| |
duke@435 | 90 | // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
duke@435 | 91 | // |-------------------------------------------------------| |
duke@435 | 92 | // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
duke@435 | 93 | // | rdi rsi rdx rcx r8 r9 | solaris/linux |
duke@435 | 94 | // |-------------------------------------------------------| |
duke@435 | 95 | // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
duke@435 | 96 | // |-------------------------------------------------------| |
duke@435 | 97 | |
duke@435 | 98 | REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
duke@435 | 99 | REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
duke@435 | 100 | REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
duke@435 | 101 | // Windows runs out of register args here |
duke@435 | 102 | #ifdef _WIN64 |
duke@435 | 103 | REGISTER_DECLARATION(Register, j_rarg3, rdi); |
duke@435 | 104 | REGISTER_DECLARATION(Register, j_rarg4, rsi); |
duke@435 | 105 | #else |
duke@435 | 106 | REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
duke@435 | 107 | REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
coleenp@548 | 108 | #endif // _WIN64 |
duke@435 | 109 | REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
duke@435 | 110 | |
duke@435 | 111 | REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
duke@435 | 112 | REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
duke@435 | 113 | REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
duke@435 | 114 | REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
duke@435 | 115 | REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
duke@435 | 116 | REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
duke@435 | 117 | REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
duke@435 | 118 | REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
duke@435 | 119 | |
duke@435 | 120 | REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
duke@435 | 121 | REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
duke@435 | 122 | |
coleenp@548 | 123 | REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
coleenp@548 | 124 | REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
duke@435 | 125 | |
duke@435 | 126 | #endif // _LP64 |
duke@435 | 127 | |
duke@435 | 128 | // Address is an abstraction used to represent a memory location |
duke@435 | 129 | // using any of the amd64 addressing modes with one object. |
duke@435 | 130 | // |
duke@435 | 131 | // Note: A register location is represented via a Register, not |
duke@435 | 132 | // via an address for efficiency & simplicity reasons. |
duke@435 | 133 | |
duke@435 | 134 | class ArrayAddress; |
duke@435 | 135 | |
duke@435 | 136 | class Address VALUE_OBJ_CLASS_SPEC { |
duke@435 | 137 | public: |
duke@435 | 138 | enum ScaleFactor { |
duke@435 | 139 | no_scale = -1, |
duke@435 | 140 | times_1 = 0, |
duke@435 | 141 | times_2 = 1, |
duke@435 | 142 | times_4 = 2, |
duke@435 | 143 | times_8 = 3 |
duke@435 | 144 | }; |
duke@435 | 145 | |
duke@435 | 146 | private: |
duke@435 | 147 | Register _base; |
duke@435 | 148 | Register _index; |
duke@435 | 149 | ScaleFactor _scale; |
duke@435 | 150 | int _disp; |
duke@435 | 151 | RelocationHolder _rspec; |
duke@435 | 152 | |
duke@435 | 153 | // Easily misused constructors make them private |
duke@435 | 154 | Address(int disp, address loc, relocInfo::relocType rtype); |
duke@435 | 155 | Address(int disp, address loc, RelocationHolder spec); |
duke@435 | 156 | |
duke@435 | 157 | public: |
duke@435 | 158 | // creation |
duke@435 | 159 | Address() |
duke@435 | 160 | : _base(noreg), |
duke@435 | 161 | _index(noreg), |
duke@435 | 162 | _scale(no_scale), |
duke@435 | 163 | _disp(0) { |
duke@435 | 164 | } |
duke@435 | 165 | |
duke@435 | 166 | // No default displacement otherwise Register can be implicitly |
duke@435 | 167 | // converted to 0(Register) which is quite a different animal. |
duke@435 | 168 | |
duke@435 | 169 | Address(Register base, int disp) |
duke@435 | 170 | : _base(base), |
duke@435 | 171 | _index(noreg), |
duke@435 | 172 | _scale(no_scale), |
duke@435 | 173 | _disp(disp) { |
duke@435 | 174 | } |
duke@435 | 175 | |
duke@435 | 176 | Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
duke@435 | 177 | : _base (base), |
duke@435 | 178 | _index(index), |
duke@435 | 179 | _scale(scale), |
duke@435 | 180 | _disp (disp) { |
duke@435 | 181 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 182 | "inconsistent address"); |
duke@435 | 183 | } |
duke@435 | 184 | |
duke@435 | 185 | // The following two overloads are used in connection with the |
duke@435 | 186 | // ByteSize type (see sizes.hpp). They simplify the use of |
duke@435 | 187 | // ByteSize'd arguments in assembly code. Note that their equivalent |
duke@435 | 188 | // for the optimized build are the member functions with int disp |
duke@435 | 189 | // argument since ByteSize is mapped to an int type in that case. |
duke@435 | 190 | // |
duke@435 | 191 | // Note: DO NOT introduce similar overloaded functions for WordSize |
duke@435 | 192 | // arguments as in the optimized mode, both ByteSize and WordSize |
duke@435 | 193 | // are mapped to the same type and thus the compiler cannot make a |
duke@435 | 194 | // distinction anymore (=> compiler errors). |
duke@435 | 195 | |
duke@435 | 196 | #ifdef ASSERT |
duke@435 | 197 | Address(Register base, ByteSize disp) |
duke@435 | 198 | : _base(base), |
duke@435 | 199 | _index(noreg), |
duke@435 | 200 | _scale(no_scale), |
duke@435 | 201 | _disp(in_bytes(disp)) { |
duke@435 | 202 | } |
duke@435 | 203 | |
duke@435 | 204 | Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
duke@435 | 205 | : _base(base), |
duke@435 | 206 | _index(index), |
duke@435 | 207 | _scale(scale), |
duke@435 | 208 | _disp(in_bytes(disp)) { |
duke@435 | 209 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 210 | "inconsistent address"); |
duke@435 | 211 | } |
duke@435 | 212 | #endif // ASSERT |
duke@435 | 213 | |
duke@435 | 214 | // accessors |
duke@435 | 215 | bool uses(Register reg) const { |
duke@435 | 216 | return _base == reg || _index == reg; |
duke@435 | 217 | } |
duke@435 | 218 | |
duke@435 | 219 | // Convert the raw encoding form into the form expected by the constructor for |
duke@435 | 220 | // Address. An index of 4 (rsp) corresponds to having no index, so convert |
duke@435 | 221 | // that to noreg for the Address constructor. |
duke@435 | 222 | static Address make_raw(int base, int index, int scale, int disp); |
duke@435 | 223 | |
duke@435 | 224 | static Address make_array(ArrayAddress); |
duke@435 | 225 | |
duke@435 | 226 | private: |
duke@435 | 227 | bool base_needs_rex() const { |
duke@435 | 228 | return _base != noreg && _base->encoding() >= 8; |
duke@435 | 229 | } |
duke@435 | 230 | |
duke@435 | 231 | bool index_needs_rex() const { |
duke@435 | 232 | return _index != noreg &&_index->encoding() >= 8; |
duke@435 | 233 | } |
duke@435 | 234 | |
duke@435 | 235 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 236 | |
duke@435 | 237 | friend class Assembler; |
duke@435 | 238 | friend class MacroAssembler; |
duke@435 | 239 | friend class LIR_Assembler; // base/index/scale/disp |
duke@435 | 240 | }; |
duke@435 | 241 | |
duke@435 | 242 | // |
duke@435 | 243 | // AddressLiteral has been split out from Address because operands of this type |
duke@435 | 244 | // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
duke@435 | 245 | // the few instructions that need to deal with address literals are unique and the |
duke@435 | 246 | // MacroAssembler does not have to implement every instruction in the Assembler |
duke@435 | 247 | // in order to search for address literals that may need special handling depending |
duke@435 | 248 | // on the instruction and the platform. As small step on the way to merging i486/amd64 |
duke@435 | 249 | // directories. |
duke@435 | 250 | // |
duke@435 | 251 | class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
duke@435 | 252 | friend class ArrayAddress; |
duke@435 | 253 | RelocationHolder _rspec; |
duke@435 | 254 | // Typically we use AddressLiterals we want to use their rval |
duke@435 | 255 | // However in some situations we want the lval (effect address) of the item. |
duke@435 | 256 | // We provide a special factory for making those lvals. |
duke@435 | 257 | bool _is_lval; |
duke@435 | 258 | |
duke@435 | 259 | // If the target is far we'll need to load the ea of this to |
duke@435 | 260 | // a register to reach it. Otherwise if near we can do rip |
duke@435 | 261 | // relative addressing. |
duke@435 | 262 | |
duke@435 | 263 | address _target; |
duke@435 | 264 | |
duke@435 | 265 | protected: |
duke@435 | 266 | // creation |
duke@435 | 267 | AddressLiteral() |
duke@435 | 268 | : _is_lval(false), |
duke@435 | 269 | _target(NULL) |
duke@435 | 270 | {} |
duke@435 | 271 | |
duke@435 | 272 | public: |
duke@435 | 273 | |
duke@435 | 274 | |
duke@435 | 275 | AddressLiteral(address target, relocInfo::relocType rtype); |
duke@435 | 276 | |
duke@435 | 277 | AddressLiteral(address target, RelocationHolder const& rspec) |
duke@435 | 278 | : _rspec(rspec), |
duke@435 | 279 | _is_lval(false), |
duke@435 | 280 | _target(target) |
duke@435 | 281 | {} |
duke@435 | 282 | |
duke@435 | 283 | AddressLiteral addr() { |
duke@435 | 284 | AddressLiteral ret = *this; |
duke@435 | 285 | ret._is_lval = true; |
duke@435 | 286 | return ret; |
duke@435 | 287 | } |
duke@435 | 288 | |
duke@435 | 289 | |
duke@435 | 290 | private: |
duke@435 | 291 | |
duke@435 | 292 | address target() { return _target; } |
duke@435 | 293 | bool is_lval() { return _is_lval; } |
duke@435 | 294 | |
duke@435 | 295 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 296 | const RelocationHolder& rspec() const { return _rspec; } |
duke@435 | 297 | |
duke@435 | 298 | friend class Assembler; |
duke@435 | 299 | friend class MacroAssembler; |
duke@435 | 300 | friend class Address; |
duke@435 | 301 | friend class LIR_Assembler; |
duke@435 | 302 | }; |
duke@435 | 303 | |
duke@435 | 304 | // Convience classes |
duke@435 | 305 | class RuntimeAddress: public AddressLiteral { |
duke@435 | 306 | |
duke@435 | 307 | public: |
duke@435 | 308 | |
duke@435 | 309 | RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
duke@435 | 310 | |
duke@435 | 311 | }; |
duke@435 | 312 | |
duke@435 | 313 | class OopAddress: public AddressLiteral { |
duke@435 | 314 | |
duke@435 | 315 | public: |
duke@435 | 316 | |
duke@435 | 317 | OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} |
duke@435 | 318 | |
duke@435 | 319 | }; |
duke@435 | 320 | |
duke@435 | 321 | class ExternalAddress: public AddressLiteral { |
duke@435 | 322 | |
duke@435 | 323 | public: |
duke@435 | 324 | |
duke@435 | 325 | ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} |
duke@435 | 326 | |
duke@435 | 327 | }; |
duke@435 | 328 | |
duke@435 | 329 | class InternalAddress: public AddressLiteral { |
duke@435 | 330 | |
duke@435 | 331 | public: |
duke@435 | 332 | |
duke@435 | 333 | InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
duke@435 | 334 | |
duke@435 | 335 | }; |
duke@435 | 336 | |
duke@435 | 337 | // x86 can do array addressing as a single operation since disp can be an absolute |
duke@435 | 338 | // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class |
duke@435 | 339 | // that expresses the concept but does extra magic on amd64 to get the final result |
duke@435 | 340 | |
duke@435 | 341 | class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
duke@435 | 342 | private: |
duke@435 | 343 | |
duke@435 | 344 | AddressLiteral _base; |
duke@435 | 345 | Address _index; |
duke@435 | 346 | |
duke@435 | 347 | public: |
duke@435 | 348 | |
duke@435 | 349 | ArrayAddress() {}; |
duke@435 | 350 | ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
duke@435 | 351 | AddressLiteral base() { return _base; } |
duke@435 | 352 | Address index() { return _index; } |
duke@435 | 353 | |
duke@435 | 354 | }; |
duke@435 | 355 | |
duke@435 | 356 | // The amd64 Assembler: Pure assembler doing NO optimizations on |
duke@435 | 357 | // the instruction level (e.g. mov rax, 0 is not translated into xor |
duke@435 | 358 | // rax, rax!); i.e., what you write is what you get. The Assembler is |
duke@435 | 359 | // generating code into a CodeBuffer. |
duke@435 | 360 | |
duke@435 | 361 | const int FPUStateSizeInWords = 512 / wordSize; |
duke@435 | 362 | |
duke@435 | 363 | class Assembler : public AbstractAssembler { |
duke@435 | 364 | friend class AbstractAssembler; // for the non-virtual hack |
duke@435 | 365 | friend class StubGenerator; |
duke@435 | 366 | |
duke@435 | 367 | |
duke@435 | 368 | protected: |
duke@435 | 369 | #ifdef ASSERT |
duke@435 | 370 | void check_relocation(RelocationHolder const& rspec, int format); |
duke@435 | 371 | #endif |
duke@435 | 372 | |
duke@435 | 373 | inline void emit_long64(jlong x); |
duke@435 | 374 | |
duke@435 | 375 | void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */); |
duke@435 | 376 | void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */); |
duke@435 | 377 | void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
duke@435 | 378 | void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
duke@435 | 379 | |
duke@435 | 380 | // Helper functions for groups of instructions |
duke@435 | 381 | void emit_arith_b(int op1, int op2, Register dst, int imm8); |
duke@435 | 382 | |
duke@435 | 383 | void emit_arith(int op1, int op2, Register dst, int imm32); |
duke@435 | 384 | // only x86?? |
duke@435 | 385 | void emit_arith(int op1, int op2, Register dst, jobject obj); |
duke@435 | 386 | void emit_arith(int op1, int op2, Register dst, Register src); |
duke@435 | 387 | |
duke@435 | 388 | void emit_operand(Register reg, |
duke@435 | 389 | Register base, Register index, Address::ScaleFactor scale, |
duke@435 | 390 | int disp, |
duke@435 | 391 | RelocationHolder const& rspec, |
duke@435 | 392 | int rip_relative_correction = 0); |
duke@435 | 393 | void emit_operand(Register reg, Address adr, |
duke@435 | 394 | int rip_relative_correction = 0); |
duke@435 | 395 | void emit_operand(XMMRegister reg, |
duke@435 | 396 | Register base, Register index, Address::ScaleFactor scale, |
duke@435 | 397 | int disp, |
duke@435 | 398 | RelocationHolder const& rspec, |
duke@435 | 399 | int rip_relative_correction = 0); |
duke@435 | 400 | void emit_operand(XMMRegister reg, Address adr, |
duke@435 | 401 | int rip_relative_correction = 0); |
duke@435 | 402 | |
duke@435 | 403 | // Immediate-to-memory forms |
duke@435 | 404 | void emit_arith_operand(int op1, Register rm, Address adr, int imm32); |
duke@435 | 405 | |
duke@435 | 406 | void emit_farith(int b1, int b2, int i); |
duke@435 | 407 | |
duke@435 | 408 | bool reachable(AddressLiteral adr); |
duke@435 | 409 | |
duke@435 | 410 | // These are all easily abused and hence protected |
duke@435 | 411 | |
duke@435 | 412 | // Make these disappear in 64bit mode since they would never be correct |
duke@435 | 413 | #ifndef _LP64 |
duke@435 | 414 | void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 415 | void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 416 | |
duke@435 | 417 | void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 418 | void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 419 | |
duke@435 | 420 | void push_literal32(int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 421 | #endif // _LP64 |
duke@435 | 422 | |
duke@435 | 423 | |
duke@435 | 424 | void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); |
duke@435 | 425 | |
duke@435 | 426 | // These are unique in that we are ensured by the caller that the 32bit |
duke@435 | 427 | // relative in these instructions will always be able to reach the potentially |
duke@435 | 428 | // 64bit address described by entry. Since they can take a 64bit address they |
duke@435 | 429 | // don't have the 32 suffix like the other instructions in this class. |
duke@435 | 430 | void jmp_literal(address entry, RelocationHolder const& rspec); |
duke@435 | 431 | void call_literal(address entry, RelocationHolder const& rspec); |
duke@435 | 432 | |
duke@435 | 433 | public: |
duke@435 | 434 | enum Condition { // The amd64 condition codes used for conditional jumps/moves. |
duke@435 | 435 | zero = 0x4, |
duke@435 | 436 | notZero = 0x5, |
duke@435 | 437 | equal = 0x4, |
duke@435 | 438 | notEqual = 0x5, |
duke@435 | 439 | less = 0xc, |
duke@435 | 440 | lessEqual = 0xe, |
duke@435 | 441 | greater = 0xf, |
duke@435 | 442 | greaterEqual = 0xd, |
duke@435 | 443 | below = 0x2, |
duke@435 | 444 | belowEqual = 0x6, |
duke@435 | 445 | above = 0x7, |
duke@435 | 446 | aboveEqual = 0x3, |
duke@435 | 447 | overflow = 0x0, |
duke@435 | 448 | noOverflow = 0x1, |
duke@435 | 449 | carrySet = 0x2, |
duke@435 | 450 | carryClear = 0x3, |
duke@435 | 451 | negative = 0x8, |
duke@435 | 452 | positive = 0x9, |
duke@435 | 453 | parity = 0xa, |
duke@435 | 454 | noParity = 0xb |
duke@435 | 455 | }; |
duke@435 | 456 | |
duke@435 | 457 | enum Prefix { |
duke@435 | 458 | // segment overrides |
duke@435 | 459 | // XXX remove segment prefixes |
duke@435 | 460 | CS_segment = 0x2e, |
duke@435 | 461 | SS_segment = 0x36, |
duke@435 | 462 | DS_segment = 0x3e, |
duke@435 | 463 | ES_segment = 0x26, |
duke@435 | 464 | FS_segment = 0x64, |
duke@435 | 465 | GS_segment = 0x65, |
duke@435 | 466 | |
duke@435 | 467 | REX = 0x40, |
duke@435 | 468 | |
duke@435 | 469 | REX_B = 0x41, |
duke@435 | 470 | REX_X = 0x42, |
duke@435 | 471 | REX_XB = 0x43, |
duke@435 | 472 | REX_R = 0x44, |
duke@435 | 473 | REX_RB = 0x45, |
duke@435 | 474 | REX_RX = 0x46, |
duke@435 | 475 | REX_RXB = 0x47, |
duke@435 | 476 | |
duke@435 | 477 | REX_W = 0x48, |
duke@435 | 478 | |
duke@435 | 479 | REX_WB = 0x49, |
duke@435 | 480 | REX_WX = 0x4A, |
duke@435 | 481 | REX_WXB = 0x4B, |
duke@435 | 482 | REX_WR = 0x4C, |
duke@435 | 483 | REX_WRB = 0x4D, |
duke@435 | 484 | REX_WRX = 0x4E, |
duke@435 | 485 | REX_WRXB = 0x4F |
duke@435 | 486 | }; |
duke@435 | 487 | |
duke@435 | 488 | enum WhichOperand { |
duke@435 | 489 | // input to locate_operand, and format code for relocations |
duke@435 | 490 | imm64_operand = 0, // embedded 64-bit immediate operand |
duke@435 | 491 | disp32_operand = 1, // embedded 32-bit displacement |
duke@435 | 492 | call32_operand = 2, // embedded 32-bit self-relative displacement |
kvn@599 | 493 | #ifndef AMD64 |
duke@435 | 494 | _WhichOperand_limit = 3 |
kvn@599 | 495 | #else |
kvn@599 | 496 | narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
kvn@599 | 497 | _WhichOperand_limit = 4 |
kvn@599 | 498 | #endif |
duke@435 | 499 | }; |
duke@435 | 500 | |
duke@435 | 501 | public: |
duke@435 | 502 | |
duke@435 | 503 | // Creation |
duke@435 | 504 | Assembler(CodeBuffer* code) |
duke@435 | 505 | : AbstractAssembler(code) { |
duke@435 | 506 | } |
duke@435 | 507 | |
duke@435 | 508 | // Decoding |
duke@435 | 509 | static address locate_operand(address inst, WhichOperand which); |
duke@435 | 510 | static address locate_next_instruction(address inst); |
duke@435 | 511 | |
duke@435 | 512 | // Utilities |
duke@435 | 513 | |
duke@435 | 514 | static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } |
duke@435 | 515 | static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; } |
duke@435 | 516 | |
duke@435 | 517 | |
duke@435 | 518 | // Stack |
duke@435 | 519 | void pushaq(); |
duke@435 | 520 | void popaq(); |
duke@435 | 521 | |
duke@435 | 522 | void pushfq(); |
duke@435 | 523 | void popfq(); |
duke@435 | 524 | |
duke@435 | 525 | void pushq(int imm32); |
duke@435 | 526 | |
duke@435 | 527 | void pushq(Register src); |
duke@435 | 528 | void pushq(Address src); |
duke@435 | 529 | |
duke@435 | 530 | void popq(Register dst); |
duke@435 | 531 | void popq(Address dst); |
duke@435 | 532 | |
duke@435 | 533 | // Instruction prefixes |
duke@435 | 534 | void prefix(Prefix p); |
duke@435 | 535 | |
duke@435 | 536 | int prefix_and_encode(int reg_enc, bool byteinst = false); |
duke@435 | 537 | int prefixq_and_encode(int reg_enc); |
duke@435 | 538 | |
duke@435 | 539 | int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); |
duke@435 | 540 | int prefixq_and_encode(int dst_enc, int src_enc); |
duke@435 | 541 | |
duke@435 | 542 | void prefix(Register reg); |
duke@435 | 543 | void prefix(Address adr); |
duke@435 | 544 | void prefixq(Address adr); |
duke@435 | 545 | |
duke@435 | 546 | void prefix(Address adr, Register reg, bool byteinst = false); |
duke@435 | 547 | void prefixq(Address adr, Register reg); |
duke@435 | 548 | |
duke@435 | 549 | void prefix(Address adr, XMMRegister reg); |
duke@435 | 550 | |
duke@435 | 551 | // Moves |
duke@435 | 552 | void movb(Register dst, Address src); |
duke@435 | 553 | void movb(Address dst, int imm8); |
duke@435 | 554 | void movb(Address dst, Register src); |
duke@435 | 555 | |
duke@435 | 556 | void movw(Address dst, int imm16); |
duke@435 | 557 | void movw(Register dst, Address src); |
duke@435 | 558 | void movw(Address dst, Register src); |
duke@435 | 559 | |
duke@435 | 560 | void movl(Register dst, int imm32); |
duke@435 | 561 | void movl(Register dst, Register src); |
duke@435 | 562 | void movl(Register dst, Address src); |
duke@435 | 563 | void movl(Address dst, int imm32); |
duke@435 | 564 | void movl(Address dst, Register src); |
duke@435 | 565 | |
duke@435 | 566 | void movq(Register dst, Register src); |
duke@435 | 567 | void movq(Register dst, Address src); |
duke@435 | 568 | void movq(Address dst, Register src); |
duke@435 | 569 | // These prevent using movq from converting a zero (like NULL) into Register |
duke@435 | 570 | // by giving the compiler two choices it can't resolve |
duke@435 | 571 | void movq(Address dst, void* dummy); |
duke@435 | 572 | void movq(Register dst, void* dummy); |
duke@435 | 573 | |
duke@435 | 574 | void mov64(Register dst, intptr_t imm64); |
duke@435 | 575 | void mov64(Address dst, intptr_t imm64); |
duke@435 | 576 | |
duke@435 | 577 | void movsbl(Register dst, Address src); |
duke@435 | 578 | void movsbl(Register dst, Register src); |
duke@435 | 579 | void movswl(Register dst, Address src); |
duke@435 | 580 | void movswl(Register dst, Register src); |
duke@435 | 581 | void movslq(Register dst, Address src); |
duke@435 | 582 | void movslq(Register dst, Register src); |
duke@435 | 583 | |
duke@435 | 584 | void movzbl(Register dst, Address src); |
duke@435 | 585 | void movzbl(Register dst, Register src); |
duke@435 | 586 | void movzwl(Register dst, Address src); |
duke@435 | 587 | void movzwl(Register dst, Register src); |
duke@435 | 588 | |
duke@435 | 589 | protected: // Avoid using the next instructions directly. |
duke@435 | 590 | // New cpus require use of movsd and movss to avoid partial register stall |
duke@435 | 591 | // when loading from memory. But for old Opteron use movlpd instead of movsd. |
duke@435 | 592 | // The selection is done in MacroAssembler::movdbl() and movflt(). |
duke@435 | 593 | void movss(XMMRegister dst, XMMRegister src); |
duke@435 | 594 | void movss(XMMRegister dst, Address src); |
duke@435 | 595 | void movss(Address dst, XMMRegister src); |
duke@435 | 596 | void movsd(XMMRegister dst, XMMRegister src); |
duke@435 | 597 | void movsd(Address dst, XMMRegister src); |
duke@435 | 598 | void movsd(XMMRegister dst, Address src); |
duke@435 | 599 | void movlpd(XMMRegister dst, Address src); |
duke@435 | 600 | // New cpus require use of movaps and movapd to avoid partial register stall |
duke@435 | 601 | // when moving between registers. |
duke@435 | 602 | void movapd(XMMRegister dst, XMMRegister src); |
duke@435 | 603 | void movaps(XMMRegister dst, XMMRegister src); |
duke@435 | 604 | public: |
duke@435 | 605 | |
duke@435 | 606 | void movdl(XMMRegister dst, Register src); |
duke@435 | 607 | void movdl(Register dst, XMMRegister src); |
duke@435 | 608 | void movdq(XMMRegister dst, Register src); |
duke@435 | 609 | void movdq(Register dst, XMMRegister src); |
duke@435 | 610 | |
duke@435 | 611 | void cmovl(Condition cc, Register dst, Register src); |
duke@435 | 612 | void cmovl(Condition cc, Register dst, Address src); |
duke@435 | 613 | void cmovq(Condition cc, Register dst, Register src); |
duke@435 | 614 | void cmovq(Condition cc, Register dst, Address src); |
duke@435 | 615 | |
duke@435 | 616 | // Prefetches |
duke@435 | 617 | private: |
duke@435 | 618 | void prefetch_prefix(Address src); |
duke@435 | 619 | public: |
duke@435 | 620 | void prefetcht0(Address src); |
duke@435 | 621 | void prefetcht1(Address src); |
duke@435 | 622 | void prefetcht2(Address src); |
duke@435 | 623 | void prefetchnta(Address src); |
duke@435 | 624 | void prefetchw(Address src); |
duke@435 | 625 | |
duke@435 | 626 | // Arithmetics |
duke@435 | 627 | void adcl(Register dst, int imm32); |
duke@435 | 628 | void adcl(Register dst, Address src); |
duke@435 | 629 | void adcl(Register dst, Register src); |
duke@435 | 630 | void adcq(Register dst, int imm32); |
duke@435 | 631 | void adcq(Register dst, Address src); |
duke@435 | 632 | void adcq(Register dst, Register src); |
duke@435 | 633 | |
duke@435 | 634 | void addl(Address dst, int imm32); |
duke@435 | 635 | void addl(Address dst, Register src); |
duke@435 | 636 | void addl(Register dst, int imm32); |
duke@435 | 637 | void addl(Register dst, Address src); |
duke@435 | 638 | void addl(Register dst, Register src); |
duke@435 | 639 | void addq(Address dst, int imm32); |
duke@435 | 640 | void addq(Address dst, Register src); |
duke@435 | 641 | void addq(Register dst, int imm32); |
duke@435 | 642 | void addq(Register dst, Address src); |
duke@435 | 643 | void addq(Register dst, Register src); |
duke@435 | 644 | |
duke@435 | 645 | void andl(Register dst, int imm32); |
duke@435 | 646 | void andl(Register dst, Address src); |
duke@435 | 647 | void andl(Register dst, Register src); |
duke@435 | 648 | void andq(Register dst, int imm32); |
duke@435 | 649 | void andq(Register dst, Address src); |
duke@435 | 650 | void andq(Register dst, Register src); |
duke@435 | 651 | |
duke@435 | 652 | void cmpb(Address dst, int imm8); |
duke@435 | 653 | void cmpl(Address dst, int imm32); |
duke@435 | 654 | void cmpl(Register dst, int imm32); |
duke@435 | 655 | void cmpl(Register dst, Register src); |
duke@435 | 656 | void cmpl(Register dst, Address src); |
duke@435 | 657 | void cmpq(Address dst, int imm32); |
duke@435 | 658 | void cmpq(Address dst, Register src); |
duke@435 | 659 | void cmpq(Register dst, int imm32); |
duke@435 | 660 | void cmpq(Register dst, Register src); |
duke@435 | 661 | void cmpq(Register dst, Address src); |
duke@435 | 662 | |
duke@435 | 663 | void ucomiss(XMMRegister dst, XMMRegister src); |
duke@435 | 664 | void ucomisd(XMMRegister dst, XMMRegister src); |
duke@435 | 665 | |
duke@435 | 666 | protected: |
duke@435 | 667 | // Don't use next inc() and dec() methods directly. INC & DEC instructions |
duke@435 | 668 | // could cause a partial flag stall since they don't set CF flag. |
duke@435 | 669 | // Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
duke@435 | 670 | // which call inc() & dec() or add() & sub() in accordance with |
duke@435 | 671 | // the product flag UseIncDec value. |
duke@435 | 672 | |
duke@435 | 673 | void decl(Register dst); |
duke@435 | 674 | void decl(Address dst); |
duke@435 | 675 | void decq(Register dst); |
duke@435 | 676 | void decq(Address dst); |
duke@435 | 677 | |
duke@435 | 678 | void incl(Register dst); |
duke@435 | 679 | void incl(Address dst); |
duke@435 | 680 | void incq(Register dst); |
duke@435 | 681 | void incq(Address dst); |
duke@435 | 682 | |
duke@435 | 683 | public: |
duke@435 | 684 | void idivl(Register src); |
duke@435 | 685 | void idivq(Register src); |
duke@435 | 686 | void cdql(); |
duke@435 | 687 | void cdqq(); |
duke@435 | 688 | |
duke@435 | 689 | void imull(Register dst, Register src); |
duke@435 | 690 | void imull(Register dst, Register src, int value); |
duke@435 | 691 | void imulq(Register dst, Register src); |
duke@435 | 692 | void imulq(Register dst, Register src, int value); |
duke@435 | 693 | |
duke@435 | 694 | void leal(Register dst, Address src); |
duke@435 | 695 | void leaq(Register dst, Address src); |
duke@435 | 696 | |
duke@435 | 697 | void mull(Address src); |
duke@435 | 698 | void mull(Register src); |
duke@435 | 699 | |
duke@435 | 700 | void negl(Register dst); |
duke@435 | 701 | void negq(Register dst); |
duke@435 | 702 | |
duke@435 | 703 | void notl(Register dst); |
duke@435 | 704 | void notq(Register dst); |
duke@435 | 705 | |
duke@435 | 706 | void orl(Address dst, int imm32); |
duke@435 | 707 | void orl(Register dst, int imm32); |
duke@435 | 708 | void orl(Register dst, Address src); |
duke@435 | 709 | void orl(Register dst, Register src); |
duke@435 | 710 | void orq(Address dst, int imm32); |
duke@435 | 711 | void orq(Register dst, int imm32); |
duke@435 | 712 | void orq(Register dst, Address src); |
duke@435 | 713 | void orq(Register dst, Register src); |
duke@435 | 714 | |
duke@435 | 715 | void rcll(Register dst, int imm8); |
duke@435 | 716 | void rclq(Register dst, int imm8); |
duke@435 | 717 | |
duke@435 | 718 | void sarl(Register dst, int imm8); |
duke@435 | 719 | void sarl(Register dst); |
duke@435 | 720 | void sarq(Register dst, int imm8); |
duke@435 | 721 | void sarq(Register dst); |
duke@435 | 722 | |
duke@435 | 723 | void sbbl(Address dst, int imm32); |
duke@435 | 724 | void sbbl(Register dst, int imm32); |
duke@435 | 725 | void sbbl(Register dst, Address src); |
duke@435 | 726 | void sbbl(Register dst, Register src); |
duke@435 | 727 | void sbbq(Address dst, int imm32); |
duke@435 | 728 | void sbbq(Register dst, int imm32); |
duke@435 | 729 | void sbbq(Register dst, Address src); |
duke@435 | 730 | void sbbq(Register dst, Register src); |
duke@435 | 731 | |
duke@435 | 732 | void shll(Register dst, int imm8); |
duke@435 | 733 | void shll(Register dst); |
duke@435 | 734 | void shlq(Register dst, int imm8); |
duke@435 | 735 | void shlq(Register dst); |
duke@435 | 736 | |
duke@435 | 737 | void shrl(Register dst, int imm8); |
duke@435 | 738 | void shrl(Register dst); |
duke@435 | 739 | void shrq(Register dst, int imm8); |
duke@435 | 740 | void shrq(Register dst); |
duke@435 | 741 | |
duke@435 | 742 | void subl(Address dst, int imm32); |
duke@435 | 743 | void subl(Address dst, Register src); |
duke@435 | 744 | void subl(Register dst, int imm32); |
duke@435 | 745 | void subl(Register dst, Address src); |
duke@435 | 746 | void subl(Register dst, Register src); |
duke@435 | 747 | void subq(Address dst, int imm32); |
duke@435 | 748 | void subq(Address dst, Register src); |
duke@435 | 749 | void subq(Register dst, int imm32); |
duke@435 | 750 | void subq(Register dst, Address src); |
duke@435 | 751 | void subq(Register dst, Register src); |
duke@435 | 752 | |
duke@435 | 753 | void testb(Register dst, int imm8); |
duke@435 | 754 | void testl(Register dst, int imm32); |
duke@435 | 755 | void testl(Register dst, Register src); |
duke@435 | 756 | void testq(Register dst, int imm32); |
duke@435 | 757 | void testq(Register dst, Register src); |
duke@435 | 758 | |
duke@435 | 759 | void xaddl(Address dst, Register src); |
duke@435 | 760 | void xaddq(Address dst, Register src); |
duke@435 | 761 | |
duke@435 | 762 | void xorl(Register dst, int imm32); |
duke@435 | 763 | void xorl(Register dst, Address src); |
duke@435 | 764 | void xorl(Register dst, Register src); |
duke@435 | 765 | void xorq(Register dst, int imm32); |
duke@435 | 766 | void xorq(Register dst, Address src); |
duke@435 | 767 | void xorq(Register dst, Register src); |
duke@435 | 768 | |
duke@435 | 769 | // Miscellaneous |
duke@435 | 770 | void bswapl(Register reg); |
duke@435 | 771 | void bswapq(Register reg); |
duke@435 | 772 | void lock(); |
duke@435 | 773 | |
duke@435 | 774 | void xchgl(Register reg, Address adr); |
duke@435 | 775 | void xchgl(Register dst, Register src); |
duke@435 | 776 | void xchgq(Register reg, Address adr); |
duke@435 | 777 | void xchgq(Register dst, Register src); |
duke@435 | 778 | |
duke@435 | 779 | void cmpxchgl(Register reg, Address adr); |
duke@435 | 780 | void cmpxchgq(Register reg, Address adr); |
duke@435 | 781 | |
duke@435 | 782 | void nop(int i = 1); |
duke@435 | 783 | void addr_nop_4(); |
duke@435 | 784 | void addr_nop_5(); |
duke@435 | 785 | void addr_nop_7(); |
duke@435 | 786 | void addr_nop_8(); |
duke@435 | 787 | |
duke@435 | 788 | void hlt(); |
duke@435 | 789 | void ret(int imm16); |
duke@435 | 790 | void smovl(); |
duke@435 | 791 | void rep_movl(); |
duke@435 | 792 | void rep_movq(); |
duke@435 | 793 | void rep_set(); |
coleenp@548 | 794 | void repne_scanl(); |
coleenp@548 | 795 | void repne_scanq(); |
duke@435 | 796 | void setb(Condition cc, Register dst); |
duke@435 | 797 | |
duke@435 | 798 | void clflush(Address adr); |
duke@435 | 799 | |
duke@435 | 800 | enum Membar_mask_bits { |
duke@435 | 801 | StoreStore = 1 << 3, |
duke@435 | 802 | LoadStore = 1 << 2, |
duke@435 | 803 | StoreLoad = 1 << 1, |
duke@435 | 804 | LoadLoad = 1 << 0 |
duke@435 | 805 | }; |
duke@435 | 806 | |
duke@435 | 807 | // Serializes memory. |
duke@435 | 808 | void membar(Membar_mask_bits order_constraint) { |
duke@435 | 809 | // We only have to handle StoreLoad and LoadLoad |
duke@435 | 810 | if (order_constraint & StoreLoad) { |
duke@435 | 811 | // MFENCE subsumes LFENCE |
duke@435 | 812 | mfence(); |
duke@435 | 813 | } /* [jk] not needed currently: else if (order_constraint & LoadLoad) { |
duke@435 | 814 | lfence(); |
duke@435 | 815 | } */ |
duke@435 | 816 | } |
duke@435 | 817 | |
duke@435 | 818 | void lfence() { |
duke@435 | 819 | emit_byte(0x0F); |
duke@435 | 820 | emit_byte(0xAE); |
duke@435 | 821 | emit_byte(0xE8); |
duke@435 | 822 | } |
duke@435 | 823 | |
duke@435 | 824 | void mfence() { |
duke@435 | 825 | emit_byte(0x0F); |
duke@435 | 826 | emit_byte(0xAE); |
duke@435 | 827 | emit_byte(0xF0); |
duke@435 | 828 | } |
duke@435 | 829 | |
duke@435 | 830 | // Identify processor type and features |
duke@435 | 831 | void cpuid() { |
duke@435 | 832 | emit_byte(0x0F); |
duke@435 | 833 | emit_byte(0xA2); |
duke@435 | 834 | } |
duke@435 | 835 | |
duke@435 | 836 | void cld() { emit_byte(0xfc); |
duke@435 | 837 | } |
duke@435 | 838 | |
duke@435 | 839 | void std() { emit_byte(0xfd); |
duke@435 | 840 | } |
duke@435 | 841 | |
duke@435 | 842 | |
duke@435 | 843 | // Calls |
duke@435 | 844 | |
duke@435 | 845 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 846 | void call(Register reg); |
duke@435 | 847 | void call(Address adr); |
duke@435 | 848 | |
duke@435 | 849 | // Jumps |
duke@435 | 850 | |
duke@435 | 851 | void jmp(Register reg); |
duke@435 | 852 | void jmp(Address adr); |
duke@435 | 853 | |
duke@435 | 854 | // Label operations & relative jumps (PPUM Appendix D) |
duke@435 | 855 | // unconditional jump to L |
duke@435 | 856 | void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); |
duke@435 | 857 | |
duke@435 | 858 | |
duke@435 | 859 | // Unconditional 8-bit offset jump to L. |
duke@435 | 860 | // WARNING: be very careful using this for forward jumps. If the label is |
duke@435 | 861 | // not bound within an 8-bit offset of this instruction, a run-time error |
duke@435 | 862 | // will occur. |
duke@435 | 863 | void jmpb(Label& L); |
duke@435 | 864 | |
duke@435 | 865 | // jcc is the generic conditional branch generator to run- time |
duke@435 | 866 | // routines, jcc is used for branches to labels. jcc takes a branch |
duke@435 | 867 | // opcode (cc) and a label (L) and generates either a backward |
duke@435 | 868 | // branch or a forward branch and links it to the label fixup |
duke@435 | 869 | // chain. Usage: |
duke@435 | 870 | // |
duke@435 | 871 | // Label L; // unbound label |
duke@435 | 872 | // jcc(cc, L); // forward branch to unbound label |
duke@435 | 873 | // bind(L); // bind label to the current pc |
duke@435 | 874 | // jcc(cc, L); // backward branch to bound label |
duke@435 | 875 | // bind(L); // illegal: a label may be bound only once |
duke@435 | 876 | // |
duke@435 | 877 | // Note: The same Label can be used for forward and backward branches |
duke@435 | 878 | // but it may be bound only once. |
duke@435 | 879 | |
duke@435 | 880 | void jcc(Condition cc, Label& L, |
duke@435 | 881 | relocInfo::relocType rtype = relocInfo::none); |
duke@435 | 882 | |
duke@435 | 883 | // Conditional jump to a 8-bit offset to L. |
duke@435 | 884 | // WARNING: be very careful using this for forward jumps. If the label is |
duke@435 | 885 | // not bound within an 8-bit offset of this instruction, a run-time error |
duke@435 | 886 | // will occur. |
duke@435 | 887 | void jccb(Condition cc, Label& L); |
duke@435 | 888 | |
duke@435 | 889 | // Floating-point operations |
duke@435 | 890 | |
duke@435 | 891 | void fxsave(Address dst); |
duke@435 | 892 | void fxrstor(Address src); |
duke@435 | 893 | void ldmxcsr(Address src); |
duke@435 | 894 | void stmxcsr(Address dst); |
duke@435 | 895 | |
duke@435 | 896 | void addss(XMMRegister dst, XMMRegister src); |
duke@435 | 897 | void addss(XMMRegister dst, Address src); |
duke@435 | 898 | void subss(XMMRegister dst, XMMRegister src); |
duke@435 | 899 | void subss(XMMRegister dst, Address src); |
duke@435 | 900 | void mulss(XMMRegister dst, XMMRegister src); |
duke@435 | 901 | void mulss(XMMRegister dst, Address src); |
duke@435 | 902 | void divss(XMMRegister dst, XMMRegister src); |
duke@435 | 903 | void divss(XMMRegister dst, Address src); |
duke@435 | 904 | void addsd(XMMRegister dst, XMMRegister src); |
duke@435 | 905 | void addsd(XMMRegister dst, Address src); |
duke@435 | 906 | void subsd(XMMRegister dst, XMMRegister src); |
duke@435 | 907 | void subsd(XMMRegister dst, Address src); |
duke@435 | 908 | void mulsd(XMMRegister dst, XMMRegister src); |
duke@435 | 909 | void mulsd(XMMRegister dst, Address src); |
duke@435 | 910 | void divsd(XMMRegister dst, XMMRegister src); |
duke@435 | 911 | void divsd(XMMRegister dst, Address src); |
duke@435 | 912 | |
duke@435 | 913 | // We only need the double form |
duke@435 | 914 | void sqrtsd(XMMRegister dst, XMMRegister src); |
duke@435 | 915 | void sqrtsd(XMMRegister dst, Address src); |
duke@435 | 916 | |
duke@435 | 917 | void xorps(XMMRegister dst, XMMRegister src); |
duke@435 | 918 | void xorps(XMMRegister dst, Address src); |
duke@435 | 919 | void xorpd(XMMRegister dst, XMMRegister src); |
duke@435 | 920 | void xorpd(XMMRegister dst, Address src); |
duke@435 | 921 | |
duke@435 | 922 | void cvtsi2ssl(XMMRegister dst, Register src); |
duke@435 | 923 | void cvtsi2ssq(XMMRegister dst, Register src); |
duke@435 | 924 | void cvtsi2sdl(XMMRegister dst, Register src); |
duke@435 | 925 | void cvtsi2sdq(XMMRegister dst, Register src); |
duke@435 | 926 | void cvttss2sil(Register dst, XMMRegister src); // truncates |
duke@435 | 927 | void cvttss2siq(Register dst, XMMRegister src); // truncates |
duke@435 | 928 | void cvttsd2sil(Register dst, XMMRegister src); // truncates |
duke@435 | 929 | void cvttsd2siq(Register dst, XMMRegister src); // truncates |
duke@435 | 930 | void cvtss2sd(XMMRegister dst, XMMRegister src); |
duke@435 | 931 | void cvtsd2ss(XMMRegister dst, XMMRegister src); |
kvn@506 | 932 | void cvtdq2pd(XMMRegister dst, XMMRegister src); |
kvn@506 | 933 | void cvtdq2ps(XMMRegister dst, XMMRegister src); |
duke@435 | 934 | |
duke@435 | 935 | void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values |
duke@435 | 936 | void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values |
duke@435 | 937 | |
duke@435 | 938 | void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword |
duke@435 | 939 | void movdqa(XMMRegister dst, XMMRegister src); |
duke@435 | 940 | void movdqa(Address dst, XMMRegister src); |
duke@435 | 941 | |
duke@435 | 942 | void movq(XMMRegister dst, Address src); |
duke@435 | 943 | void movq(Address dst, XMMRegister src); |
duke@435 | 944 | |
duke@435 | 945 | void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords |
duke@435 | 946 | void pshufd(XMMRegister dst, Address src, int mode); |
duke@435 | 947 | void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words |
duke@435 | 948 | void pshuflw(XMMRegister dst, Address src, int mode); |
duke@435 | 949 | |
duke@435 | 950 | void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate |
duke@435 | 951 | |
duke@435 | 952 | void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes |
duke@435 | 953 | void punpcklbw(XMMRegister dst, Address src); |
duke@435 | 954 | }; |
duke@435 | 955 | |
duke@435 | 956 | |
duke@435 | 957 | // MacroAssembler extends Assembler by frequently used macros. |
duke@435 | 958 | // |
duke@435 | 959 | // Instructions for which a 'better' code sequence exists depending |
duke@435 | 960 | // on arguments should also go in here. |
duke@435 | 961 | |
duke@435 | 962 | class MacroAssembler : public Assembler { |
duke@435 | 963 | friend class LIR_Assembler; |
duke@435 | 964 | protected: |
duke@435 | 965 | |
duke@435 | 966 | Address as_Address(AddressLiteral adr); |
duke@435 | 967 | Address as_Address(ArrayAddress adr); |
duke@435 | 968 | |
duke@435 | 969 | // Support for VM calls |
duke@435 | 970 | // |
duke@435 | 971 | // This is the base routine called by the different versions of |
duke@435 | 972 | // call_VM_leaf. The interpreter may customize this version by |
duke@435 | 973 | // overriding it for its purposes (e.g., to save/restore additional |
duke@435 | 974 | // registers when doing a VM call). |
duke@435 | 975 | |
duke@435 | 976 | virtual void call_VM_leaf_base( |
duke@435 | 977 | address entry_point, // the entry point |
duke@435 | 978 | int number_of_arguments // the number of arguments to |
duke@435 | 979 | // pop after the call |
duke@435 | 980 | ); |
duke@435 | 981 | |
duke@435 | 982 | // This is the base routine called by the different versions of |
duke@435 | 983 | // call_VM. The interpreter may customize this version by overriding |
duke@435 | 984 | // it for its purposes (e.g., to save/restore additional registers |
duke@435 | 985 | // when doing a VM call). |
duke@435 | 986 | // |
duke@435 | 987 | // If no java_thread register is specified (noreg) than rdi will be |
duke@435 | 988 | // used instead. call_VM_base returns the register which contains |
duke@435 | 989 | // the thread upon return. If a thread register has been specified, |
duke@435 | 990 | // the return value will correspond to that register. If no |
duke@435 | 991 | // last_java_sp is specified (noreg) than rsp will be used instead. |
duke@435 | 992 | virtual void call_VM_base( // returns the register |
duke@435 | 993 | // containing the thread upon |
duke@435 | 994 | // return |
duke@435 | 995 | Register oop_result, // where an oop-result ends up |
duke@435 | 996 | // if any; use noreg otherwise |
duke@435 | 997 | Register java_thread, // the thread if computed |
duke@435 | 998 | // before ; use noreg otherwise |
duke@435 | 999 | Register last_java_sp, // to set up last_Java_frame in |
duke@435 | 1000 | // stubs; use noreg otherwise |
duke@435 | 1001 | address entry_point, // the entry point |
duke@435 | 1002 | int number_of_arguments, // the number of arguments (w/o |
duke@435 | 1003 | // thread) to pop after the |
duke@435 | 1004 | // call |
duke@435 | 1005 | bool check_exceptions // whether to check for pending |
duke@435 | 1006 | // exceptions after return |
duke@435 | 1007 | ); |
duke@435 | 1008 | |
duke@435 | 1009 | // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code. |
duke@435 | 1010 | // The implementation is only non-empty for the InterpreterMacroAssembler, |
duke@435 | 1011 | // as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
duke@435 | 1012 | virtual void check_and_handle_popframe(Register java_thread); |
duke@435 | 1013 | virtual void check_and_handle_earlyret(Register java_thread); |
duke@435 | 1014 | |
duke@435 | 1015 | void call_VM_helper(Register oop_result, |
duke@435 | 1016 | address entry_point, |
duke@435 | 1017 | int number_of_arguments, |
duke@435 | 1018 | bool check_exceptions = true); |
duke@435 | 1019 | |
duke@435 | 1020 | public: |
duke@435 | 1021 | MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
duke@435 | 1022 | |
duke@435 | 1023 | // Support for NULL-checks |
duke@435 | 1024 | // |
duke@435 | 1025 | // Generates code that causes a NULL OS exception if the content of |
duke@435 | 1026 | // reg is NULL. If the accessed location is M[reg + offset] and the |
duke@435 | 1027 | // offset is known, provide the offset. No explicit code generation |
duke@435 | 1028 | // is needed if the offset is within a certain range (0 <= offset <= |
duke@435 | 1029 | // page_size). |
duke@435 | 1030 | void null_check(Register reg, int offset = -1); |
duke@435 | 1031 | static bool needs_explicit_null_check(int offset); |
duke@435 | 1032 | |
duke@435 | 1033 | // Required platform-specific helpers for Label::patch_instructions. |
duke@435 | 1034 | // They _shadow_ the declarations in AbstractAssembler, which are undefined. |
duke@435 | 1035 | void pd_patch_instruction(address branch, address target); |
duke@435 | 1036 | #ifndef PRODUCT |
duke@435 | 1037 | static void pd_print_patched_instruction(address branch); |
duke@435 | 1038 | #endif |
duke@435 | 1039 | |
duke@435 | 1040 | |
duke@435 | 1041 | // The following 4 methods return the offset of the appropriate move |
duke@435 | 1042 | // instruction. Note: these are 32 bit instructions |
duke@435 | 1043 | |
duke@435 | 1044 | // Support for fast byte/word loading with zero extension (depending |
duke@435 | 1045 | // on particular CPU) |
duke@435 | 1046 | int load_unsigned_byte(Register dst, Address src); |
duke@435 | 1047 | int load_unsigned_word(Register dst, Address src); |
duke@435 | 1048 | |
duke@435 | 1049 | // Support for fast byte/word loading with sign extension (depending |
duke@435 | 1050 | // on particular CPU) |
duke@435 | 1051 | int load_signed_byte(Register dst, Address src); |
duke@435 | 1052 | int load_signed_word(Register dst, Address src); |
duke@435 | 1053 | |
duke@435 | 1054 | // Support for inc/dec with optimal instruction selection depending |
duke@435 | 1055 | // on value |
duke@435 | 1056 | void incrementl(Register reg, int value = 1); |
duke@435 | 1057 | void decrementl(Register reg, int value = 1); |
duke@435 | 1058 | void incrementq(Register reg, int value = 1); |
duke@435 | 1059 | void decrementq(Register reg, int value = 1); |
duke@435 | 1060 | |
duke@435 | 1061 | void incrementl(Address dst, int value = 1); |
duke@435 | 1062 | void decrementl(Address dst, int value = 1); |
duke@435 | 1063 | void incrementq(Address dst, int value = 1); |
duke@435 | 1064 | void decrementq(Address dst, int value = 1); |
duke@435 | 1065 | |
duke@435 | 1066 | // Support optimal SSE move instructions. |
duke@435 | 1067 | void movflt(XMMRegister dst, XMMRegister src) { |
duke@435 | 1068 | if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
duke@435 | 1069 | else { movss (dst, src); return; } |
duke@435 | 1070 | } |
duke@435 | 1071 | |
duke@435 | 1072 | void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
duke@435 | 1073 | |
duke@435 | 1074 | void movflt(XMMRegister dst, AddressLiteral src); |
duke@435 | 1075 | |
duke@435 | 1076 | void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
duke@435 | 1077 | |
duke@435 | 1078 | void movdbl(XMMRegister dst, XMMRegister src) { |
duke@435 | 1079 | if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
duke@435 | 1080 | else { movsd (dst, src); return; } |
duke@435 | 1081 | } |
duke@435 | 1082 | |
duke@435 | 1083 | void movdbl(XMMRegister dst, AddressLiteral src); |
duke@435 | 1084 | |
duke@435 | 1085 | void movdbl(XMMRegister dst, Address src) { |
duke@435 | 1086 | if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
duke@435 | 1087 | else { movlpd(dst, src); return; } |
duke@435 | 1088 | } |
duke@435 | 1089 | |
duke@435 | 1090 | void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
duke@435 | 1091 | |
duke@435 | 1092 | void incrementl(AddressLiteral dst); |
duke@435 | 1093 | void incrementl(ArrayAddress dst); |
duke@435 | 1094 | |
duke@435 | 1095 | // Alignment |
duke@435 | 1096 | void align(int modulus); |
duke@435 | 1097 | |
duke@435 | 1098 | // Misc |
duke@435 | 1099 | void fat_nop(); // 5 byte nop |
duke@435 | 1100 | |
duke@435 | 1101 | |
duke@435 | 1102 | // C++ bool manipulation |
duke@435 | 1103 | |
duke@435 | 1104 | void movbool(Register dst, Address src); |
duke@435 | 1105 | void movbool(Address dst, bool boolconst); |
duke@435 | 1106 | void movbool(Address dst, Register src); |
duke@435 | 1107 | void testbool(Register dst); |
duke@435 | 1108 | |
coleenp@548 | 1109 | // oop manipulations |
coleenp@548 | 1110 | void load_klass(Register dst, Register src); |
coleenp@548 | 1111 | void store_klass(Register dst, Register src); |
coleenp@548 | 1112 | |
coleenp@548 | 1113 | void load_heap_oop(Register dst, Address src); |
coleenp@548 | 1114 | void store_heap_oop(Address dst, Register src); |
coleenp@548 | 1115 | void encode_heap_oop(Register r); |
coleenp@548 | 1116 | void decode_heap_oop(Register r); |
coleenp@548 | 1117 | void encode_heap_oop_not_null(Register r); |
coleenp@548 | 1118 | void decode_heap_oop_not_null(Register r); |
kvn@559 | 1119 | void encode_heap_oop_not_null(Register dst, Register src); |
kvn@559 | 1120 | void decode_heap_oop_not_null(Register dst, Register src); |
coleenp@548 | 1121 | |
kvn@599 | 1122 | void set_narrow_oop(Register dst, jobject obj); |
kvn@599 | 1123 | |
duke@435 | 1124 | // Stack frame creation/removal |
duke@435 | 1125 | void enter(); |
duke@435 | 1126 | void leave(); |
duke@435 | 1127 | |
duke@435 | 1128 | // Support for getting the JavaThread pointer (i.e.; a reference to |
duke@435 | 1129 | // thread-local information) The pointer will be loaded into the |
duke@435 | 1130 | // thread register. |
duke@435 | 1131 | void get_thread(Register thread); |
duke@435 | 1132 | |
duke@435 | 1133 | void int3(); |
duke@435 | 1134 | |
duke@435 | 1135 | // Support for VM calls |
duke@435 | 1136 | // |
duke@435 | 1137 | // It is imperative that all calls into the VM are handled via the |
duke@435 | 1138 | // call_VM macros. They make sure that the stack linkage is setup |
duke@435 | 1139 | // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points |
duke@435 | 1140 | // while call_VM_leaf's correspond to LEAF entry points. |
duke@435 | 1141 | void call_VM(Register oop_result, |
duke@435 | 1142 | address entry_point, |
duke@435 | 1143 | bool check_exceptions = true); |
duke@435 | 1144 | void call_VM(Register oop_result, |
duke@435 | 1145 | address entry_point, |
duke@435 | 1146 | Register arg_1, |
duke@435 | 1147 | bool check_exceptions = true); |
duke@435 | 1148 | void call_VM(Register oop_result, |
duke@435 | 1149 | address entry_point, |
duke@435 | 1150 | Register arg_1, Register arg_2, |
duke@435 | 1151 | bool check_exceptions = true); |
duke@435 | 1152 | void call_VM(Register oop_result, |
duke@435 | 1153 | address entry_point, |
duke@435 | 1154 | Register arg_1, Register arg_2, Register arg_3, |
duke@435 | 1155 | bool check_exceptions = true); |
duke@435 | 1156 | |
duke@435 | 1157 | // Overloadings with last_Java_sp |
duke@435 | 1158 | void call_VM(Register oop_result, |
duke@435 | 1159 | Register last_java_sp, |
duke@435 | 1160 | address entry_point, |
duke@435 | 1161 | int number_of_arguments = 0, |
duke@435 | 1162 | bool check_exceptions = true); |
duke@435 | 1163 | void call_VM(Register oop_result, |
duke@435 | 1164 | Register last_java_sp, |
duke@435 | 1165 | address entry_point, |
duke@435 | 1166 | Register arg_1, bool |
duke@435 | 1167 | check_exceptions = true); |
duke@435 | 1168 | void call_VM(Register oop_result, |
duke@435 | 1169 | Register last_java_sp, |
duke@435 | 1170 | address entry_point, |
duke@435 | 1171 | Register arg_1, Register arg_2, |
duke@435 | 1172 | bool check_exceptions = true); |
duke@435 | 1173 | void call_VM(Register oop_result, |
duke@435 | 1174 | Register last_java_sp, |
duke@435 | 1175 | address entry_point, |
duke@435 | 1176 | Register arg_1, Register arg_2, Register arg_3, |
duke@435 | 1177 | bool check_exceptions = true); |
duke@435 | 1178 | |
duke@435 | 1179 | void call_VM_leaf(address entry_point, |
duke@435 | 1180 | int number_of_arguments = 0); |
duke@435 | 1181 | void call_VM_leaf(address entry_point, |
duke@435 | 1182 | Register arg_1); |
duke@435 | 1183 | void call_VM_leaf(address entry_point, |
duke@435 | 1184 | Register arg_1, Register arg_2); |
duke@435 | 1185 | void call_VM_leaf(address entry_point, |
duke@435 | 1186 | Register arg_1, Register arg_2, Register arg_3); |
duke@435 | 1187 | |
duke@435 | 1188 | // last Java Frame (fills frame anchor) |
duke@435 | 1189 | void set_last_Java_frame(Register last_java_sp, |
duke@435 | 1190 | Register last_java_fp, |
duke@435 | 1191 | address last_java_pc); |
duke@435 | 1192 | void reset_last_Java_frame(bool clear_fp, bool clear_pc); |
duke@435 | 1193 | |
duke@435 | 1194 | // Stores |
duke@435 | 1195 | void store_check(Register obj); // store check for |
duke@435 | 1196 | // obj - register is |
duke@435 | 1197 | // destroyed |
duke@435 | 1198 | // afterwards |
duke@435 | 1199 | void store_check(Register obj, Address dst); // same as above, dst |
duke@435 | 1200 | // is exact store |
duke@435 | 1201 | // location (reg. is |
duke@435 | 1202 | // destroyed) |
duke@435 | 1203 | |
duke@435 | 1204 | // split store_check(Register obj) to enhance instruction interleaving |
duke@435 | 1205 | void store_check_part_1(Register obj); |
duke@435 | 1206 | void store_check_part_2(Register obj); |
duke@435 | 1207 | |
duke@435 | 1208 | // C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
duke@435 | 1209 | void c2bool(Register x); |
duke@435 | 1210 | |
duke@435 | 1211 | // Int division/reminder for Java |
duke@435 | 1212 | // (as idivl, but checks for special case as described in JVM spec.) |
duke@435 | 1213 | // returns idivl instruction offset for implicit exception handling |
duke@435 | 1214 | int corrected_idivl(Register reg); |
duke@435 | 1215 | // Long division/reminder for Java |
duke@435 | 1216 | // (as idivq, but checks for special case as described in JVM spec.) |
duke@435 | 1217 | // returns idivq instruction offset for implicit exception handling |
duke@435 | 1218 | int corrected_idivq(Register reg); |
duke@435 | 1219 | |
duke@435 | 1220 | // Push and pop integer/fpu/cpu state |
duke@435 | 1221 | void push_IU_state(); |
duke@435 | 1222 | void pop_IU_state(); |
duke@435 | 1223 | |
duke@435 | 1224 | void push_FPU_state(); |
duke@435 | 1225 | void pop_FPU_state(); |
duke@435 | 1226 | |
duke@435 | 1227 | void push_CPU_state(); |
duke@435 | 1228 | void pop_CPU_state(); |
duke@435 | 1229 | |
duke@435 | 1230 | // Sign extension |
duke@435 | 1231 | void sign_extend_short(Register reg); |
duke@435 | 1232 | void sign_extend_byte(Register reg); |
duke@435 | 1233 | |
duke@435 | 1234 | // Division by power of 2, rounding towards 0 |
duke@435 | 1235 | void division_with_shift(Register reg, int shift_value); |
duke@435 | 1236 | |
duke@435 | 1237 | // Round up to a power of two |
duke@435 | 1238 | void round_to_l(Register reg, int modulus); |
duke@435 | 1239 | void round_to_q(Register reg, int modulus); |
duke@435 | 1240 | |
duke@435 | 1241 | // allocation |
duke@435 | 1242 | void eden_allocate( |
duke@435 | 1243 | Register obj, // result: pointer to object after |
duke@435 | 1244 | // successful allocation |
duke@435 | 1245 | Register var_size_in_bytes, // object size in bytes if unknown at |
duke@435 | 1246 | // compile time; invalid otherwise |
duke@435 | 1247 | int con_size_in_bytes, // object size in bytes if known at |
duke@435 | 1248 | // compile time |
duke@435 | 1249 | Register t1, // temp register |
duke@435 | 1250 | Label& slow_case // continuation point if fast |
duke@435 | 1251 | // allocation fails |
duke@435 | 1252 | ); |
duke@435 | 1253 | void tlab_allocate( |
duke@435 | 1254 | Register obj, // result: pointer to object after |
duke@435 | 1255 | // successful allocation |
duke@435 | 1256 | Register var_size_in_bytes, // object size in bytes if unknown at |
duke@435 | 1257 | // compile time; invalid otherwise |
duke@435 | 1258 | int con_size_in_bytes, // object size in bytes if known at |
duke@435 | 1259 | // compile time |
duke@435 | 1260 | Register t1, // temp register |
duke@435 | 1261 | Register t2, // temp register |
duke@435 | 1262 | Label& slow_case // continuation point if fast |
duke@435 | 1263 | // allocation fails |
duke@435 | 1264 | ); |
duke@435 | 1265 | void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); |
duke@435 | 1266 | |
duke@435 | 1267 | //---- |
duke@435 | 1268 | |
duke@435 | 1269 | // Debugging |
duke@435 | 1270 | |
duke@435 | 1271 | // only if +VerifyOops |
duke@435 | 1272 | void verify_oop(Register reg, const char* s = "broken oop"); |
duke@435 | 1273 | void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
duke@435 | 1274 | |
coleenp@548 | 1275 | // if heap base register is used - reinit it with the correct value |
coleenp@548 | 1276 | void reinit_heapbase(); |
coleenp@548 | 1277 | |
duke@435 | 1278 | // only if +VerifyFPU |
duke@435 | 1279 | void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {} |
duke@435 | 1280 | |
duke@435 | 1281 | // prints msg, dumps registers and stops execution |
duke@435 | 1282 | void stop(const char* msg); |
duke@435 | 1283 | |
duke@435 | 1284 | // prints message and continues |
duke@435 | 1285 | void warn(const char* msg); |
duke@435 | 1286 | |
duke@435 | 1287 | static void debug(char* msg, int64_t pc, int64_t regs[]); |
duke@435 | 1288 | |
duke@435 | 1289 | void os_breakpoint(); |
duke@435 | 1290 | |
duke@435 | 1291 | void untested() |
duke@435 | 1292 | { |
duke@435 | 1293 | stop("untested"); |
duke@435 | 1294 | } |
duke@435 | 1295 | |
duke@435 | 1296 | void unimplemented(const char* what = "") |
duke@435 | 1297 | { |
duke@435 | 1298 | char* b = new char[1024]; |
duke@435 | 1299 | sprintf(b, "unimplemented: %s", what); |
duke@435 | 1300 | stop(b); |
duke@435 | 1301 | } |
duke@435 | 1302 | |
duke@435 | 1303 | void should_not_reach_here() |
duke@435 | 1304 | { |
duke@435 | 1305 | stop("should not reach here"); |
duke@435 | 1306 | } |
duke@435 | 1307 | |
duke@435 | 1308 | // Stack overflow checking |
duke@435 | 1309 | void bang_stack_with_offset(int offset) |
duke@435 | 1310 | { |
duke@435 | 1311 | // stack grows down, caller passes positive offset |
duke@435 | 1312 | assert(offset > 0, "must bang with negative offset"); |
duke@435 | 1313 | movl(Address(rsp, (-offset)), rax); |
duke@435 | 1314 | } |
duke@435 | 1315 | |
duke@435 | 1316 | // Writes to stack successive pages until offset reached to check for |
duke@435 | 1317 | // stack overflow + shadow pages. Also, clobbers tmp |
duke@435 | 1318 | void bang_stack_size(Register offset, Register tmp); |
duke@435 | 1319 | |
duke@435 | 1320 | // Support for serializing memory accesses between threads. |
duke@435 | 1321 | void serialize_memory(Register thread, Register tmp); |
duke@435 | 1322 | |
duke@435 | 1323 | void verify_tlab(); |
duke@435 | 1324 | |
duke@435 | 1325 | // Biased locking support |
duke@435 | 1326 | // lock_reg and obj_reg must be loaded up with the appropriate values. |
duke@435 | 1327 | // swap_reg must be rax and is killed. |
duke@435 | 1328 | // tmp_reg must be supplied and is killed. |
duke@435 | 1329 | // If swap_reg_contains_mark is true then the code assumes that the |
duke@435 | 1330 | // mark word of the object has already been loaded into swap_reg. |
duke@435 | 1331 | // Optional slow case is for implementations (interpreter and C1) which branch to |
duke@435 | 1332 | // slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
duke@435 | 1333 | // Returns offset of first potentially-faulting instruction for null |
duke@435 | 1334 | // check info (currently consumed only by C1). If |
duke@435 | 1335 | // swap_reg_contains_mark is true then returns -1 as it is assumed |
duke@435 | 1336 | // the calling code has already passed any potential faults. |
duke@435 | 1337 | int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, |
duke@435 | 1338 | bool swap_reg_contains_mark, |
duke@435 | 1339 | Label& done, Label* slow_case = NULL, |
duke@435 | 1340 | BiasedLockingCounters* counters = NULL); |
duke@435 | 1341 | void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
duke@435 | 1342 | |
duke@435 | 1343 | Condition negate_condition(Condition cond); |
duke@435 | 1344 | |
duke@435 | 1345 | // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
duke@435 | 1346 | // operands. In general the names are modified to avoid hiding the instruction in Assembler |
duke@435 | 1347 | // so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
duke@435 | 1348 | // here in MacroAssembler. The major exception to this rule is call |
duke@435 | 1349 | |
duke@435 | 1350 | // Arithmetics |
duke@435 | 1351 | |
duke@435 | 1352 | void cmp8(AddressLiteral src1, int8_t imm32); |
duke@435 | 1353 | |
duke@435 | 1354 | void cmp32(AddressLiteral src1, int32_t src2); |
duke@435 | 1355 | // compare reg - mem, or reg - &mem |
duke@435 | 1356 | void cmp32(Register src1, AddressLiteral src2); |
duke@435 | 1357 | |
duke@435 | 1358 | void cmp32(Register src1, Address src2); |
duke@435 | 1359 | |
duke@435 | 1360 | #ifndef _LP64 |
duke@435 | 1361 | void cmpoop(Address dst, jobject obj); |
duke@435 | 1362 | void cmpoop(Register dst, jobject obj); |
duke@435 | 1363 | #endif // _LP64 |
duke@435 | 1364 | |
duke@435 | 1365 | // NOTE src2 must be the lval. This is NOT an mem-mem compare |
duke@435 | 1366 | void cmpptr(Address src1, AddressLiteral src2); |
duke@435 | 1367 | |
duke@435 | 1368 | void cmpptr(Register src1, AddressLiteral src); |
duke@435 | 1369 | |
duke@435 | 1370 | // will be cmpreg(?) |
duke@435 | 1371 | void cmp64(Register src1, AddressLiteral src); |
duke@435 | 1372 | |
duke@435 | 1373 | void cmpxchgptr(Register reg, Address adr); |
duke@435 | 1374 | void cmpxchgptr(Register reg, AddressLiteral adr); |
duke@435 | 1375 | |
duke@435 | 1376 | // Helper functions for statistics gathering. |
duke@435 | 1377 | // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
duke@435 | 1378 | void cond_inc32(Condition cond, AddressLiteral counter_addr); |
duke@435 | 1379 | // Unconditional atomic increment. |
duke@435 | 1380 | void atomic_incl(AddressLiteral counter_addr); |
duke@435 | 1381 | |
duke@435 | 1382 | |
duke@435 | 1383 | void lea(Register dst, AddressLiteral src); |
duke@435 | 1384 | void lea(Register dst, Address src); |
duke@435 | 1385 | |
duke@435 | 1386 | |
duke@435 | 1387 | // Calls |
duke@435 | 1388 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 1389 | void call(Register entry); |
duke@435 | 1390 | void call(AddressLiteral entry); |
duke@435 | 1391 | |
duke@435 | 1392 | // Jumps |
duke@435 | 1393 | |
duke@435 | 1394 | // 32bit can do a case table jump in one instruction but we no longer allow the base |
duke@435 | 1395 | // to be installed in the Address class |
duke@435 | 1396 | void jump(ArrayAddress entry); |
duke@435 | 1397 | |
duke@435 | 1398 | void jump(AddressLiteral entry); |
duke@435 | 1399 | void jump_cc(Condition cc, AddressLiteral dst); |
duke@435 | 1400 | |
duke@435 | 1401 | // Floating |
duke@435 | 1402 | |
duke@435 | 1403 | void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
duke@435 | 1404 | void ldmxcsr(AddressLiteral src); |
duke@435 | 1405 | |
duke@435 | 1406 | private: |
duke@435 | 1407 | // these are private because users should be doing movflt/movdbl |
duke@435 | 1408 | |
duke@435 | 1409 | void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 1410 | void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 1411 | void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
duke@435 | 1412 | void movss(XMMRegister dst, AddressLiteral src); |
duke@435 | 1413 | |
duke@435 | 1414 | void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
duke@435 | 1415 | void movlpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1416 | |
duke@435 | 1417 | public: |
duke@435 | 1418 | |
duke@435 | 1419 | |
duke@435 | 1420 | void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); } |
duke@435 | 1421 | void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); } |
duke@435 | 1422 | void xorpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1423 | |
duke@435 | 1424 | void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); } |
duke@435 | 1425 | void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); } |
duke@435 | 1426 | void xorps(XMMRegister dst, AddressLiteral src); |
duke@435 | 1427 | |
duke@435 | 1428 | |
duke@435 | 1429 | // Data |
duke@435 | 1430 | |
duke@435 | 1431 | void movoop(Register dst, jobject obj); |
duke@435 | 1432 | void movoop(Address dst, jobject obj); |
duke@435 | 1433 | |
duke@435 | 1434 | void movptr(ArrayAddress dst, Register src); |
duke@435 | 1435 | void movptr(Register dst, AddressLiteral src); |
duke@435 | 1436 | |
duke@435 | 1437 | void movptr(Register dst, intptr_t src); |
duke@435 | 1438 | void movptr(Address dst, intptr_t src); |
duke@435 | 1439 | |
duke@435 | 1440 | void movptr(Register dst, ArrayAddress src); |
duke@435 | 1441 | |
duke@435 | 1442 | // to avoid hiding movl |
duke@435 | 1443 | void mov32(AddressLiteral dst, Register src); |
duke@435 | 1444 | void mov32(Register dst, AddressLiteral src); |
duke@435 | 1445 | |
duke@435 | 1446 | void pushoop(jobject obj); |
duke@435 | 1447 | |
duke@435 | 1448 | // Can push value or effective address |
duke@435 | 1449 | void pushptr(AddressLiteral src); |
duke@435 | 1450 | |
duke@435 | 1451 | }; |
duke@435 | 1452 | |
duke@435 | 1453 | /** |
duke@435 | 1454 | * class SkipIfEqual: |
duke@435 | 1455 | * |
duke@435 | 1456 | * Instantiating this class will result in assembly code being output that will |
duke@435 | 1457 | * jump around any code emitted between the creation of the instance and it's |
duke@435 | 1458 | * automatic destruction at the end of a scope block, depending on the value of |
duke@435 | 1459 | * the flag passed to the constructor, which will be checked at run-time. |
duke@435 | 1460 | */ |
duke@435 | 1461 | class SkipIfEqual { |
duke@435 | 1462 | private: |
duke@435 | 1463 | MacroAssembler* _masm; |
duke@435 | 1464 | Label _label; |
duke@435 | 1465 | |
duke@435 | 1466 | public: |
duke@435 | 1467 | SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
duke@435 | 1468 | ~SkipIfEqual(); |
duke@435 | 1469 | }; |
duke@435 | 1470 | |
duke@435 | 1471 | |
duke@435 | 1472 | #ifdef ASSERT |
duke@435 | 1473 | inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
duke@435 | 1474 | #endif |