Wed, 24 Oct 2012 14:33:22 -0700
7184394: add intrinsics to use AES instructions
Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com
twisti@1020 | 1 | /* |
sla@3587 | 2 | * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
twisti@1020 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
twisti@1020 | 4 | * |
twisti@1020 | 5 | * This code is free software; you can redistribute it and/or modify it |
twisti@1020 | 6 | * under the terms of the GNU General Public License version 2 only, as |
twisti@1020 | 7 | * published by the Free Software Foundation. |
twisti@1020 | 8 | * |
twisti@1020 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
twisti@1020 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
twisti@1020 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
twisti@1020 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
twisti@1020 | 13 | * accompanied this code). |
twisti@1020 | 14 | * |
twisti@1020 | 15 | * You should have received a copy of the GNU General Public License version |
twisti@1020 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
twisti@1020 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
twisti@1020 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
twisti@1020 | 22 | * |
twisti@1020 | 23 | */ |
twisti@1020 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "assembler_x86.inline.hpp" |
stefank@2314 | 27 | #include "memory/resourceArea.hpp" |
stefank@2314 | 28 | #include "runtime/java.hpp" |
stefank@2314 | 29 | #include "runtime/stubCodeGenerator.hpp" |
stefank@2314 | 30 | #include "vm_version_x86.hpp" |
stefank@2314 | 31 | #ifdef TARGET_OS_FAMILY_linux |
stefank@2314 | 32 | # include "os_linux.inline.hpp" |
stefank@2314 | 33 | #endif |
stefank@2314 | 34 | #ifdef TARGET_OS_FAMILY_solaris |
stefank@2314 | 35 | # include "os_solaris.inline.hpp" |
stefank@2314 | 36 | #endif |
stefank@2314 | 37 | #ifdef TARGET_OS_FAMILY_windows |
stefank@2314 | 38 | # include "os_windows.inline.hpp" |
stefank@2314 | 39 | #endif |
never@3156 | 40 | #ifdef TARGET_OS_FAMILY_bsd |
never@3156 | 41 | # include "os_bsd.inline.hpp" |
never@3156 | 42 | #endif |
twisti@1020 | 43 | |
twisti@1020 | 44 | |
twisti@1020 | 45 | int VM_Version::_cpu; |
twisti@1020 | 46 | int VM_Version::_model; |
twisti@1020 | 47 | int VM_Version::_stepping; |
twisti@1020 | 48 | int VM_Version::_cpuFeatures; |
twisti@1020 | 49 | const char* VM_Version::_features_str = ""; |
twisti@1020 | 50 | VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
twisti@1020 | 51 | |
twisti@1020 | 52 | static BufferBlob* stub_blob; |
kvn@3400 | 53 | static const int stub_size = 550; |
twisti@1020 | 54 | |
twisti@1020 | 55 | extern "C" { |
twisti@1020 | 56 | typedef void (*getPsrInfo_stub_t)(void*); |
twisti@1020 | 57 | } |
twisti@1020 | 58 | static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
twisti@1020 | 59 | |
twisti@1020 | 60 | |
twisti@1020 | 61 | class VM_Version_StubGenerator: public StubCodeGenerator { |
twisti@1020 | 62 | public: |
twisti@1020 | 63 | |
twisti@1020 | 64 | VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
twisti@1020 | 65 | |
twisti@1020 | 66 | address generate_getPsrInfo() { |
twisti@1020 | 67 | // Flags to test CPU type. |
sla@3587 | 68 | const uint32_t HS_EFL_AC = 0x40000; |
sla@3587 | 69 | const uint32_t HS_EFL_ID = 0x200000; |
twisti@1020 | 70 | // Values for when we don't have a CPUID instruction. |
twisti@1020 | 71 | const int CPU_FAMILY_SHIFT = 8; |
twisti@1020 | 72 | const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
twisti@1020 | 73 | const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
twisti@1020 | 74 | |
kvn@1977 | 75 | Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
kvn@3400 | 76 | Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
twisti@1020 | 77 | |
twisti@1020 | 78 | StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
twisti@1020 | 79 | # define __ _masm-> |
twisti@1020 | 80 | |
twisti@1020 | 81 | address start = __ pc(); |
twisti@1020 | 82 | |
twisti@1020 | 83 | // |
twisti@1020 | 84 | // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
twisti@1020 | 85 | // |
twisti@1020 | 86 | // LP64: rcx and rdx are first and second argument registers on windows |
twisti@1020 | 87 | |
twisti@1020 | 88 | __ push(rbp); |
twisti@1020 | 89 | #ifdef _LP64 |
twisti@1020 | 90 | __ mov(rbp, c_rarg0); // cpuid_info address |
twisti@1020 | 91 | #else |
twisti@1020 | 92 | __ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
twisti@1020 | 93 | #endif |
twisti@1020 | 94 | __ push(rbx); |
twisti@1020 | 95 | __ push(rsi); |
twisti@1020 | 96 | __ pushf(); // preserve rbx, and flags |
twisti@1020 | 97 | __ pop(rax); |
twisti@1020 | 98 | __ push(rax); |
twisti@1020 | 99 | __ mov(rcx, rax); |
twisti@1020 | 100 | // |
twisti@1020 | 101 | // if we are unable to change the AC flag, we have a 386 |
twisti@1020 | 102 | // |
sla@3587 | 103 | __ xorl(rax, HS_EFL_AC); |
twisti@1020 | 104 | __ push(rax); |
twisti@1020 | 105 | __ popf(); |
twisti@1020 | 106 | __ pushf(); |
twisti@1020 | 107 | __ pop(rax); |
twisti@1020 | 108 | __ cmpptr(rax, rcx); |
twisti@1020 | 109 | __ jccb(Assembler::notEqual, detect_486); |
twisti@1020 | 110 | |
twisti@1020 | 111 | __ movl(rax, CPU_FAMILY_386); |
twisti@1020 | 112 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 113 | __ jmp(done); |
twisti@1020 | 114 | |
twisti@1020 | 115 | // |
twisti@1020 | 116 | // If we are unable to change the ID flag, we have a 486 which does |
twisti@1020 | 117 | // not support the "cpuid" instruction. |
twisti@1020 | 118 | // |
twisti@1020 | 119 | __ bind(detect_486); |
twisti@1020 | 120 | __ mov(rax, rcx); |
sla@3587 | 121 | __ xorl(rax, HS_EFL_ID); |
twisti@1020 | 122 | __ push(rax); |
twisti@1020 | 123 | __ popf(); |
twisti@1020 | 124 | __ pushf(); |
twisti@1020 | 125 | __ pop(rax); |
twisti@1020 | 126 | __ cmpptr(rcx, rax); |
twisti@1020 | 127 | __ jccb(Assembler::notEqual, detect_586); |
twisti@1020 | 128 | |
twisti@1020 | 129 | __ bind(cpu486); |
twisti@1020 | 130 | __ movl(rax, CPU_FAMILY_486); |
twisti@1020 | 131 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 132 | __ jmp(done); |
twisti@1020 | 133 | |
twisti@1020 | 134 | // |
twisti@1020 | 135 | // At this point, we have a chip which supports the "cpuid" instruction |
twisti@1020 | 136 | // |
twisti@1020 | 137 | __ bind(detect_586); |
twisti@1020 | 138 | __ xorl(rax, rax); |
twisti@1020 | 139 | __ cpuid(); |
twisti@1020 | 140 | __ orl(rax, rax); |
twisti@1020 | 141 | __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
twisti@1020 | 142 | // value of at least 1, we give up and |
twisti@1020 | 143 | // assume a 486 |
twisti@1020 | 144 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
twisti@1020 | 145 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 146 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 147 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 148 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 149 | |
kvn@1977 | 150 | __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
kvn@1977 | 151 | __ jccb(Assembler::belowEqual, std_cpuid4); |
kvn@1977 | 152 | |
kvn@1977 | 153 | // |
kvn@1977 | 154 | // cpuid(0xB) Processor Topology |
kvn@1977 | 155 | // |
kvn@1977 | 156 | __ movl(rax, 0xb); |
kvn@1977 | 157 | __ xorl(rcx, rcx); // Threads level |
kvn@1977 | 158 | __ cpuid(); |
kvn@1977 | 159 | |
kvn@1977 | 160 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
kvn@1977 | 161 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 162 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 163 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 164 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 165 | |
kvn@1977 | 166 | __ movl(rax, 0xb); |
kvn@1977 | 167 | __ movl(rcx, 1); // Cores level |
kvn@1977 | 168 | __ cpuid(); |
kvn@1977 | 169 | __ push(rax); |
kvn@1977 | 170 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 171 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 172 | __ andl(rax, 0xffff); |
kvn@1977 | 173 | __ pop(rax); |
kvn@1977 | 174 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 175 | |
kvn@1977 | 176 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
kvn@1977 | 177 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 178 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 179 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 180 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 181 | |
kvn@1977 | 182 | __ movl(rax, 0xb); |
kvn@1977 | 183 | __ movl(rcx, 2); // Packages level |
kvn@1977 | 184 | __ cpuid(); |
kvn@1977 | 185 | __ push(rax); |
kvn@1977 | 186 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 187 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 188 | __ andl(rax, 0xffff); |
kvn@1977 | 189 | __ pop(rax); |
kvn@1977 | 190 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 191 | |
kvn@1977 | 192 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
kvn@1977 | 193 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 194 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 195 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 196 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 197 | |
twisti@1020 | 198 | // |
twisti@1020 | 199 | // cpuid(0x4) Deterministic cache params |
twisti@1020 | 200 | // |
kvn@1977 | 201 | __ bind(std_cpuid4); |
twisti@1020 | 202 | __ movl(rax, 4); |
kvn@1977 | 203 | __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
kvn@1977 | 204 | __ jccb(Assembler::greater, std_cpuid1); |
kvn@1977 | 205 | |
twisti@1020 | 206 | __ xorl(rcx, rcx); // L1 cache |
twisti@1020 | 207 | __ cpuid(); |
twisti@1020 | 208 | __ push(rax); |
twisti@1020 | 209 | __ andl(rax, 0x1f); // Determine if valid cache parameters used |
twisti@1020 | 210 | __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
twisti@1020 | 211 | __ pop(rax); |
twisti@1020 | 212 | __ jccb(Assembler::equal, std_cpuid1); |
twisti@1020 | 213 | |
twisti@1020 | 214 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
twisti@1020 | 215 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 216 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 217 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 218 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 219 | |
twisti@1020 | 220 | // |
twisti@1020 | 221 | // Standard cpuid(0x1) |
twisti@1020 | 222 | // |
twisti@1020 | 223 | __ bind(std_cpuid1); |
twisti@1020 | 224 | __ movl(rax, 1); |
twisti@1020 | 225 | __ cpuid(); |
twisti@1020 | 226 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
twisti@1020 | 227 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 228 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 229 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 230 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 231 | |
kvn@3388 | 232 | // |
kvn@3388 | 233 | // Check if OS has enabled XGETBV instruction to access XCR0 |
kvn@3388 | 234 | // (OSXSAVE feature flag) and CPU supports AVX |
kvn@3388 | 235 | // |
kvn@3388 | 236 | __ andl(rcx, 0x18000000); |
kvn@3388 | 237 | __ cmpl(rcx, 0x18000000); |
kvn@3388 | 238 | __ jccb(Assembler::notEqual, sef_cpuid); |
kvn@3388 | 239 | |
kvn@3388 | 240 | // |
kvn@3388 | 241 | // XCR0, XFEATURE_ENABLED_MASK register |
kvn@3388 | 242 | // |
kvn@3388 | 243 | __ xorl(rcx, rcx); // zero for XCR0 register |
kvn@3388 | 244 | __ xgetbv(); |
kvn@3388 | 245 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); |
kvn@3388 | 246 | __ movl(Address(rsi, 0), rax); |
kvn@3388 | 247 | __ movl(Address(rsi, 4), rdx); |
kvn@3388 | 248 | |
kvn@3388 | 249 | // |
kvn@3388 | 250 | // cpuid(0x7) Structured Extended Features |
kvn@3388 | 251 | // |
kvn@3388 | 252 | __ bind(sef_cpuid); |
kvn@3388 | 253 | __ movl(rax, 7); |
kvn@3388 | 254 | __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? |
kvn@3388 | 255 | __ jccb(Assembler::greater, ext_cpuid); |
kvn@3388 | 256 | |
kvn@3388 | 257 | __ xorl(rcx, rcx); |
kvn@3388 | 258 | __ cpuid(); |
kvn@3388 | 259 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
kvn@3388 | 260 | __ movl(Address(rsi, 0), rax); |
kvn@3388 | 261 | __ movl(Address(rsi, 4), rbx); |
kvn@3388 | 262 | |
kvn@3388 | 263 | // |
kvn@3388 | 264 | // Extended cpuid(0x80000000) |
kvn@3388 | 265 | // |
kvn@3388 | 266 | __ bind(ext_cpuid); |
twisti@1020 | 267 | __ movl(rax, 0x80000000); |
twisti@1020 | 268 | __ cpuid(); |
twisti@1020 | 269 | __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
twisti@1020 | 270 | __ jcc(Assembler::belowEqual, done); |
twisti@1020 | 271 | __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
twisti@1020 | 272 | __ jccb(Assembler::belowEqual, ext_cpuid1); |
phh@3378 | 273 | __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
phh@3378 | 274 | __ jccb(Assembler::belowEqual, ext_cpuid5); |
twisti@1020 | 275 | __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
phh@3378 | 276 | __ jccb(Assembler::belowEqual, ext_cpuid7); |
twisti@1020 | 277 | // |
twisti@1020 | 278 | // Extended cpuid(0x80000008) |
twisti@1020 | 279 | // |
twisti@1020 | 280 | __ movl(rax, 0x80000008); |
twisti@1020 | 281 | __ cpuid(); |
twisti@1020 | 282 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
twisti@1020 | 283 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 284 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 285 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 286 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 287 | |
twisti@1020 | 288 | // |
phh@3378 | 289 | // Extended cpuid(0x80000007) |
phh@3378 | 290 | // |
phh@3378 | 291 | __ bind(ext_cpuid7); |
phh@3378 | 292 | __ movl(rax, 0x80000007); |
phh@3378 | 293 | __ cpuid(); |
phh@3378 | 294 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
phh@3378 | 295 | __ movl(Address(rsi, 0), rax); |
phh@3378 | 296 | __ movl(Address(rsi, 4), rbx); |
phh@3378 | 297 | __ movl(Address(rsi, 8), rcx); |
phh@3378 | 298 | __ movl(Address(rsi,12), rdx); |
phh@3378 | 299 | |
phh@3378 | 300 | // |
twisti@1020 | 301 | // Extended cpuid(0x80000005) |
twisti@1020 | 302 | // |
twisti@1020 | 303 | __ bind(ext_cpuid5); |
twisti@1020 | 304 | __ movl(rax, 0x80000005); |
twisti@1020 | 305 | __ cpuid(); |
twisti@1020 | 306 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
twisti@1020 | 307 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 308 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 309 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 310 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 311 | |
twisti@1020 | 312 | // |
twisti@1020 | 313 | // Extended cpuid(0x80000001) |
twisti@1020 | 314 | // |
twisti@1020 | 315 | __ bind(ext_cpuid1); |
twisti@1020 | 316 | __ movl(rax, 0x80000001); |
twisti@1020 | 317 | __ cpuid(); |
twisti@1020 | 318 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
twisti@1020 | 319 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 320 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 321 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 322 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 323 | |
twisti@1020 | 324 | // |
twisti@1020 | 325 | // return |
twisti@1020 | 326 | // |
twisti@1020 | 327 | __ bind(done); |
twisti@1020 | 328 | __ popf(); |
twisti@1020 | 329 | __ pop(rsi); |
twisti@1020 | 330 | __ pop(rbx); |
twisti@1020 | 331 | __ pop(rbp); |
twisti@1020 | 332 | __ ret(0); |
twisti@1020 | 333 | |
twisti@1020 | 334 | # undef __ |
twisti@1020 | 335 | |
twisti@1020 | 336 | return start; |
twisti@1020 | 337 | }; |
twisti@1020 | 338 | }; |
twisti@1020 | 339 | |
twisti@1020 | 340 | |
twisti@1020 | 341 | void VM_Version::get_processor_features() { |
twisti@1020 | 342 | |
twisti@1020 | 343 | _cpu = 4; // 486 by default |
twisti@1020 | 344 | _model = 0; |
twisti@1020 | 345 | _stepping = 0; |
twisti@1020 | 346 | _cpuFeatures = 0; |
twisti@1020 | 347 | _logical_processors_per_package = 1; |
twisti@1020 | 348 | |
twisti@1020 | 349 | if (!Use486InstrsOnly) { |
twisti@1020 | 350 | // Get raw processor info |
twisti@1020 | 351 | getPsrInfo_stub(&_cpuid_info); |
twisti@1020 | 352 | assert_is_initialized(); |
twisti@1020 | 353 | _cpu = extended_cpu_family(); |
twisti@1020 | 354 | _model = extended_cpu_model(); |
twisti@1020 | 355 | _stepping = cpu_stepping(); |
twisti@1020 | 356 | |
twisti@1020 | 357 | if (cpu_family() > 4) { // it supports CPUID |
twisti@1020 | 358 | _cpuFeatures = feature_flags(); |
twisti@1020 | 359 | // Logical processors are only available on P4s and above, |
twisti@1020 | 360 | // and only if hyperthreading is available. |
twisti@1020 | 361 | _logical_processors_per_package = logical_processor_count(); |
twisti@1020 | 362 | } |
twisti@1020 | 363 | } |
twisti@1020 | 364 | |
twisti@1020 | 365 | _supports_cx8 = supports_cmpxchg8(); |
roland@4106 | 366 | // xchg and xadd instructions |
roland@4106 | 367 | _supports_atomic_getset4 = true; |
roland@4106 | 368 | _supports_atomic_getadd4 = true; |
roland@4106 | 369 | LP64_ONLY(_supports_atomic_getset8 = true); |
roland@4106 | 370 | LP64_ONLY(_supports_atomic_getadd8 = true); |
twisti@1020 | 371 | |
twisti@1020 | 372 | #ifdef _LP64 |
twisti@1020 | 373 | // OS should support SSE for x64 and hardware should support at least SSE2. |
twisti@1020 | 374 | if (!VM_Version::supports_sse2()) { |
twisti@1020 | 375 | vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
twisti@1020 | 376 | } |
roland@1495 | 377 | // in 64 bit the use of SSE2 is the minimum |
roland@1495 | 378 | if (UseSSE < 2) UseSSE = 2; |
twisti@1020 | 379 | #endif |
twisti@1020 | 380 | |
kvn@2984 | 381 | #ifdef AMD64 |
kvn@2984 | 382 | // flush_icache_stub have to be generated first. |
kvn@2984 | 383 | // That is why Icache line size is hard coded in ICache class, |
kvn@2984 | 384 | // see icache_x86.hpp. It is also the reason why we can't use |
kvn@2984 | 385 | // clflush instruction in 32-bit VM since it could be running |
kvn@2984 | 386 | // on CPU which does not support it. |
kvn@2984 | 387 | // |
kvn@2984 | 388 | // The only thing we can do is to verify that flushed |
kvn@2984 | 389 | // ICache::line_size has correct value. |
kvn@2984 | 390 | guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
kvn@2984 | 391 | // clflush_size is size in quadwords (8 bytes). |
kvn@2984 | 392 | guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
kvn@2984 | 393 | #endif |
kvn@2984 | 394 | |
twisti@1020 | 395 | // If the OS doesn't support SSE, we can't use this feature even if the HW does |
twisti@1020 | 396 | if (!os::supports_sse()) |
twisti@1020 | 397 | _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
twisti@1020 | 398 | |
twisti@1020 | 399 | if (UseSSE < 4) { |
twisti@1020 | 400 | _cpuFeatures &= ~CPU_SSE4_1; |
twisti@1020 | 401 | _cpuFeatures &= ~CPU_SSE4_2; |
twisti@1020 | 402 | } |
twisti@1020 | 403 | |
twisti@1020 | 404 | if (UseSSE < 3) { |
twisti@1020 | 405 | _cpuFeatures &= ~CPU_SSE3; |
twisti@1020 | 406 | _cpuFeatures &= ~CPU_SSSE3; |
twisti@1020 | 407 | _cpuFeatures &= ~CPU_SSE4A; |
twisti@1020 | 408 | } |
twisti@1020 | 409 | |
twisti@1020 | 410 | if (UseSSE < 2) |
twisti@1020 | 411 | _cpuFeatures &= ~CPU_SSE2; |
twisti@1020 | 412 | |
twisti@1020 | 413 | if (UseSSE < 1) |
twisti@1020 | 414 | _cpuFeatures &= ~CPU_SSE; |
twisti@1020 | 415 | |
kvn@3388 | 416 | if (UseAVX < 2) |
kvn@3388 | 417 | _cpuFeatures &= ~CPU_AVX2; |
kvn@3388 | 418 | |
kvn@3388 | 419 | if (UseAVX < 1) |
kvn@3388 | 420 | _cpuFeatures &= ~CPU_AVX; |
kvn@3388 | 421 | |
kvn@4205 | 422 | if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
kvn@4205 | 423 | _cpuFeatures &= ~CPU_AES; |
kvn@4205 | 424 | |
twisti@1020 | 425 | if (logical_processors_per_package() == 1) { |
twisti@1020 | 426 | // HT processor could be installed on a system which doesn't support HT. |
twisti@1020 | 427 | _cpuFeatures &= ~CPU_HT; |
twisti@1020 | 428 | } |
twisti@1020 | 429 | |
twisti@1020 | 430 | char buf[256]; |
kvn@4205 | 431 | jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
twisti@1020 | 432 | cores_per_cpu(), threads_per_core(), |
twisti@1020 | 433 | cpu_family(), _model, _stepping, |
twisti@1020 | 434 | (supports_cmov() ? ", cmov" : ""), |
twisti@1020 | 435 | (supports_cmpxchg8() ? ", cx8" : ""), |
twisti@1020 | 436 | (supports_fxsr() ? ", fxsr" : ""), |
twisti@1020 | 437 | (supports_mmx() ? ", mmx" : ""), |
twisti@1020 | 438 | (supports_sse() ? ", sse" : ""), |
twisti@1020 | 439 | (supports_sse2() ? ", sse2" : ""), |
twisti@1020 | 440 | (supports_sse3() ? ", sse3" : ""), |
twisti@1020 | 441 | (supports_ssse3()? ", ssse3": ""), |
twisti@1020 | 442 | (supports_sse4_1() ? ", sse4.1" : ""), |
twisti@1020 | 443 | (supports_sse4_2() ? ", sse4.2" : ""), |
twisti@1078 | 444 | (supports_popcnt() ? ", popcnt" : ""), |
kvn@3388 | 445 | (supports_avx() ? ", avx" : ""), |
kvn@3388 | 446 | (supports_avx2() ? ", avx2" : ""), |
kvn@4205 | 447 | (supports_aes() ? ", aes" : ""), |
twisti@1020 | 448 | (supports_mmx_ext() ? ", mmxext" : ""), |
kvn@2761 | 449 | (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
twisti@1210 | 450 | (supports_lzcnt() ? ", lzcnt": ""), |
twisti@1020 | 451 | (supports_sse4a() ? ", sse4a": ""), |
phh@3378 | 452 | (supports_ht() ? ", ht": ""), |
phh@3378 | 453 | (supports_tsc() ? ", tsc": ""), |
phh@3378 | 454 | (supports_tscinv_bit() ? ", tscinvbit": ""), |
phh@3378 | 455 | (supports_tscinv() ? ", tscinv": "")); |
twisti@1020 | 456 | _features_str = strdup(buf); |
twisti@1020 | 457 | |
twisti@1020 | 458 | // UseSSE is set to the smaller of what hardware supports and what |
twisti@1020 | 459 | // the command line requires. I.e., you cannot set UseSSE to 2 on |
twisti@1020 | 460 | // older Pentiums which do not support it. |
kvn@3388 | 461 | if (UseSSE > 4) UseSSE=4; |
kvn@3388 | 462 | if (UseSSE < 0) UseSSE=0; |
kvn@3388 | 463 | if (!supports_sse4_1()) // Drop to 3 if no SSE4 support |
twisti@1020 | 464 | UseSSE = MIN2((intx)3,UseSSE); |
kvn@3388 | 465 | if (!supports_sse3()) // Drop to 2 if no SSE3 support |
twisti@1020 | 466 | UseSSE = MIN2((intx)2,UseSSE); |
kvn@3388 | 467 | if (!supports_sse2()) // Drop to 1 if no SSE2 support |
twisti@1020 | 468 | UseSSE = MIN2((intx)1,UseSSE); |
kvn@3388 | 469 | if (!supports_sse ()) // Drop to 0 if no SSE support |
twisti@1020 | 470 | UseSSE = 0; |
twisti@1020 | 471 | |
kvn@3388 | 472 | if (UseAVX > 2) UseAVX=2; |
kvn@3388 | 473 | if (UseAVX < 0) UseAVX=0; |
kvn@3388 | 474 | if (!supports_avx2()) // Drop to 1 if no AVX2 support |
kvn@3388 | 475 | UseAVX = MIN2((intx)1,UseAVX); |
kvn@3388 | 476 | if (!supports_avx ()) // Drop to 0 if no AVX support |
kvn@3388 | 477 | UseAVX = 0; |
kvn@3388 | 478 | |
kvn@4205 | 479 | // Use AES instructions if available. |
kvn@4205 | 480 | if (supports_aes()) { |
kvn@4205 | 481 | if (FLAG_IS_DEFAULT(UseAES)) { |
kvn@4205 | 482 | UseAES = true; |
kvn@4205 | 483 | } |
kvn@4205 | 484 | } else if (UseAES) { |
kvn@4205 | 485 | if (!FLAG_IS_DEFAULT(UseAES)) |
kvn@4205 | 486 | warning("AES instructions not available on this CPU"); |
kvn@4205 | 487 | FLAG_SET_DEFAULT(UseAES, false); |
kvn@4205 | 488 | } |
kvn@4205 | 489 | |
kvn@4205 | 490 | // The AES intrinsic stubs require AES instruction support (of course) |
kvn@4205 | 491 | // but also require AVX mode for misaligned SSE access |
kvn@4205 | 492 | if (UseAES && (UseAVX > 0)) { |
kvn@4205 | 493 | if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kvn@4205 | 494 | UseAESIntrinsics = true; |
kvn@4205 | 495 | } |
kvn@4205 | 496 | } else if (UseAESIntrinsics) { |
kvn@4205 | 497 | if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) |
kvn@4205 | 498 | warning("AES intrinsics not available on this CPU"); |
kvn@4205 | 499 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kvn@4205 | 500 | } |
kvn@4205 | 501 | |
kvn@3882 | 502 | #ifdef COMPILER2 |
kvn@3882 | 503 | if (UseFPUForSpilling) { |
kvn@3882 | 504 | if (UseSSE < 2) { |
kvn@3882 | 505 | // Only supported with SSE2+ |
kvn@3882 | 506 | FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
kvn@3882 | 507 | } |
kvn@3882 | 508 | } |
kvn@3882 | 509 | if (MaxVectorSize > 0) { |
kvn@3882 | 510 | if (!is_power_of_2(MaxVectorSize)) { |
kvn@3882 | 511 | warning("MaxVectorSize must be a power of 2"); |
kvn@3882 | 512 | FLAG_SET_DEFAULT(MaxVectorSize, 32); |
kvn@3882 | 513 | } |
kvn@3882 | 514 | if (MaxVectorSize > 32) { |
kvn@3882 | 515 | FLAG_SET_DEFAULT(MaxVectorSize, 32); |
kvn@3882 | 516 | } |
kvn@3882 | 517 | if (MaxVectorSize > 16 && UseAVX == 0) { |
kvn@3882 | 518 | // Only supported with AVX+ |
kvn@3882 | 519 | FLAG_SET_DEFAULT(MaxVectorSize, 16); |
kvn@3882 | 520 | } |
kvn@3882 | 521 | if (UseSSE < 2) { |
kvn@3882 | 522 | // Only supported with SSE2+ |
kvn@3882 | 523 | FLAG_SET_DEFAULT(MaxVectorSize, 0); |
kvn@3882 | 524 | } |
kvn@3882 | 525 | } |
kvn@3882 | 526 | #endif |
kvn@3882 | 527 | |
twisti@1020 | 528 | // On new cpus instructions which update whole XMM register should be used |
twisti@1020 | 529 | // to prevent partial register stall due to dependencies on high half. |
twisti@1020 | 530 | // |
twisti@1020 | 531 | // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
twisti@1020 | 532 | // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
twisti@1020 | 533 | // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
twisti@1020 | 534 | // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
twisti@1020 | 535 | |
twisti@1020 | 536 | if( is_amd() ) { // AMD cpus specific settings |
twisti@1020 | 537 | if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 538 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 539 | UseAddressNop = true; |
twisti@1020 | 540 | } |
twisti@1020 | 541 | if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
twisti@1020 | 542 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 543 | UseNewLongLShift = true; |
twisti@1020 | 544 | } |
twisti@1020 | 545 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 546 | if( supports_sse4a() ) { |
twisti@1020 | 547 | UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
twisti@1020 | 548 | } else { |
twisti@1020 | 549 | UseXmmLoadAndClearUpper = false; |
twisti@1020 | 550 | } |
twisti@1020 | 551 | } |
twisti@1020 | 552 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 553 | if( supports_sse4a() ) { |
twisti@1020 | 554 | UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
twisti@1020 | 555 | } else { |
twisti@1020 | 556 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 557 | } |
twisti@1020 | 558 | } |
twisti@1020 | 559 | if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
twisti@1020 | 560 | if( supports_sse4a() ) { |
twisti@1020 | 561 | UseXmmI2F = true; |
twisti@1020 | 562 | } else { |
twisti@1020 | 563 | UseXmmI2F = false; |
twisti@1020 | 564 | } |
twisti@1020 | 565 | } |
twisti@1020 | 566 | if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
twisti@1020 | 567 | if( supports_sse4a() ) { |
twisti@1020 | 568 | UseXmmI2D = true; |
twisti@1020 | 569 | } else { |
twisti@1020 | 570 | UseXmmI2D = false; |
twisti@1020 | 571 | } |
twisti@1020 | 572 | } |
kvn@2688 | 573 | if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
kvn@2688 | 574 | if( supports_sse4_2() && UseSSE >= 4 ) { |
kvn@2688 | 575 | UseSSE42Intrinsics = true; |
kvn@2688 | 576 | } |
kvn@2688 | 577 | } |
twisti@1210 | 578 | |
twisti@1210 | 579 | // Use count leading zeros count instruction if available. |
twisti@1210 | 580 | if (supports_lzcnt()) { |
twisti@1210 | 581 | if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
twisti@1210 | 582 | UseCountLeadingZerosInstruction = true; |
twisti@1210 | 583 | } |
twisti@1210 | 584 | } |
kvn@2640 | 585 | |
kvn@2808 | 586 | // some defaults for AMD family 15h |
kvn@2808 | 587 | if ( cpu_family() == 0x15 ) { |
kvn@2808 | 588 | // On family 15h processors default is no sw prefetch |
kvn@2640 | 589 | if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
kvn@2640 | 590 | AllocatePrefetchStyle = 0; |
kvn@2640 | 591 | } |
kvn@2808 | 592 | // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
kvn@2808 | 593 | if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
kvn@2808 | 594 | AllocatePrefetchInstr = 3; |
kvn@2808 | 595 | } |
kvn@2808 | 596 | // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
kvn@4105 | 597 | if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
kvn@2808 | 598 | UseXMMForArrayCopy = true; |
kvn@2808 | 599 | } |
kvn@4105 | 600 | if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
kvn@2808 | 601 | UseUnalignedLoadStores = true; |
kvn@2808 | 602 | } |
kvn@2640 | 603 | } |
kvn@2808 | 604 | |
kvn@3882 | 605 | #ifdef COMPILER2 |
kvn@3882 | 606 | if (MaxVectorSize > 16) { |
kvn@3882 | 607 | // Limit vectors size to 16 bytes on current AMD cpus. |
kvn@3882 | 608 | FLAG_SET_DEFAULT(MaxVectorSize, 16); |
kvn@3882 | 609 | } |
kvn@3882 | 610 | #endif // COMPILER2 |
twisti@1020 | 611 | } |
twisti@1020 | 612 | |
twisti@1020 | 613 | if( is_intel() ) { // Intel cpus specific settings |
twisti@1020 | 614 | if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
twisti@1020 | 615 | UseStoreImmI16 = false; // don't use it on Intel cpus |
twisti@1020 | 616 | } |
twisti@1020 | 617 | if( cpu_family() == 6 || cpu_family() == 15 ) { |
twisti@1020 | 618 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 619 | // Use it on all Intel cpus starting from PentiumPro |
twisti@1020 | 620 | UseAddressNop = true; |
twisti@1020 | 621 | } |
twisti@1020 | 622 | } |
twisti@1020 | 623 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 624 | UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
twisti@1020 | 625 | } |
twisti@1020 | 626 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 627 | if( supports_sse3() ) { |
twisti@1020 | 628 | UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
twisti@1020 | 629 | } else { |
twisti@1020 | 630 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 631 | } |
twisti@1020 | 632 | } |
twisti@1020 | 633 | if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
twisti@1020 | 634 | #ifdef COMPILER2 |
twisti@1020 | 635 | if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
twisti@1020 | 636 | // For new Intel cpus do the next optimization: |
twisti@1020 | 637 | // don't align the beginning of a loop if there are enough instructions |
twisti@1020 | 638 | // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
twisti@1020 | 639 | // in current fetch line (OptoLoopAlignment) or the padding |
twisti@1020 | 640 | // is big (> MaxLoopPad). |
twisti@1020 | 641 | // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
twisti@1020 | 642 | // generated NOP instructions. 11 is the largest size of one |
twisti@1020 | 643 | // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
twisti@1020 | 644 | MaxLoopPad = 11; |
twisti@1020 | 645 | } |
twisti@1020 | 646 | #endif // COMPILER2 |
kvn@4105 | 647 | if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
twisti@1020 | 648 | UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
twisti@1020 | 649 | } |
kvn@4105 | 650 | if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
kvn@4105 | 651 | if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
twisti@1020 | 652 | UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
twisti@1020 | 653 | } |
twisti@1020 | 654 | } |
kvn@4105 | 655 | if (supports_sse4_2() && UseSSE >= 4) { |
kvn@4105 | 656 | if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
cfang@1116 | 657 | UseSSE42Intrinsics = true; |
cfang@1116 | 658 | } |
cfang@1116 | 659 | } |
twisti@1020 | 660 | } |
twisti@1020 | 661 | } |
twisti@1020 | 662 | |
twisti@1078 | 663 | // Use population count instruction if available. |
twisti@1078 | 664 | if (supports_popcnt()) { |
twisti@1078 | 665 | if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
twisti@1078 | 666 | UsePopCountInstruction = true; |
twisti@1078 | 667 | } |
kvn@3388 | 668 | } else if (UsePopCountInstruction) { |
kvn@3388 | 669 | warning("POPCNT instruction is not available on this CPU"); |
kvn@3388 | 670 | FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
twisti@1078 | 671 | } |
twisti@1078 | 672 | |
kvn@4105 | 673 | #ifdef COMPILER2 |
kvn@4105 | 674 | if (FLAG_IS_DEFAULT(AlignVector)) { |
kvn@4105 | 675 | // Modern processors allow misaligned memory operations for vectors. |
kvn@4105 | 676 | AlignVector = !UseUnalignedLoadStores; |
kvn@4105 | 677 | } |
kvn@4105 | 678 | #endif // COMPILER2 |
kvn@4105 | 679 | |
twisti@1020 | 680 | assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 681 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 682 | |
twisti@1020 | 683 | // set valid Prefetch instruction |
twisti@1020 | 684 | if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
twisti@1020 | 685 | if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
kvn@2761 | 686 | if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
kvn@2761 | 687 | if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; |
twisti@1020 | 688 | |
twisti@1020 | 689 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
twisti@1020 | 690 | if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
kvn@2761 | 691 | if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
kvn@2761 | 692 | if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; |
twisti@1020 | 693 | |
twisti@1020 | 694 | // Allocation prefetch settings |
kvn@3052 | 695 | intx cache_line_size = prefetch_data_size(); |
twisti@1020 | 696 | if( cache_line_size > AllocatePrefetchStepSize ) |
twisti@1020 | 697 | AllocatePrefetchStepSize = cache_line_size; |
kvn@3052 | 698 | |
twisti@1020 | 699 | assert(AllocatePrefetchLines > 0, "invalid value"); |
kvn@3052 | 700 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 701 | AllocatePrefetchLines = 3; |
kvn@3052 | 702 | assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
kvn@3052 | 703 | if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 704 | AllocateInstancePrefetchLines = 1; |
twisti@1020 | 705 | |
twisti@1020 | 706 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
twisti@1020 | 707 | AllocatePrefetchStyle = allocate_prefetch_style(); |
twisti@1020 | 708 | |
kvn@1977 | 709 | if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
kvn@1977 | 710 | if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core |
twisti@1020 | 711 | #ifdef _LP64 |
kvn@1977 | 712 | AllocatePrefetchDistance = 384; |
twisti@1020 | 713 | #else |
kvn@1977 | 714 | AllocatePrefetchDistance = 320; |
twisti@1020 | 715 | #endif |
kvn@1977 | 716 | } |
kvn@1977 | 717 | if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus |
kvn@1977 | 718 | AllocatePrefetchDistance = 192; |
kvn@1977 | 719 | AllocatePrefetchLines = 4; |
never@2085 | 720 | #ifdef COMPILER2 |
never@2085 | 721 | if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
never@2085 | 722 | FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
never@2085 | 723 | } |
never@2085 | 724 | #endif |
kvn@1977 | 725 | } |
twisti@1020 | 726 | } |
twisti@1020 | 727 | assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
twisti@1020 | 728 | |
twisti@1020 | 729 | #ifdef _LP64 |
twisti@1020 | 730 | // Prefetch settings |
twisti@1020 | 731 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
twisti@1020 | 732 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
twisti@1020 | 733 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
twisti@1020 | 734 | #endif |
twisti@1020 | 735 | |
twisti@1020 | 736 | #ifndef PRODUCT |
twisti@1020 | 737 | if (PrintMiscellaneous && Verbose) { |
twisti@1020 | 738 | tty->print_cr("Logical CPUs per core: %u", |
twisti@1020 | 739 | logical_processors_per_package()); |
kvn@3388 | 740 | tty->print("UseSSE=%d",UseSSE); |
kvn@3388 | 741 | if (UseAVX > 0) { |
kvn@3388 | 742 | tty->print(" UseAVX=%d",UseAVX); |
kvn@3388 | 743 | } |
kvn@4205 | 744 | if (UseAES) { |
kvn@4205 | 745 | tty->print(" UseAES=1"); |
kvn@4205 | 746 | } |
kvn@3388 | 747 | tty->cr(); |
kvn@3052 | 748 | tty->print("Allocation"); |
kvn@2761 | 749 | if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
kvn@3052 | 750 | tty->print_cr(": no prefetching"); |
twisti@1020 | 751 | } else { |
kvn@3052 | 752 | tty->print(" prefetching: "); |
kvn@2761 | 753 | if (UseSSE == 0 && supports_3dnow_prefetch()) { |
twisti@1020 | 754 | tty->print("PREFETCHW"); |
twisti@1020 | 755 | } else if (UseSSE >= 1) { |
twisti@1020 | 756 | if (AllocatePrefetchInstr == 0) { |
twisti@1020 | 757 | tty->print("PREFETCHNTA"); |
twisti@1020 | 758 | } else if (AllocatePrefetchInstr == 1) { |
twisti@1020 | 759 | tty->print("PREFETCHT0"); |
twisti@1020 | 760 | } else if (AllocatePrefetchInstr == 2) { |
twisti@1020 | 761 | tty->print("PREFETCHT2"); |
twisti@1020 | 762 | } else if (AllocatePrefetchInstr == 3) { |
twisti@1020 | 763 | tty->print("PREFETCHW"); |
twisti@1020 | 764 | } |
twisti@1020 | 765 | } |
twisti@1020 | 766 | if (AllocatePrefetchLines > 1) { |
kvn@3052 | 767 | tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
twisti@1020 | 768 | } else { |
kvn@3052 | 769 | tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
twisti@1020 | 770 | } |
twisti@1020 | 771 | } |
twisti@1020 | 772 | |
twisti@1020 | 773 | if (PrefetchCopyIntervalInBytes > 0) { |
twisti@1020 | 774 | tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); |
twisti@1020 | 775 | } |
twisti@1020 | 776 | if (PrefetchScanIntervalInBytes > 0) { |
twisti@1020 | 777 | tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); |
twisti@1020 | 778 | } |
twisti@1020 | 779 | if (PrefetchFieldsAhead > 0) { |
twisti@1020 | 780 | tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); |
twisti@1020 | 781 | } |
twisti@1020 | 782 | } |
twisti@1020 | 783 | #endif // !PRODUCT |
twisti@1020 | 784 | } |
twisti@1020 | 785 | |
twisti@1020 | 786 | void VM_Version::initialize() { |
twisti@1020 | 787 | ResourceMark rm; |
twisti@1020 | 788 | // Making this stub must be FIRST use of assembler |
twisti@1020 | 789 | |
twisti@1020 | 790 | stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
twisti@1020 | 791 | if (stub_blob == NULL) { |
twisti@1020 | 792 | vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
twisti@1020 | 793 | } |
twisti@2103 | 794 | CodeBuffer c(stub_blob); |
twisti@1020 | 795 | VM_Version_StubGenerator g(&c); |
twisti@1020 | 796 | getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
twisti@1020 | 797 | g.generate_getPsrInfo()); |
twisti@1020 | 798 | |
twisti@1020 | 799 | get_processor_features(); |
twisti@1020 | 800 | } |