Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/x86/vm/vm_version_x86.cpp@a3ecd773a7b9
src/cpu/x86/vm/vm_version_x86.cpp
Wed, 24 Oct 2012 14:33:22 -0700
- author
- kvn
- date
- Wed, 24 Oct 2012 14:33:22 -0700
- changeset 4205
- a3ecd773a7b9
- parent 4106
- 7eca5de9e0b6
- child 4254
- dbeaeee28bc2
- permissions
- -rw-r--r--
7184394: add intrinsics to use AES instructions
Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_x86.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37 #ifdef TARGET_OS_FAMILY_windows
38 # include "os_windows.inline.hpp"
39 #endif
40 #ifdef TARGET_OS_FAMILY_bsd
41 # include "os_bsd.inline.hpp"
42 #endif
45 int VM_Version::_cpu;
46 int VM_Version::_model;
47 int VM_Version::_stepping;
48 int VM_Version::_cpuFeatures;
49 const char* VM_Version::_features_str = "";
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
52 static BufferBlob* stub_blob;
53 static const int stub_size = 550;
55 extern "C" {
56 typedef void (*getPsrInfo_stub_t)(void*);
57 }
58 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
61 class VM_Version_StubGenerator: public StubCodeGenerator {
62 public:
64 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
66 address generate_getPsrInfo() {
67 // Flags to test CPU type.
68 const uint32_t HS_EFL_AC = 0x40000;
69 const uint32_t HS_EFL_ID = 0x200000;
70 // Values for when we don't have a CPUID instruction.
71 const int CPU_FAMILY_SHIFT = 8;
72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
76 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
79 # define __ _masm->
81 address start = __ pc();
83 //
84 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
85 //
86 // LP64: rcx and rdx are first and second argument registers on windows
88 __ push(rbp);
89 #ifdef _LP64
90 __ mov(rbp, c_rarg0); // cpuid_info address
91 #else
92 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
93 #endif
94 __ push(rbx);
95 __ push(rsi);
96 __ pushf(); // preserve rbx, and flags
97 __ pop(rax);
98 __ push(rax);
99 __ mov(rcx, rax);
100 //
101 // if we are unable to change the AC flag, we have a 386
102 //
103 __ xorl(rax, HS_EFL_AC);
104 __ push(rax);
105 __ popf();
106 __ pushf();
107 __ pop(rax);
108 __ cmpptr(rax, rcx);
109 __ jccb(Assembler::notEqual, detect_486);
111 __ movl(rax, CPU_FAMILY_386);
112 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
113 __ jmp(done);
115 //
116 // If we are unable to change the ID flag, we have a 486 which does
117 // not support the "cpuid" instruction.
118 //
119 __ bind(detect_486);
120 __ mov(rax, rcx);
121 __ xorl(rax, HS_EFL_ID);
122 __ push(rax);
123 __ popf();
124 __ pushf();
125 __ pop(rax);
126 __ cmpptr(rcx, rax);
127 __ jccb(Assembler::notEqual, detect_586);
129 __ bind(cpu486);
130 __ movl(rax, CPU_FAMILY_486);
131 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
132 __ jmp(done);
134 //
135 // At this point, we have a chip which supports the "cpuid" instruction
136 //
137 __ bind(detect_586);
138 __ xorl(rax, rax);
139 __ cpuid();
140 __ orl(rax, rax);
141 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
142 // value of at least 1, we give up and
143 // assume a 486
144 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
145 __ movl(Address(rsi, 0), rax);
146 __ movl(Address(rsi, 4), rbx);
147 __ movl(Address(rsi, 8), rcx);
148 __ movl(Address(rsi,12), rdx);
150 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
151 __ jccb(Assembler::belowEqual, std_cpuid4);
153 //
154 // cpuid(0xB) Processor Topology
155 //
156 __ movl(rax, 0xb);
157 __ xorl(rcx, rcx); // Threads level
158 __ cpuid();
160 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
161 __ movl(Address(rsi, 0), rax);
162 __ movl(Address(rsi, 4), rbx);
163 __ movl(Address(rsi, 8), rcx);
164 __ movl(Address(rsi,12), rdx);
166 __ movl(rax, 0xb);
167 __ movl(rcx, 1); // Cores level
168 __ cpuid();
169 __ push(rax);
170 __ andl(rax, 0x1f); // Determine if valid topology level
171 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
172 __ andl(rax, 0xffff);
173 __ pop(rax);
174 __ jccb(Assembler::equal, std_cpuid4);
176 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
177 __ movl(Address(rsi, 0), rax);
178 __ movl(Address(rsi, 4), rbx);
179 __ movl(Address(rsi, 8), rcx);
180 __ movl(Address(rsi,12), rdx);
182 __ movl(rax, 0xb);
183 __ movl(rcx, 2); // Packages level
184 __ cpuid();
185 __ push(rax);
186 __ andl(rax, 0x1f); // Determine if valid topology level
187 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
188 __ andl(rax, 0xffff);
189 __ pop(rax);
190 __ jccb(Assembler::equal, std_cpuid4);
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
193 __ movl(Address(rsi, 0), rax);
194 __ movl(Address(rsi, 4), rbx);
195 __ movl(Address(rsi, 8), rcx);
196 __ movl(Address(rsi,12), rdx);
198 //
199 // cpuid(0x4) Deterministic cache params
200 //
201 __ bind(std_cpuid4);
202 __ movl(rax, 4);
203 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
204 __ jccb(Assembler::greater, std_cpuid1);
206 __ xorl(rcx, rcx); // L1 cache
207 __ cpuid();
208 __ push(rax);
209 __ andl(rax, 0x1f); // Determine if valid cache parameters used
210 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
211 __ pop(rax);
212 __ jccb(Assembler::equal, std_cpuid1);
214 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
215 __ movl(Address(rsi, 0), rax);
216 __ movl(Address(rsi, 4), rbx);
217 __ movl(Address(rsi, 8), rcx);
218 __ movl(Address(rsi,12), rdx);
220 //
221 // Standard cpuid(0x1)
222 //
223 __ bind(std_cpuid1);
224 __ movl(rax, 1);
225 __ cpuid();
226 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
227 __ movl(Address(rsi, 0), rax);
228 __ movl(Address(rsi, 4), rbx);
229 __ movl(Address(rsi, 8), rcx);
230 __ movl(Address(rsi,12), rdx);
232 //
233 // Check if OS has enabled XGETBV instruction to access XCR0
234 // (OSXSAVE feature flag) and CPU supports AVX
235 //
236 __ andl(rcx, 0x18000000);
237 __ cmpl(rcx, 0x18000000);
238 __ jccb(Assembler::notEqual, sef_cpuid);
240 //
241 // XCR0, XFEATURE_ENABLED_MASK register
242 //
243 __ xorl(rcx, rcx); // zero for XCR0 register
244 __ xgetbv();
245 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
246 __ movl(Address(rsi, 0), rax);
247 __ movl(Address(rsi, 4), rdx);
249 //
250 // cpuid(0x7) Structured Extended Features
251 //
252 __ bind(sef_cpuid);
253 __ movl(rax, 7);
254 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
255 __ jccb(Assembler::greater, ext_cpuid);
257 __ xorl(rcx, rcx);
258 __ cpuid();
259 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
260 __ movl(Address(rsi, 0), rax);
261 __ movl(Address(rsi, 4), rbx);
263 //
264 // Extended cpuid(0x80000000)
265 //
266 __ bind(ext_cpuid);
267 __ movl(rax, 0x80000000);
268 __ cpuid();
269 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
270 __ jcc(Assembler::belowEqual, done);
271 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid1);
273 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
274 __ jccb(Assembler::belowEqual, ext_cpuid5);
275 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
276 __ jccb(Assembler::belowEqual, ext_cpuid7);
277 //
278 // Extended cpuid(0x80000008)
279 //
280 __ movl(rax, 0x80000008);
281 __ cpuid();
282 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
283 __ movl(Address(rsi, 0), rax);
284 __ movl(Address(rsi, 4), rbx);
285 __ movl(Address(rsi, 8), rcx);
286 __ movl(Address(rsi,12), rdx);
288 //
289 // Extended cpuid(0x80000007)
290 //
291 __ bind(ext_cpuid7);
292 __ movl(rax, 0x80000007);
293 __ cpuid();
294 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
295 __ movl(Address(rsi, 0), rax);
296 __ movl(Address(rsi, 4), rbx);
297 __ movl(Address(rsi, 8), rcx);
298 __ movl(Address(rsi,12), rdx);
300 //
301 // Extended cpuid(0x80000005)
302 //
303 __ bind(ext_cpuid5);
304 __ movl(rax, 0x80000005);
305 __ cpuid();
306 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
307 __ movl(Address(rsi, 0), rax);
308 __ movl(Address(rsi, 4), rbx);
309 __ movl(Address(rsi, 8), rcx);
310 __ movl(Address(rsi,12), rdx);
312 //
313 // Extended cpuid(0x80000001)
314 //
315 __ bind(ext_cpuid1);
316 __ movl(rax, 0x80000001);
317 __ cpuid();
318 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
319 __ movl(Address(rsi, 0), rax);
320 __ movl(Address(rsi, 4), rbx);
321 __ movl(Address(rsi, 8), rcx);
322 __ movl(Address(rsi,12), rdx);
324 //
325 // return
326 //
327 __ bind(done);
328 __ popf();
329 __ pop(rsi);
330 __ pop(rbx);
331 __ pop(rbp);
332 __ ret(0);
334 # undef __
336 return start;
337 };
338 };
341 void VM_Version::get_processor_features() {
343 _cpu = 4; // 486 by default
344 _model = 0;
345 _stepping = 0;
346 _cpuFeatures = 0;
347 _logical_processors_per_package = 1;
349 if (!Use486InstrsOnly) {
350 // Get raw processor info
351 getPsrInfo_stub(&_cpuid_info);
352 assert_is_initialized();
353 _cpu = extended_cpu_family();
354 _model = extended_cpu_model();
355 _stepping = cpu_stepping();
357 if (cpu_family() > 4) { // it supports CPUID
358 _cpuFeatures = feature_flags();
359 // Logical processors are only available on P4s and above,
360 // and only if hyperthreading is available.
361 _logical_processors_per_package = logical_processor_count();
362 }
363 }
365 _supports_cx8 = supports_cmpxchg8();
366 // xchg and xadd instructions
367 _supports_atomic_getset4 = true;
368 _supports_atomic_getadd4 = true;
369 LP64_ONLY(_supports_atomic_getset8 = true);
370 LP64_ONLY(_supports_atomic_getadd8 = true);
372 #ifdef _LP64
373 // OS should support SSE for x64 and hardware should support at least SSE2.
374 if (!VM_Version::supports_sse2()) {
375 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
376 }
377 // in 64 bit the use of SSE2 is the minimum
378 if (UseSSE < 2) UseSSE = 2;
379 #endif
381 #ifdef AMD64
382 // flush_icache_stub have to be generated first.
383 // That is why Icache line size is hard coded in ICache class,
384 // see icache_x86.hpp. It is also the reason why we can't use
385 // clflush instruction in 32-bit VM since it could be running
386 // on CPU which does not support it.
387 //
388 // The only thing we can do is to verify that flushed
389 // ICache::line_size has correct value.
390 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
391 // clflush_size is size in quadwords (8 bytes).
392 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
393 #endif
395 // If the OS doesn't support SSE, we can't use this feature even if the HW does
396 if (!os::supports_sse())
397 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
399 if (UseSSE < 4) {
400 _cpuFeatures &= ~CPU_SSE4_1;
401 _cpuFeatures &= ~CPU_SSE4_2;
402 }
404 if (UseSSE < 3) {
405 _cpuFeatures &= ~CPU_SSE3;
406 _cpuFeatures &= ~CPU_SSSE3;
407 _cpuFeatures &= ~CPU_SSE4A;
408 }
410 if (UseSSE < 2)
411 _cpuFeatures &= ~CPU_SSE2;
413 if (UseSSE < 1)
414 _cpuFeatures &= ~CPU_SSE;
416 if (UseAVX < 2)
417 _cpuFeatures &= ~CPU_AVX2;
419 if (UseAVX < 1)
420 _cpuFeatures &= ~CPU_AVX;
422 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
423 _cpuFeatures &= ~CPU_AES;
425 if (logical_processors_per_package() == 1) {
426 // HT processor could be installed on a system which doesn't support HT.
427 _cpuFeatures &= ~CPU_HT;
428 }
430 char buf[256];
431 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
432 cores_per_cpu(), threads_per_core(),
433 cpu_family(), _model, _stepping,
434 (supports_cmov() ? ", cmov" : ""),
435 (supports_cmpxchg8() ? ", cx8" : ""),
436 (supports_fxsr() ? ", fxsr" : ""),
437 (supports_mmx() ? ", mmx" : ""),
438 (supports_sse() ? ", sse" : ""),
439 (supports_sse2() ? ", sse2" : ""),
440 (supports_sse3() ? ", sse3" : ""),
441 (supports_ssse3()? ", ssse3": ""),
442 (supports_sse4_1() ? ", sse4.1" : ""),
443 (supports_sse4_2() ? ", sse4.2" : ""),
444 (supports_popcnt() ? ", popcnt" : ""),
445 (supports_avx() ? ", avx" : ""),
446 (supports_avx2() ? ", avx2" : ""),
447 (supports_aes() ? ", aes" : ""),
448 (supports_mmx_ext() ? ", mmxext" : ""),
449 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
450 (supports_lzcnt() ? ", lzcnt": ""),
451 (supports_sse4a() ? ", sse4a": ""),
452 (supports_ht() ? ", ht": ""),
453 (supports_tsc() ? ", tsc": ""),
454 (supports_tscinv_bit() ? ", tscinvbit": ""),
455 (supports_tscinv() ? ", tscinv": ""));
456 _features_str = strdup(buf);
458 // UseSSE is set to the smaller of what hardware supports and what
459 // the command line requires. I.e., you cannot set UseSSE to 2 on
460 // older Pentiums which do not support it.
461 if (UseSSE > 4) UseSSE=4;
462 if (UseSSE < 0) UseSSE=0;
463 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
464 UseSSE = MIN2((intx)3,UseSSE);
465 if (!supports_sse3()) // Drop to 2 if no SSE3 support
466 UseSSE = MIN2((intx)2,UseSSE);
467 if (!supports_sse2()) // Drop to 1 if no SSE2 support
468 UseSSE = MIN2((intx)1,UseSSE);
469 if (!supports_sse ()) // Drop to 0 if no SSE support
470 UseSSE = 0;
472 if (UseAVX > 2) UseAVX=2;
473 if (UseAVX < 0) UseAVX=0;
474 if (!supports_avx2()) // Drop to 1 if no AVX2 support
475 UseAVX = MIN2((intx)1,UseAVX);
476 if (!supports_avx ()) // Drop to 0 if no AVX support
477 UseAVX = 0;
479 // Use AES instructions if available.
480 if (supports_aes()) {
481 if (FLAG_IS_DEFAULT(UseAES)) {
482 UseAES = true;
483 }
484 } else if (UseAES) {
485 if (!FLAG_IS_DEFAULT(UseAES))
486 warning("AES instructions not available on this CPU");
487 FLAG_SET_DEFAULT(UseAES, false);
488 }
490 // The AES intrinsic stubs require AES instruction support (of course)
491 // but also require AVX mode for misaligned SSE access
492 if (UseAES && (UseAVX > 0)) {
493 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
494 UseAESIntrinsics = true;
495 }
496 } else if (UseAESIntrinsics) {
497 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
498 warning("AES intrinsics not available on this CPU");
499 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
500 }
502 #ifdef COMPILER2
503 if (UseFPUForSpilling) {
504 if (UseSSE < 2) {
505 // Only supported with SSE2+
506 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
507 }
508 }
509 if (MaxVectorSize > 0) {
510 if (!is_power_of_2(MaxVectorSize)) {
511 warning("MaxVectorSize must be a power of 2");
512 FLAG_SET_DEFAULT(MaxVectorSize, 32);
513 }
514 if (MaxVectorSize > 32) {
515 FLAG_SET_DEFAULT(MaxVectorSize, 32);
516 }
517 if (MaxVectorSize > 16 && UseAVX == 0) {
518 // Only supported with AVX+
519 FLAG_SET_DEFAULT(MaxVectorSize, 16);
520 }
521 if (UseSSE < 2) {
522 // Only supported with SSE2+
523 FLAG_SET_DEFAULT(MaxVectorSize, 0);
524 }
525 }
526 #endif
528 // On new cpus instructions which update whole XMM register should be used
529 // to prevent partial register stall due to dependencies on high half.
530 //
531 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
532 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
533 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
534 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
536 if( is_amd() ) { // AMD cpus specific settings
537 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
538 // Use it on new AMD cpus starting from Opteron.
539 UseAddressNop = true;
540 }
541 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
542 // Use it on new AMD cpus starting from Opteron.
543 UseNewLongLShift = true;
544 }
545 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
546 if( supports_sse4a() ) {
547 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
548 } else {
549 UseXmmLoadAndClearUpper = false;
550 }
551 }
552 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
553 if( supports_sse4a() ) {
554 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
555 } else {
556 UseXmmRegToRegMoveAll = false;
557 }
558 }
559 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
560 if( supports_sse4a() ) {
561 UseXmmI2F = true;
562 } else {
563 UseXmmI2F = false;
564 }
565 }
566 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
567 if( supports_sse4a() ) {
568 UseXmmI2D = true;
569 } else {
570 UseXmmI2D = false;
571 }
572 }
573 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
574 if( supports_sse4_2() && UseSSE >= 4 ) {
575 UseSSE42Intrinsics = true;
576 }
577 }
579 // Use count leading zeros count instruction if available.
580 if (supports_lzcnt()) {
581 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
582 UseCountLeadingZerosInstruction = true;
583 }
584 }
586 // some defaults for AMD family 15h
587 if ( cpu_family() == 0x15 ) {
588 // On family 15h processors default is no sw prefetch
589 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
590 AllocatePrefetchStyle = 0;
591 }
592 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
593 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
594 AllocatePrefetchInstr = 3;
595 }
596 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
597 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
598 UseXMMForArrayCopy = true;
599 }
600 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
601 UseUnalignedLoadStores = true;
602 }
603 }
605 #ifdef COMPILER2
606 if (MaxVectorSize > 16) {
607 // Limit vectors size to 16 bytes on current AMD cpus.
608 FLAG_SET_DEFAULT(MaxVectorSize, 16);
609 }
610 #endif // COMPILER2
611 }
613 if( is_intel() ) { // Intel cpus specific settings
614 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
615 UseStoreImmI16 = false; // don't use it on Intel cpus
616 }
617 if( cpu_family() == 6 || cpu_family() == 15 ) {
618 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
619 // Use it on all Intel cpus starting from PentiumPro
620 UseAddressNop = true;
621 }
622 }
623 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
624 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
625 }
626 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
627 if( supports_sse3() ) {
628 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
629 } else {
630 UseXmmRegToRegMoveAll = false;
631 }
632 }
633 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
634 #ifdef COMPILER2
635 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
636 // For new Intel cpus do the next optimization:
637 // don't align the beginning of a loop if there are enough instructions
638 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
639 // in current fetch line (OptoLoopAlignment) or the padding
640 // is big (> MaxLoopPad).
641 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
642 // generated NOP instructions. 11 is the largest size of one
643 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
644 MaxLoopPad = 11;
645 }
646 #endif // COMPILER2
647 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
648 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
649 }
650 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
651 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
652 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
653 }
654 }
655 if (supports_sse4_2() && UseSSE >= 4) {
656 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
657 UseSSE42Intrinsics = true;
658 }
659 }
660 }
661 }
663 // Use population count instruction if available.
664 if (supports_popcnt()) {
665 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
666 UsePopCountInstruction = true;
667 }
668 } else if (UsePopCountInstruction) {
669 warning("POPCNT instruction is not available on this CPU");
670 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
671 }
673 #ifdef COMPILER2
674 if (FLAG_IS_DEFAULT(AlignVector)) {
675 // Modern processors allow misaligned memory operations for vectors.
676 AlignVector = !UseUnalignedLoadStores;
677 }
678 #endif // COMPILER2
680 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
681 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
683 // set valid Prefetch instruction
684 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
685 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
686 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
687 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
689 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
690 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
691 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
692 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
694 // Allocation prefetch settings
695 intx cache_line_size = prefetch_data_size();
696 if( cache_line_size > AllocatePrefetchStepSize )
697 AllocatePrefetchStepSize = cache_line_size;
699 assert(AllocatePrefetchLines > 0, "invalid value");
700 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
701 AllocatePrefetchLines = 3;
702 assert(AllocateInstancePrefetchLines > 0, "invalid value");
703 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
704 AllocateInstancePrefetchLines = 1;
706 AllocatePrefetchDistance = allocate_prefetch_distance();
707 AllocatePrefetchStyle = allocate_prefetch_style();
709 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
710 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
711 #ifdef _LP64
712 AllocatePrefetchDistance = 384;
713 #else
714 AllocatePrefetchDistance = 320;
715 #endif
716 }
717 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
718 AllocatePrefetchDistance = 192;
719 AllocatePrefetchLines = 4;
720 #ifdef COMPILER2
721 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
722 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
723 }
724 #endif
725 }
726 }
727 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
729 #ifdef _LP64
730 // Prefetch settings
731 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
732 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
733 PrefetchFieldsAhead = prefetch_fields_ahead();
734 #endif
736 #ifndef PRODUCT
737 if (PrintMiscellaneous && Verbose) {
738 tty->print_cr("Logical CPUs per core: %u",
739 logical_processors_per_package());
740 tty->print("UseSSE=%d",UseSSE);
741 if (UseAVX > 0) {
742 tty->print(" UseAVX=%d",UseAVX);
743 }
744 if (UseAES) {
745 tty->print(" UseAES=1");
746 }
747 tty->cr();
748 tty->print("Allocation");
749 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
750 tty->print_cr(": no prefetching");
751 } else {
752 tty->print(" prefetching: ");
753 if (UseSSE == 0 && supports_3dnow_prefetch()) {
754 tty->print("PREFETCHW");
755 } else if (UseSSE >= 1) {
756 if (AllocatePrefetchInstr == 0) {
757 tty->print("PREFETCHNTA");
758 } else if (AllocatePrefetchInstr == 1) {
759 tty->print("PREFETCHT0");
760 } else if (AllocatePrefetchInstr == 2) {
761 tty->print("PREFETCHT2");
762 } else if (AllocatePrefetchInstr == 3) {
763 tty->print("PREFETCHW");
764 }
765 }
766 if (AllocatePrefetchLines > 1) {
767 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
768 } else {
769 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
770 }
771 }
773 if (PrefetchCopyIntervalInBytes > 0) {
774 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
775 }
776 if (PrefetchScanIntervalInBytes > 0) {
777 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
778 }
779 if (PrefetchFieldsAhead > 0) {
780 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
781 }
782 }
783 #endif // !PRODUCT
784 }
786 void VM_Version::initialize() {
787 ResourceMark rm;
788 // Making this stub must be FIRST use of assembler
790 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
791 if (stub_blob == NULL) {
792 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
793 }
794 CodeBuffer c(stub_blob);
795 VM_Version_StubGenerator g(&c);
796 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
797 g.generate_getPsrInfo());
799 get_processor_features();
800 }
