Sat, 07 Nov 2020 10:30:02 +0800
Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f
twisti@1020 | 1 | /* |
drchase@6680 | 2 | * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
twisti@1020 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
twisti@1020 | 4 | * |
twisti@1020 | 5 | * This code is free software; you can redistribute it and/or modify it |
twisti@1020 | 6 | * under the terms of the GNU General Public License version 2 only, as |
twisti@1020 | 7 | * published by the Free Software Foundation. |
twisti@1020 | 8 | * |
twisti@1020 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
twisti@1020 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
twisti@1020 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
twisti@1020 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
twisti@1020 | 13 | * accompanied this code). |
twisti@1020 | 14 | * |
twisti@1020 | 15 | * You should have received a copy of the GNU General Public License version |
twisti@1020 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
twisti@1020 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
twisti@1020 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
twisti@1020 | 22 | * |
twisti@1020 | 23 | */ |
twisti@1020 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
twisti@4318 | 26 | #include "asm/macroAssembler.hpp" |
twisti@4318 | 27 | #include "asm/macroAssembler.inline.hpp" |
stefank@2314 | 28 | #include "memory/resourceArea.hpp" |
stefank@2314 | 29 | #include "runtime/java.hpp" |
stefank@2314 | 30 | #include "runtime/stubCodeGenerator.hpp" |
stefank@2314 | 31 | #include "vm_version_x86.hpp" |
stefank@2314 | 32 | #ifdef TARGET_OS_FAMILY_linux |
stefank@2314 | 33 | # include "os_linux.inline.hpp" |
stefank@2314 | 34 | #endif |
stefank@2314 | 35 | #ifdef TARGET_OS_FAMILY_solaris |
stefank@2314 | 36 | # include "os_solaris.inline.hpp" |
stefank@2314 | 37 | #endif |
stefank@2314 | 38 | #ifdef TARGET_OS_FAMILY_windows |
stefank@2314 | 39 | # include "os_windows.inline.hpp" |
stefank@2314 | 40 | #endif |
never@3156 | 41 | #ifdef TARGET_OS_FAMILY_bsd |
never@3156 | 42 | # include "os_bsd.inline.hpp" |
never@3156 | 43 | #endif |
twisti@1020 | 44 | |
twisti@1020 | 45 | |
twisti@1020 | 46 | int VM_Version::_cpu; |
twisti@1020 | 47 | int VM_Version::_model; |
twisti@1020 | 48 | int VM_Version::_stepping; |
twisti@1020 | 49 | int VM_Version::_cpuFeatures; |
twisti@1020 | 50 | const char* VM_Version::_features_str = ""; |
twisti@1020 | 51 | VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
twisti@1020 | 52 | |
kvn@6388 | 53 | // Address of instruction which causes SEGV |
kvn@6388 | 54 | address VM_Version::_cpuinfo_segv_addr = 0; |
kvn@6388 | 55 | // Address of instruction after the one which causes SEGV |
kvn@6388 | 56 | address VM_Version::_cpuinfo_cont_addr = 0; |
kvn@6388 | 57 | |
twisti@1020 | 58 | static BufferBlob* stub_blob; |
kvn@6388 | 59 | static const int stub_size = 600; |
twisti@1020 | 60 | |
twisti@1020 | 61 | extern "C" { |
kvn@6537 | 62 | typedef void (*get_cpu_info_stub_t)(void*); |
twisti@1020 | 63 | } |
kvn@6537 | 64 | static get_cpu_info_stub_t get_cpu_info_stub = NULL; |
twisti@1020 | 65 | |
twisti@1020 | 66 | |
twisti@1020 | 67 | class VM_Version_StubGenerator: public StubCodeGenerator { |
twisti@1020 | 68 | public: |
twisti@1020 | 69 | |
twisti@1020 | 70 | VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
twisti@1020 | 71 | |
kvn@6537 | 72 | address generate_get_cpu_info() { |
twisti@1020 | 73 | // Flags to test CPU type. |
sla@3587 | 74 | const uint32_t HS_EFL_AC = 0x40000; |
sla@3587 | 75 | const uint32_t HS_EFL_ID = 0x200000; |
twisti@1020 | 76 | // Values for when we don't have a CPUID instruction. |
twisti@1020 | 77 | const int CPU_FAMILY_SHIFT = 8; |
twisti@1020 | 78 | const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
twisti@1020 | 79 | const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
twisti@1020 | 80 | |
kvn@1977 | 81 | Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
kvn@3400 | 82 | Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
twisti@1020 | 83 | |
kvn@6537 | 84 | StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); |
twisti@1020 | 85 | # define __ _masm-> |
twisti@1020 | 86 | |
twisti@1020 | 87 | address start = __ pc(); |
twisti@1020 | 88 | |
twisti@1020 | 89 | // |
kvn@6537 | 90 | // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); |
twisti@1020 | 91 | // |
twisti@1020 | 92 | // LP64: rcx and rdx are first and second argument registers on windows |
twisti@1020 | 93 | |
twisti@1020 | 94 | __ push(rbp); |
twisti@1020 | 95 | #ifdef _LP64 |
twisti@1020 | 96 | __ mov(rbp, c_rarg0); // cpuid_info address |
twisti@1020 | 97 | #else |
twisti@1020 | 98 | __ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
twisti@1020 | 99 | #endif |
twisti@1020 | 100 | __ push(rbx); |
twisti@1020 | 101 | __ push(rsi); |
twisti@1020 | 102 | __ pushf(); // preserve rbx, and flags |
twisti@1020 | 103 | __ pop(rax); |
twisti@1020 | 104 | __ push(rax); |
twisti@1020 | 105 | __ mov(rcx, rax); |
twisti@1020 | 106 | // |
twisti@1020 | 107 | // if we are unable to change the AC flag, we have a 386 |
twisti@1020 | 108 | // |
sla@3587 | 109 | __ xorl(rax, HS_EFL_AC); |
twisti@1020 | 110 | __ push(rax); |
twisti@1020 | 111 | __ popf(); |
twisti@1020 | 112 | __ pushf(); |
twisti@1020 | 113 | __ pop(rax); |
twisti@1020 | 114 | __ cmpptr(rax, rcx); |
twisti@1020 | 115 | __ jccb(Assembler::notEqual, detect_486); |
twisti@1020 | 116 | |
twisti@1020 | 117 | __ movl(rax, CPU_FAMILY_386); |
twisti@1020 | 118 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 119 | __ jmp(done); |
twisti@1020 | 120 | |
twisti@1020 | 121 | // |
twisti@1020 | 122 | // If we are unable to change the ID flag, we have a 486 which does |
twisti@1020 | 123 | // not support the "cpuid" instruction. |
twisti@1020 | 124 | // |
twisti@1020 | 125 | __ bind(detect_486); |
twisti@1020 | 126 | __ mov(rax, rcx); |
sla@3587 | 127 | __ xorl(rax, HS_EFL_ID); |
twisti@1020 | 128 | __ push(rax); |
twisti@1020 | 129 | __ popf(); |
twisti@1020 | 130 | __ pushf(); |
twisti@1020 | 131 | __ pop(rax); |
twisti@1020 | 132 | __ cmpptr(rcx, rax); |
twisti@1020 | 133 | __ jccb(Assembler::notEqual, detect_586); |
twisti@1020 | 134 | |
twisti@1020 | 135 | __ bind(cpu486); |
twisti@1020 | 136 | __ movl(rax, CPU_FAMILY_486); |
twisti@1020 | 137 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 138 | __ jmp(done); |
twisti@1020 | 139 | |
twisti@1020 | 140 | // |
twisti@1020 | 141 | // At this point, we have a chip which supports the "cpuid" instruction |
twisti@1020 | 142 | // |
twisti@1020 | 143 | __ bind(detect_586); |
twisti@1020 | 144 | __ xorl(rax, rax); |
twisti@1020 | 145 | __ cpuid(); |
twisti@1020 | 146 | __ orl(rax, rax); |
twisti@1020 | 147 | __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
twisti@1020 | 148 | // value of at least 1, we give up and |
twisti@1020 | 149 | // assume a 486 |
twisti@1020 | 150 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
twisti@1020 | 151 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 152 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 153 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 154 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 155 | |
kvn@1977 | 156 | __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
kvn@1977 | 157 | __ jccb(Assembler::belowEqual, std_cpuid4); |
kvn@1977 | 158 | |
kvn@1977 | 159 | // |
kvn@1977 | 160 | // cpuid(0xB) Processor Topology |
kvn@1977 | 161 | // |
kvn@1977 | 162 | __ movl(rax, 0xb); |
kvn@1977 | 163 | __ xorl(rcx, rcx); // Threads level |
kvn@1977 | 164 | __ cpuid(); |
kvn@1977 | 165 | |
kvn@1977 | 166 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
kvn@1977 | 167 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 168 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 169 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 170 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 171 | |
kvn@1977 | 172 | __ movl(rax, 0xb); |
kvn@1977 | 173 | __ movl(rcx, 1); // Cores level |
kvn@1977 | 174 | __ cpuid(); |
kvn@1977 | 175 | __ push(rax); |
kvn@1977 | 176 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 177 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 178 | __ andl(rax, 0xffff); |
kvn@1977 | 179 | __ pop(rax); |
kvn@1977 | 180 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 181 | |
kvn@1977 | 182 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
kvn@1977 | 183 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 184 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 185 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 186 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 187 | |
kvn@1977 | 188 | __ movl(rax, 0xb); |
kvn@1977 | 189 | __ movl(rcx, 2); // Packages level |
kvn@1977 | 190 | __ cpuid(); |
kvn@1977 | 191 | __ push(rax); |
kvn@1977 | 192 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 193 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 194 | __ andl(rax, 0xffff); |
kvn@1977 | 195 | __ pop(rax); |
kvn@1977 | 196 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 197 | |
kvn@1977 | 198 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
kvn@1977 | 199 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 200 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 201 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 202 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 203 | |
twisti@1020 | 204 | // |
twisti@1020 | 205 | // cpuid(0x4) Deterministic cache params |
twisti@1020 | 206 | // |
kvn@1977 | 207 | __ bind(std_cpuid4); |
twisti@1020 | 208 | __ movl(rax, 4); |
kvn@1977 | 209 | __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
kvn@1977 | 210 | __ jccb(Assembler::greater, std_cpuid1); |
kvn@1977 | 211 | |
twisti@1020 | 212 | __ xorl(rcx, rcx); // L1 cache |
twisti@1020 | 213 | __ cpuid(); |
twisti@1020 | 214 | __ push(rax); |
twisti@1020 | 215 | __ andl(rax, 0x1f); // Determine if valid cache parameters used |
twisti@1020 | 216 | __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
twisti@1020 | 217 | __ pop(rax); |
twisti@1020 | 218 | __ jccb(Assembler::equal, std_cpuid1); |
twisti@1020 | 219 | |
twisti@1020 | 220 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
twisti@1020 | 221 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 222 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 223 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 224 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 225 | |
twisti@1020 | 226 | // |
twisti@1020 | 227 | // Standard cpuid(0x1) |
twisti@1020 | 228 | // |
twisti@1020 | 229 | __ bind(std_cpuid1); |
twisti@1020 | 230 | __ movl(rax, 1); |
twisti@1020 | 231 | __ cpuid(); |
twisti@1020 | 232 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
twisti@1020 | 233 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 234 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 235 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 236 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 237 | |
kvn@3388 | 238 | // |
kvn@3388 | 239 | // Check if OS has enabled XGETBV instruction to access XCR0 |
kvn@3388 | 240 | // (OSXSAVE feature flag) and CPU supports AVX |
kvn@3388 | 241 | // |
kvn@6388 | 242 | __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
kvn@3388 | 243 | __ cmpl(rcx, 0x18000000); |
kvn@6388 | 244 | __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
kvn@3388 | 245 | |
kvn@3388 | 246 | // |
kvn@3388 | 247 | // XCR0, XFEATURE_ENABLED_MASK register |
kvn@3388 | 248 | // |
kvn@3388 | 249 | __ xorl(rcx, rcx); // zero for XCR0 register |
kvn@3388 | 250 | __ xgetbv(); |
kvn@3388 | 251 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); |
kvn@3388 | 252 | __ movl(Address(rsi, 0), rax); |
kvn@3388 | 253 | __ movl(Address(rsi, 4), rdx); |
kvn@3388 | 254 | |
kvn@6388 | 255 | __ andl(rax, 0x6); // xcr0 bits sse | ymm |
kvn@6388 | 256 | __ cmpl(rax, 0x6); |
kvn@6388 | 257 | __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
kvn@6388 | 258 | |
kvn@6388 | 259 | // |
kvn@6388 | 260 | // Some OSs have a bug when upper 128bits of YMM |
kvn@6388 | 261 | // registers are not restored after a signal processing. |
kvn@6388 | 262 | // Generate SEGV here (reference through NULL) |
kvn@6388 | 263 | // and check upper YMM bits after it. |
kvn@6388 | 264 | // |
kvn@6388 | 265 | VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
kvn@6656 | 266 | intx saved_useavx = UseAVX; |
kvn@6656 | 267 | intx saved_usesse = UseSSE; |
kvn@6656 | 268 | UseAVX = 1; |
kvn@6656 | 269 | UseSSE = 2; |
kvn@6388 | 270 | |
kvn@6388 | 271 | // load value into all 32 bytes of ymm7 register |
kvn@6388 | 272 | __ movl(rcx, VM_Version::ymm_test_value()); |
kvn@6388 | 273 | |
kvn@6388 | 274 | __ movdl(xmm0, rcx); |
kvn@6388 | 275 | __ pshufd(xmm0, xmm0, 0x00); |
kvn@6388 | 276 | __ vinsertf128h(xmm0, xmm0, xmm0); |
kvn@6388 | 277 | __ vmovdqu(xmm7, xmm0); |
kvn@6388 | 278 | #ifdef _LP64 |
kvn@6388 | 279 | __ vmovdqu(xmm8, xmm0); |
kvn@6388 | 280 | __ vmovdqu(xmm15, xmm0); |
kvn@6388 | 281 | #endif |
kvn@6388 | 282 | |
kvn@6388 | 283 | __ xorl(rsi, rsi); |
kvn@6388 | 284 | VM_Version::set_cpuinfo_segv_addr( __ pc() ); |
kvn@6388 | 285 | // Generate SEGV |
kvn@6388 | 286 | __ movl(rax, Address(rsi, 0)); |
kvn@6388 | 287 | |
kvn@6388 | 288 | VM_Version::set_cpuinfo_cont_addr( __ pc() ); |
kvn@6388 | 289 | // Returns here after signal. Save xmm0 to check it later. |
kvn@6388 | 290 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); |
kvn@6388 | 291 | __ vmovdqu(Address(rsi, 0), xmm0); |
kvn@6388 | 292 | __ vmovdqu(Address(rsi, 32), xmm7); |
kvn@6388 | 293 | #ifdef _LP64 |
kvn@6388 | 294 | __ vmovdqu(Address(rsi, 64), xmm8); |
kvn@6388 | 295 | __ vmovdqu(Address(rsi, 96), xmm15); |
kvn@6388 | 296 | #endif |
kvn@6388 | 297 | |
kvn@6388 | 298 | VM_Version::clean_cpuFeatures(); |
kvn@6656 | 299 | UseAVX = saved_useavx; |
kvn@6656 | 300 | UseSSE = saved_usesse; |
kvn@6388 | 301 | |
kvn@3388 | 302 | // |
kvn@3388 | 303 | // cpuid(0x7) Structured Extended Features |
kvn@3388 | 304 | // |
kvn@3388 | 305 | __ bind(sef_cpuid); |
kvn@3388 | 306 | __ movl(rax, 7); |
kvn@3388 | 307 | __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? |
kvn@3388 | 308 | __ jccb(Assembler::greater, ext_cpuid); |
kvn@3388 | 309 | |
kvn@3388 | 310 | __ xorl(rcx, rcx); |
kvn@3388 | 311 | __ cpuid(); |
kvn@3388 | 312 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
kvn@3388 | 313 | __ movl(Address(rsi, 0), rax); |
kvn@3388 | 314 | __ movl(Address(rsi, 4), rbx); |
kvn@3388 | 315 | |
kvn@3388 | 316 | // |
kvn@3388 | 317 | // Extended cpuid(0x80000000) |
kvn@3388 | 318 | // |
kvn@3388 | 319 | __ bind(ext_cpuid); |
twisti@1020 | 320 | __ movl(rax, 0x80000000); |
twisti@1020 | 321 | __ cpuid(); |
twisti@1020 | 322 | __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
twisti@1020 | 323 | __ jcc(Assembler::belowEqual, done); |
twisti@1020 | 324 | __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
twisti@1020 | 325 | __ jccb(Assembler::belowEqual, ext_cpuid1); |
phh@3378 | 326 | __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
phh@3378 | 327 | __ jccb(Assembler::belowEqual, ext_cpuid5); |
twisti@1020 | 328 | __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
phh@3378 | 329 | __ jccb(Assembler::belowEqual, ext_cpuid7); |
twisti@1020 | 330 | // |
twisti@1020 | 331 | // Extended cpuid(0x80000008) |
twisti@1020 | 332 | // |
twisti@1020 | 333 | __ movl(rax, 0x80000008); |
twisti@1020 | 334 | __ cpuid(); |
twisti@1020 | 335 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
twisti@1020 | 336 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 337 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 338 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 339 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 340 | |
twisti@1020 | 341 | // |
phh@3378 | 342 | // Extended cpuid(0x80000007) |
phh@3378 | 343 | // |
phh@3378 | 344 | __ bind(ext_cpuid7); |
phh@3378 | 345 | __ movl(rax, 0x80000007); |
phh@3378 | 346 | __ cpuid(); |
phh@3378 | 347 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
phh@3378 | 348 | __ movl(Address(rsi, 0), rax); |
phh@3378 | 349 | __ movl(Address(rsi, 4), rbx); |
phh@3378 | 350 | __ movl(Address(rsi, 8), rcx); |
phh@3378 | 351 | __ movl(Address(rsi,12), rdx); |
phh@3378 | 352 | |
phh@3378 | 353 | // |
twisti@1020 | 354 | // Extended cpuid(0x80000005) |
twisti@1020 | 355 | // |
twisti@1020 | 356 | __ bind(ext_cpuid5); |
twisti@1020 | 357 | __ movl(rax, 0x80000005); |
twisti@1020 | 358 | __ cpuid(); |
twisti@1020 | 359 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
twisti@1020 | 360 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 361 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 362 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 363 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 364 | |
twisti@1020 | 365 | // |
twisti@1020 | 366 | // Extended cpuid(0x80000001) |
twisti@1020 | 367 | // |
twisti@1020 | 368 | __ bind(ext_cpuid1); |
twisti@1020 | 369 | __ movl(rax, 0x80000001); |
twisti@1020 | 370 | __ cpuid(); |
twisti@1020 | 371 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
twisti@1020 | 372 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 373 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 374 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 375 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 376 | |
twisti@1020 | 377 | // |
twisti@1020 | 378 | // return |
twisti@1020 | 379 | // |
twisti@1020 | 380 | __ bind(done); |
twisti@1020 | 381 | __ popf(); |
twisti@1020 | 382 | __ pop(rsi); |
twisti@1020 | 383 | __ pop(rbx); |
twisti@1020 | 384 | __ pop(rbp); |
twisti@1020 | 385 | __ ret(0); |
twisti@1020 | 386 | |
twisti@1020 | 387 | # undef __ |
twisti@1020 | 388 | |
twisti@1020 | 389 | return start; |
twisti@1020 | 390 | }; |
twisti@1020 | 391 | }; |
twisti@1020 | 392 | |
twisti@1020 | 393 | |
kvn@6537 | 394 | void VM_Version::get_cpu_info_wrapper() { |
kvn@6537 | 395 | get_cpu_info_stub(&_cpuid_info); |
kvn@6537 | 396 | } |
kvn@6537 | 397 | |
kvn@6537 | 398 | #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED |
kvn@6537 | 399 | #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() |
kvn@6537 | 400 | #endif |
kvn@6537 | 401 | |
twisti@1020 | 402 | void VM_Version::get_processor_features() { |
twisti@1020 | 403 | |
twisti@1020 | 404 | _cpu = 4; // 486 by default |
twisti@1020 | 405 | _model = 0; |
twisti@1020 | 406 | _stepping = 0; |
twisti@1020 | 407 | _cpuFeatures = 0; |
twisti@1020 | 408 | _logical_processors_per_package = 1; |
kevinw@8966 | 409 | // i486 internal cache is both I&D and has a 16-byte line size |
kevinw@8966 | 410 | _L1_data_cache_line_size = 16; |
twisti@1020 | 411 | |
twisti@1020 | 412 | if (!Use486InstrsOnly) { |
twisti@1020 | 413 | // Get raw processor info |
kvn@6537 | 414 | |
kvn@6537 | 415 | // Some platforms (like Win*) need a wrapper around here |
kvn@6537 | 416 | // in order to properly handle SEGV for YMM registers test. |
kvn@6537 | 417 | CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper); |
kvn@6537 | 418 | |
twisti@1020 | 419 | assert_is_initialized(); |
twisti@1020 | 420 | _cpu = extended_cpu_family(); |
twisti@1020 | 421 | _model = extended_cpu_model(); |
twisti@1020 | 422 | _stepping = cpu_stepping(); |
twisti@1020 | 423 | |
twisti@1020 | 424 | if (cpu_family() > 4) { // it supports CPUID |
twisti@1020 | 425 | _cpuFeatures = feature_flags(); |
twisti@1020 | 426 | // Logical processors are only available on P4s and above, |
twisti@1020 | 427 | // and only if hyperthreading is available. |
twisti@1020 | 428 | _logical_processors_per_package = logical_processor_count(); |
kevinw@8966 | 429 | _L1_data_cache_line_size = L1_line_size(); |
twisti@1020 | 430 | } |
twisti@1020 | 431 | } |
twisti@1020 | 432 | |
twisti@1020 | 433 | _supports_cx8 = supports_cmpxchg8(); |
roland@4106 | 434 | // xchg and xadd instructions |
roland@4106 | 435 | _supports_atomic_getset4 = true; |
roland@4106 | 436 | _supports_atomic_getadd4 = true; |
roland@4106 | 437 | LP64_ONLY(_supports_atomic_getset8 = true); |
roland@4106 | 438 | LP64_ONLY(_supports_atomic_getadd8 = true); |
twisti@1020 | 439 | |
twisti@1020 | 440 | #ifdef _LP64 |
twisti@1020 | 441 | // OS should support SSE for x64 and hardware should support at least SSE2. |
twisti@1020 | 442 | if (!VM_Version::supports_sse2()) { |
twisti@1020 | 443 | vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
twisti@1020 | 444 | } |
roland@1495 | 445 | // in 64 bit the use of SSE2 is the minimum |
roland@1495 | 446 | if (UseSSE < 2) UseSSE = 2; |
twisti@1020 | 447 | #endif |
twisti@1020 | 448 | |
kvn@2984 | 449 | #ifdef AMD64 |
kvn@2984 | 450 | // flush_icache_stub have to be generated first. |
kvn@2984 | 451 | // That is why Icache line size is hard coded in ICache class, |
kvn@2984 | 452 | // see icache_x86.hpp. It is also the reason why we can't use |
kvn@2984 | 453 | // clflush instruction in 32-bit VM since it could be running |
kvn@2984 | 454 | // on CPU which does not support it. |
kvn@2984 | 455 | // |
kvn@2984 | 456 | // The only thing we can do is to verify that flushed |
kvn@2984 | 457 | // ICache::line_size has correct value. |
kvn@2984 | 458 | guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
kvn@2984 | 459 | // clflush_size is size in quadwords (8 bytes). |
kvn@2984 | 460 | guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
kvn@2984 | 461 | #endif |
kvn@2984 | 462 | |
twisti@1020 | 463 | // If the OS doesn't support SSE, we can't use this feature even if the HW does |
twisti@1020 | 464 | if (!os::supports_sse()) |
twisti@1020 | 465 | _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
twisti@1020 | 466 | |
twisti@1020 | 467 | if (UseSSE < 4) { |
twisti@1020 | 468 | _cpuFeatures &= ~CPU_SSE4_1; |
twisti@1020 | 469 | _cpuFeatures &= ~CPU_SSE4_2; |
twisti@1020 | 470 | } |
twisti@1020 | 471 | |
twisti@1020 | 472 | if (UseSSE < 3) { |
twisti@1020 | 473 | _cpuFeatures &= ~CPU_SSE3; |
twisti@1020 | 474 | _cpuFeatures &= ~CPU_SSSE3; |
twisti@1020 | 475 | _cpuFeatures &= ~CPU_SSE4A; |
twisti@1020 | 476 | } |
twisti@1020 | 477 | |
twisti@1020 | 478 | if (UseSSE < 2) |
twisti@1020 | 479 | _cpuFeatures &= ~CPU_SSE2; |
twisti@1020 | 480 | |
twisti@1020 | 481 | if (UseSSE < 1) |
twisti@1020 | 482 | _cpuFeatures &= ~CPU_SSE; |
twisti@1020 | 483 | |
kvn@3388 | 484 | if (UseAVX < 2) |
kvn@3388 | 485 | _cpuFeatures &= ~CPU_AVX2; |
kvn@3388 | 486 | |
kvn@3388 | 487 | if (UseAVX < 1) |
kvn@3388 | 488 | _cpuFeatures &= ~CPU_AVX; |
kvn@3388 | 489 | |
kvn@4205 | 490 | if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
kvn@4205 | 491 | _cpuFeatures &= ~CPU_AES; |
kvn@4205 | 492 | |
twisti@1020 | 493 | if (logical_processors_per_package() == 1) { |
twisti@1020 | 494 | // HT processor could be installed on a system which doesn't support HT. |
twisti@1020 | 495 | _cpuFeatures &= ~CPU_HT; |
twisti@1020 | 496 | } |
twisti@1020 | 497 | |
twisti@1020 | 498 | char buf[256]; |
kvn@7152 | 499 | jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
twisti@1020 | 500 | cores_per_cpu(), threads_per_core(), |
twisti@1020 | 501 | cpu_family(), _model, _stepping, |
twisti@1020 | 502 | (supports_cmov() ? ", cmov" : ""), |
twisti@1020 | 503 | (supports_cmpxchg8() ? ", cx8" : ""), |
twisti@1020 | 504 | (supports_fxsr() ? ", fxsr" : ""), |
twisti@1020 | 505 | (supports_mmx() ? ", mmx" : ""), |
twisti@1020 | 506 | (supports_sse() ? ", sse" : ""), |
twisti@1020 | 507 | (supports_sse2() ? ", sse2" : ""), |
twisti@1020 | 508 | (supports_sse3() ? ", sse3" : ""), |
twisti@1020 | 509 | (supports_ssse3()? ", ssse3": ""), |
twisti@1020 | 510 | (supports_sse4_1() ? ", sse4.1" : ""), |
twisti@1020 | 511 | (supports_sse4_2() ? ", sse4.2" : ""), |
twisti@1078 | 512 | (supports_popcnt() ? ", popcnt" : ""), |
kvn@3388 | 513 | (supports_avx() ? ", avx" : ""), |
kvn@3388 | 514 | (supports_avx2() ? ", avx2" : ""), |
kvn@4205 | 515 | (supports_aes() ? ", aes" : ""), |
kvn@6429 | 516 | (supports_clmul() ? ", clmul" : ""), |
kvn@4410 | 517 | (supports_erms() ? ", erms" : ""), |
kvn@6429 | 518 | (supports_rtm() ? ", rtm" : ""), |
twisti@1020 | 519 | (supports_mmx_ext() ? ", mmxext" : ""), |
kvn@2761 | 520 | (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
twisti@1210 | 521 | (supports_lzcnt() ? ", lzcnt": ""), |
twisti@1020 | 522 | (supports_sse4a() ? ", sse4a": ""), |
phh@3378 | 523 | (supports_ht() ? ", ht": ""), |
phh@3378 | 524 | (supports_tsc() ? ", tsc": ""), |
phh@3378 | 525 | (supports_tscinv_bit() ? ", tscinvbit": ""), |
iveresov@6378 | 526 | (supports_tscinv() ? ", tscinv": ""), |
iveresov@6378 | 527 | (supports_bmi1() ? ", bmi1" : ""), |
kvn@7152 | 528 | (supports_bmi2() ? ", bmi2" : ""), |
kvn@7152 | 529 | (supports_adx() ? ", adx" : "")); |
twisti@1020 | 530 | _features_str = strdup(buf); |
twisti@1020 | 531 | |
twisti@1020 | 532 | // UseSSE is set to the smaller of what hardware supports and what |
twisti@1020 | 533 | // the command line requires. I.e., you cannot set UseSSE to 2 on |
twisti@1020 | 534 | // older Pentiums which do not support it. |
kvn@3388 | 535 | if (UseSSE > 4) UseSSE=4; |
kvn@3388 | 536 | if (UseSSE < 0) UseSSE=0; |
kvn@3388 | 537 | if (!supports_sse4_1()) // Drop to 3 if no SSE4 support |
twisti@1020 | 538 | UseSSE = MIN2((intx)3,UseSSE); |
kvn@3388 | 539 | if (!supports_sse3()) // Drop to 2 if no SSE3 support |
twisti@1020 | 540 | UseSSE = MIN2((intx)2,UseSSE); |
kvn@3388 | 541 | if (!supports_sse2()) // Drop to 1 if no SSE2 support |
twisti@1020 | 542 | UseSSE = MIN2((intx)1,UseSSE); |
kvn@3388 | 543 | if (!supports_sse ()) // Drop to 0 if no SSE support |
twisti@1020 | 544 | UseSSE = 0; |
twisti@1020 | 545 | |
kvn@3388 | 546 | if (UseAVX > 2) UseAVX=2; |
kvn@3388 | 547 | if (UseAVX < 0) UseAVX=0; |
kvn@3388 | 548 | if (!supports_avx2()) // Drop to 1 if no AVX2 support |
kvn@3388 | 549 | UseAVX = MIN2((intx)1,UseAVX); |
kvn@3388 | 550 | if (!supports_avx ()) // Drop to 0 if no AVX support |
kvn@3388 | 551 | UseAVX = 0; |
kvn@3388 | 552 | |
kvn@4205 | 553 | // Use AES instructions if available. |
kvn@4205 | 554 | if (supports_aes()) { |
kvn@4205 | 555 | if (FLAG_IS_DEFAULT(UseAES)) { |
kshefov@9795 | 556 | FLAG_SET_DEFAULT(UseAES, true); |
kvn@4205 | 557 | } |
kshefov@9795 | 558 | if (!UseAES) { |
kshefov@9795 | 559 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 560 | warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
kshefov@9795 | 561 | } |
kshefov@9795 | 562 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kshefov@9795 | 563 | } else { |
kshefov@9795 | 564 | if (UseSSE > 2) { |
kshefov@9795 | 565 | if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 566 | FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
kshefov@9795 | 567 | } |
kshefov@9795 | 568 | } else { |
kshefov@9795 | 569 | // The AES intrinsic stubs require AES instruction support (of course) |
kshefov@9795 | 570 | // but also require sse3 mode or higher for instructions it use. |
kshefov@9795 | 571 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 572 | warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled."); |
kshefov@9795 | 573 | } |
kshefov@9795 | 574 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kshefov@9795 | 575 | } |
kshefov@9795 | 576 | } |
kshefov@9795 | 577 | } else if (UseAES || UseAESIntrinsics) { |
kshefov@9795 | 578 | if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
kvn@6429 | 579 | warning("AES instructions are not available on this CPU"); |
kshefov@9795 | 580 | FLAG_SET_DEFAULT(UseAES, false); |
kshefov@9795 | 581 | } |
kshefov@9795 | 582 | if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
kshefov@9795 | 583 | warning("AES intrinsics are not available on this CPU"); |
kshefov@9795 | 584 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
kshefov@9795 | 585 | } |
kvn@4205 | 586 | } |
kvn@4205 | 587 | |
drchase@5353 | 588 | // Use CLMUL instructions if available. |
drchase@5353 | 589 | if (supports_clmul()) { |
drchase@5353 | 590 | if (FLAG_IS_DEFAULT(UseCLMUL)) { |
drchase@5353 | 591 | UseCLMUL = true; |
drchase@5353 | 592 | } |
drchase@5353 | 593 | } else if (UseCLMUL) { |
drchase@5353 | 594 | if (!FLAG_IS_DEFAULT(UseCLMUL)) |
drchase@5353 | 595 | warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
drchase@5353 | 596 | FLAG_SET_DEFAULT(UseCLMUL, false); |
drchase@5353 | 597 | } |
drchase@5353 | 598 | |
kvn@7025 | 599 | if (UseCLMUL && (UseSSE > 2)) { |
drchase@5353 | 600 | if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
drchase@5353 | 601 | UseCRC32Intrinsics = true; |
drchase@5353 | 602 | } |
drchase@5353 | 603 | } else if (UseCRC32Intrinsics) { |
drchase@5353 | 604 | if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
kvn@7152 | 605 | warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); |
drchase@5353 | 606 | FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
drchase@5353 | 607 | } |
drchase@5353 | 608 | |
ascarpino@9788 | 609 | // GHASH/GCM intrinsics |
ascarpino@9788 | 610 | if (UseCLMUL && (UseSSE > 2)) { |
ascarpino@9788 | 611 | if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
ascarpino@9788 | 612 | UseGHASHIntrinsics = true; |
ascarpino@9788 | 613 | } |
ascarpino@9788 | 614 | } else if (UseGHASHIntrinsics) { |
ascarpino@9788 | 615 | if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
ascarpino@9788 | 616 | warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU"); |
ascarpino@9788 | 617 | FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
ascarpino@9788 | 618 | } |
ascarpino@9788 | 619 | |
kvn@7027 | 620 | if (UseSHA) { |
kvn@7027 | 621 | warning("SHA instructions are not available on this CPU"); |
kvn@7027 | 622 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 623 | } |
kvn@7027 | 624 | if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { |
kvn@7027 | 625 | warning("SHA intrinsics are not available on this CPU"); |
kvn@7027 | 626 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
kvn@7027 | 627 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
kvn@7027 | 628 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
kvn@7027 | 629 | } |
kvn@7027 | 630 | |
kvn@6429 | 631 | // Adjust RTM (Restricted Transactional Memory) flags |
kvn@6429 | 632 | if (!supports_rtm() && UseRTMLocking) { |
kvn@6429 | 633 | // Can't continue because UseRTMLocking affects UseBiasedLocking flag |
kvn@6429 | 634 | // setting during arguments processing. See use_biased_locking(). |
kvn@6429 | 635 | // VM_Version_init() is executed after UseBiasedLocking is used |
kvn@6429 | 636 | // in Thread::allocate(). |
kvn@6429 | 637 | vm_exit_during_initialization("RTM instructions are not available on this CPU"); |
kvn@6429 | 638 | } |
kvn@6429 | 639 | |
kvn@6429 | 640 | #if INCLUDE_RTM_OPT |
kvn@6429 | 641 | if (UseRTMLocking) { |
kvn@7088 | 642 | if (is_intel_family_core()) { |
kvn@7088 | 643 | if ((_model == CPU_MODEL_HASWELL_E3) || |
kvn@7088 | 644 | (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || |
kvn@7088 | 645 | (_model == CPU_MODEL_BROADWELL && _stepping < 4)) { |
kvn@7088 | 646 | if (!UnlockExperimentalVMOptions) { |
kvn@7088 | 647 | vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); |
kvn@7088 | 648 | } else { |
kvn@7088 | 649 | warning("UseRTMLocking is only available as experimental option on this platform."); |
kvn@7088 | 650 | } |
kvn@7088 | 651 | } |
kvn@7088 | 652 | } |
kvn@6429 | 653 | if (!FLAG_IS_CMDLINE(UseRTMLocking)) { |
kvn@6429 | 654 | // RTM locking should be used only for applications with |
kvn@6429 | 655 | // high lock contention. For now we do not use it by default. |
kvn@6429 | 656 | vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); |
kvn@6429 | 657 | } |
kvn@6429 | 658 | if (!is_power_of_2(RTMTotalCountIncrRate)) { |
kvn@6429 | 659 | warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); |
kvn@6429 | 660 | FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); |
kvn@6429 | 661 | } |
kvn@6429 | 662 | if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { |
kvn@6429 | 663 | warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); |
kvn@6429 | 664 | FLAG_SET_DEFAULT(RTMAbortRatio, 50); |
kvn@6429 | 665 | } |
kvn@6429 | 666 | } else { // !UseRTMLocking |
kvn@6429 | 667 | if (UseRTMForStackLocks) { |
kvn@6429 | 668 | if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { |
kvn@6429 | 669 | warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); |
kvn@6429 | 670 | } |
kvn@6429 | 671 | FLAG_SET_DEFAULT(UseRTMForStackLocks, false); |
kvn@6429 | 672 | } |
kvn@6429 | 673 | if (UseRTMDeopt) { |
kvn@6429 | 674 | FLAG_SET_DEFAULT(UseRTMDeopt, false); |
kvn@6429 | 675 | } |
kvn@6429 | 676 | if (PrintPreciseRTMLockingStatistics) { |
kvn@6429 | 677 | FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); |
kvn@6429 | 678 | } |
kvn@6429 | 679 | } |
kvn@6429 | 680 | #else |
kvn@6429 | 681 | if (UseRTMLocking) { |
kvn@6429 | 682 | // Only C2 does RTM locking optimization. |
kvn@6429 | 683 | // Can't continue because UseRTMLocking affects UseBiasedLocking flag |
kvn@6429 | 684 | // setting during arguments processing. See use_biased_locking(). |
kvn@6429 | 685 | vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); |
kvn@6429 | 686 | } |
kvn@6429 | 687 | #endif |
kvn@6429 | 688 | |
kvn@3882 | 689 | #ifdef COMPILER2 |
kvn@3882 | 690 | if (UseFPUForSpilling) { |
kvn@3882 | 691 | if (UseSSE < 2) { |
kvn@3882 | 692 | // Only supported with SSE2+ |
kvn@3882 | 693 | FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
kvn@3882 | 694 | } |
kvn@3882 | 695 | } |
kvn@3882 | 696 | if (MaxVectorSize > 0) { |
kvn@3882 | 697 | if (!is_power_of_2(MaxVectorSize)) { |
kvn@3882 | 698 | warning("MaxVectorSize must be a power of 2"); |
kvn@3882 | 699 | FLAG_SET_DEFAULT(MaxVectorSize, 32); |
kvn@3882 | 700 | } |
kvn@3882 | 701 | if (MaxVectorSize > 32) { |
kvn@3882 | 702 | FLAG_SET_DEFAULT(MaxVectorSize, 32); |
kvn@3882 | 703 | } |
kvn@6388 | 704 | if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { |
kvn@6388 | 705 | // 32 bytes vectors (in YMM) are only supported with AVX+ |
kvn@3882 | 706 | FLAG_SET_DEFAULT(MaxVectorSize, 16); |
kvn@3882 | 707 | } |
kvn@3882 | 708 | if (UseSSE < 2) { |
kvn@6388 | 709 | // Vectors (in XMM) are only supported with SSE2+ |
kvn@3882 | 710 | FLAG_SET_DEFAULT(MaxVectorSize, 0); |
kvn@3882 | 711 | } |
kvn@6388 | 712 | #ifdef ASSERT |
kvn@6388 | 713 | if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { |
kvn@6388 | 714 | tty->print_cr("State of YMM registers after signal handle:"); |
kvn@6388 | 715 | int nreg = 2 LP64_ONLY(+2); |
kvn@6388 | 716 | const char* ymm_name[4] = {"0", "7", "8", "15"}; |
kvn@6388 | 717 | for (int i = 0; i < nreg; i++) { |
kvn@6388 | 718 | tty->print("YMM%s:", ymm_name[i]); |
kvn@6388 | 719 | for (int j = 7; j >=0; j--) { |
kvn@6388 | 720 | tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); |
kvn@6388 | 721 | } |
kvn@6388 | 722 | tty->cr(); |
kvn@6388 | 723 | } |
kvn@6388 | 724 | } |
kvn@6388 | 725 | #endif |
kvn@3882 | 726 | } |
kvn@7152 | 727 | |
kvn@7152 | 728 | #ifdef _LP64 |
kvn@7152 | 729 | if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { |
kvn@7152 | 730 | UseMultiplyToLenIntrinsic = true; |
kvn@7152 | 731 | } |
igerasim@8307 | 732 | if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { |
vkempik@8637 | 733 | UseSquareToLenIntrinsic = true; |
igerasim@8307 | 734 | } |
igerasim@8307 | 735 | if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { |
vkempik@8637 | 736 | UseMulAddIntrinsic = true; |
igerasim@8307 | 737 | } |
vkempik@8318 | 738 | if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { |
vkempik@8637 | 739 | UseMontgomeryMultiplyIntrinsic = true; |
vkempik@8318 | 740 | } |
vkempik@8318 | 741 | if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { |
vkempik@8637 | 742 | UseMontgomerySquareIntrinsic = true; |
vkempik@8318 | 743 | } |
kvn@7152 | 744 | #else |
kvn@7152 | 745 | if (UseMultiplyToLenIntrinsic) { |
kvn@7152 | 746 | if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { |
kvn@7152 | 747 | warning("multiplyToLen intrinsic is not available in 32-bit VM"); |
kvn@7152 | 748 | } |
kvn@7152 | 749 | FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); |
kvn@7152 | 750 | } |
igerasim@8307 | 751 | if (UseSquareToLenIntrinsic) { |
igerasim@8307 | 752 | if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { |
igerasim@8307 | 753 | warning("squareToLen intrinsic is not available in 32-bit VM"); |
igerasim@8307 | 754 | } |
igerasim@8307 | 755 | FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false); |
igerasim@8307 | 756 | } |
igerasim@8307 | 757 | if (UseMulAddIntrinsic) { |
igerasim@8307 | 758 | if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { |
igerasim@8307 | 759 | warning("mulAdd intrinsic is not available in 32-bit VM"); |
igerasim@8307 | 760 | } |
igerasim@8307 | 761 | FLAG_SET_DEFAULT(UseMulAddIntrinsic, false); |
igerasim@8307 | 762 | } |
vkempik@8318 | 763 | if (UseMontgomeryMultiplyIntrinsic) { |
vkempik@8318 | 764 | if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { |
vkempik@8318 | 765 | warning("montgomeryMultiply intrinsic is not available in 32-bit VM"); |
vkempik@8318 | 766 | } |
vkempik@8318 | 767 | FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false); |
vkempik@8318 | 768 | } |
vkempik@8318 | 769 | if (UseMontgomerySquareIntrinsic) { |
vkempik@8318 | 770 | if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { |
vkempik@8318 | 771 | warning("montgomerySquare intrinsic is not available in 32-bit VM"); |
vkempik@8318 | 772 | } |
vkempik@8318 | 773 | FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false); |
vkempik@8318 | 774 | } |
kvn@3882 | 775 | #endif |
kvn@7152 | 776 | #endif // COMPILER2 |
kvn@3882 | 777 | |
twisti@1020 | 778 | // On new cpus instructions which update whole XMM register should be used |
twisti@1020 | 779 | // to prevent partial register stall due to dependencies on high half. |
twisti@1020 | 780 | // |
twisti@1020 | 781 | // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
twisti@1020 | 782 | // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
twisti@1020 | 783 | // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
twisti@1020 | 784 | // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
twisti@1020 | 785 | |
twisti@1020 | 786 | if( is_amd() ) { // AMD cpus specific settings |
twisti@1020 | 787 | if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 788 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 789 | UseAddressNop = true; |
twisti@1020 | 790 | } |
twisti@1020 | 791 | if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
twisti@1020 | 792 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 793 | UseNewLongLShift = true; |
twisti@1020 | 794 | } |
twisti@1020 | 795 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 796 | if( supports_sse4a() ) { |
twisti@1020 | 797 | UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
twisti@1020 | 798 | } else { |
twisti@1020 | 799 | UseXmmLoadAndClearUpper = false; |
twisti@1020 | 800 | } |
twisti@1020 | 801 | } |
twisti@1020 | 802 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 803 | if( supports_sse4a() ) { |
twisti@1020 | 804 | UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
twisti@1020 | 805 | } else { |
twisti@1020 | 806 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 807 | } |
twisti@1020 | 808 | } |
twisti@1020 | 809 | if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
twisti@1020 | 810 | if( supports_sse4a() ) { |
twisti@1020 | 811 | UseXmmI2F = true; |
twisti@1020 | 812 | } else { |
twisti@1020 | 813 | UseXmmI2F = false; |
twisti@1020 | 814 | } |
twisti@1020 | 815 | } |
twisti@1020 | 816 | if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
twisti@1020 | 817 | if( supports_sse4a() ) { |
twisti@1020 | 818 | UseXmmI2D = true; |
twisti@1020 | 819 | } else { |
twisti@1020 | 820 | UseXmmI2D = false; |
twisti@1020 | 821 | } |
twisti@1020 | 822 | } |
kvn@2688 | 823 | if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
kvn@2688 | 824 | if( supports_sse4_2() && UseSSE >= 4 ) { |
kvn@2688 | 825 | UseSSE42Intrinsics = true; |
kvn@2688 | 826 | } |
kvn@2688 | 827 | } |
twisti@1210 | 828 | |
kvn@2808 | 829 | // some defaults for AMD family 15h |
kvn@2808 | 830 | if ( cpu_family() == 0x15 ) { |
kvn@2808 | 831 | // On family 15h processors default is no sw prefetch |
kvn@2640 | 832 | if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
kvn@2640 | 833 | AllocatePrefetchStyle = 0; |
kvn@2640 | 834 | } |
kvn@2808 | 835 | // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
kvn@2808 | 836 | if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
kvn@2808 | 837 | AllocatePrefetchInstr = 3; |
kvn@2808 | 838 | } |
kvn@2808 | 839 | // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
kvn@4105 | 840 | if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
kvn@2808 | 841 | UseXMMForArrayCopy = true; |
kvn@2808 | 842 | } |
kvn@4105 | 843 | if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
kvn@2808 | 844 | UseUnalignedLoadStores = true; |
kvn@2808 | 845 | } |
kvn@2640 | 846 | } |
kvn@2808 | 847 | |
kvn@3882 | 848 | #ifdef COMPILER2 |
kvn@3882 | 849 | if (MaxVectorSize > 16) { |
kvn@3882 | 850 | // Limit vectors size to 16 bytes on current AMD cpus. |
kvn@3882 | 851 | FLAG_SET_DEFAULT(MaxVectorSize, 16); |
kvn@3882 | 852 | } |
kvn@3882 | 853 | #endif // COMPILER2 |
twisti@1020 | 854 | } |
twisti@1020 | 855 | |
twisti@1020 | 856 | if( is_intel() ) { // Intel cpus specific settings |
twisti@1020 | 857 | if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
twisti@1020 | 858 | UseStoreImmI16 = false; // don't use it on Intel cpus |
twisti@1020 | 859 | } |
twisti@1020 | 860 | if( cpu_family() == 6 || cpu_family() == 15 ) { |
twisti@1020 | 861 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 862 | // Use it on all Intel cpus starting from PentiumPro |
twisti@1020 | 863 | UseAddressNop = true; |
twisti@1020 | 864 | } |
twisti@1020 | 865 | } |
twisti@1020 | 866 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 867 | UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
twisti@1020 | 868 | } |
twisti@1020 | 869 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 870 | if( supports_sse3() ) { |
twisti@1020 | 871 | UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
twisti@1020 | 872 | } else { |
twisti@1020 | 873 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 874 | } |
twisti@1020 | 875 | } |
twisti@1020 | 876 | if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
twisti@1020 | 877 | #ifdef COMPILER2 |
twisti@1020 | 878 | if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
twisti@1020 | 879 | // For new Intel cpus do the next optimization: |
twisti@1020 | 880 | // don't align the beginning of a loop if there are enough instructions |
twisti@1020 | 881 | // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
twisti@1020 | 882 | // in current fetch line (OptoLoopAlignment) or the padding |
twisti@1020 | 883 | // is big (> MaxLoopPad). |
twisti@1020 | 884 | // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
twisti@1020 | 885 | // generated NOP instructions. 11 is the largest size of one |
twisti@1020 | 886 | // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
twisti@1020 | 887 | MaxLoopPad = 11; |
twisti@1020 | 888 | } |
twisti@1020 | 889 | #endif // COMPILER2 |
kvn@4105 | 890 | if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
twisti@1020 | 891 | UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
twisti@1020 | 892 | } |
kvn@4105 | 893 | if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
kvn@4105 | 894 | if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
twisti@1020 | 895 | UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
twisti@1020 | 896 | } |
twisti@1020 | 897 | } |
kvn@4105 | 898 | if (supports_sse4_2() && UseSSE >= 4) { |
kvn@4105 | 899 | if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
cfang@1116 | 900 | UseSSE42Intrinsics = true; |
cfang@1116 | 901 | } |
cfang@1116 | 902 | } |
twisti@1020 | 903 | } |
kvn@7025 | 904 | if ((cpu_family() == 0x06) && |
kvn@7025 | 905 | ((extended_cpu_model() == 0x36) || // Centerton |
kvn@7025 | 906 | (extended_cpu_model() == 0x37) || // Silvermont |
kvn@7025 | 907 | (extended_cpu_model() == 0x4D))) { |
kvn@7025 | 908 | #ifdef COMPILER2 |
kvn@7025 | 909 | if (FLAG_IS_DEFAULT(OptoScheduling)) { |
kvn@7025 | 910 | OptoScheduling = true; |
kvn@7025 | 911 | } |
kvn@7025 | 912 | #endif |
kvn@7025 | 913 | if (supports_sse4_2()) { // Silvermont |
kvn@7025 | 914 | if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
kvn@7025 | 915 | UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
kvn@7025 | 916 | } |
kvn@7025 | 917 | } |
kvn@7025 | 918 | } |
kvn@7152 | 919 | if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { |
kvn@7152 | 920 | AllocatePrefetchInstr = 3; |
kvn@7152 | 921 | } |
twisti@1020 | 922 | } |
twisti@1020 | 923 | |
iveresov@6378 | 924 | // Use count leading zeros count instruction if available. |
iveresov@6378 | 925 | if (supports_lzcnt()) { |
iveresov@6378 | 926 | if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
iveresov@6378 | 927 | UseCountLeadingZerosInstruction = true; |
iveresov@6378 | 928 | } |
iveresov@6378 | 929 | } else if (UseCountLeadingZerosInstruction) { |
iveresov@6378 | 930 | warning("lzcnt instruction is not available on this CPU"); |
iveresov@6378 | 931 | FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
iveresov@6378 | 932 | } |
iveresov@6378 | 933 | |
kvn@7152 | 934 | // Use count trailing zeros instruction if available |
iveresov@6378 | 935 | if (supports_bmi1()) { |
kvn@7152 | 936 | // tzcnt does not require VEX prefix |
kvn@7152 | 937 | if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
kvn@7269 | 938 | if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
kvn@7269 | 939 | // Don't use tzcnt if BMI1 is switched off on command line. |
kvn@7269 | 940 | UseCountTrailingZerosInstruction = false; |
kvn@7269 | 941 | } else { |
kvn@7269 | 942 | UseCountTrailingZerosInstruction = true; |
kvn@7269 | 943 | } |
kvn@7152 | 944 | } |
kvn@7152 | 945 | } else if (UseCountTrailingZerosInstruction) { |
kvn@7152 | 946 | warning("tzcnt instruction is not available on this CPU"); |
kvn@7152 | 947 | FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
kvn@7152 | 948 | } |
kvn@7152 | 949 | |
kvn@7269 | 950 | // BMI instructions (except tzcnt) use an encoding with VEX prefix. |
kvn@7152 | 951 | // VEX prefix is generated only when AVX > 0. |
kvn@7152 | 952 | if (supports_bmi1() && supports_avx()) { |
iveresov@6378 | 953 | if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
iveresov@6378 | 954 | UseBMI1Instructions = true; |
iveresov@6378 | 955 | } |
iveresov@6378 | 956 | } else if (UseBMI1Instructions) { |
kvn@7152 | 957 | warning("BMI1 instructions are not available on this CPU (AVX is also required)"); |
iveresov@6378 | 958 | FLAG_SET_DEFAULT(UseBMI1Instructions, false); |
iveresov@6378 | 959 | } |
iveresov@6378 | 960 | |
kvn@7152 | 961 | if (supports_bmi2() && supports_avx()) { |
kvn@7152 | 962 | if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { |
kvn@7152 | 963 | UseBMI2Instructions = true; |
iveresov@6378 | 964 | } |
kvn@7152 | 965 | } else if (UseBMI2Instructions) { |
kvn@7152 | 966 | warning("BMI2 instructions are not available on this CPU (AVX is also required)"); |
kvn@7152 | 967 | FLAG_SET_DEFAULT(UseBMI2Instructions, false); |
iveresov@6378 | 968 | } |
iveresov@6378 | 969 | |
twisti@1078 | 970 | // Use population count instruction if available. |
twisti@1078 | 971 | if (supports_popcnt()) { |
twisti@1078 | 972 | if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
twisti@1078 | 973 | UsePopCountInstruction = true; |
twisti@1078 | 974 | } |
kvn@3388 | 975 | } else if (UsePopCountInstruction) { |
kvn@3388 | 976 | warning("POPCNT instruction is not available on this CPU"); |
kvn@3388 | 977 | FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
twisti@1078 | 978 | } |
twisti@1078 | 979 | |
kvn@4410 | 980 | // Use fast-string operations if available. |
kvn@4410 | 981 | if (supports_erms()) { |
kvn@4410 | 982 | if (FLAG_IS_DEFAULT(UseFastStosb)) { |
kvn@4410 | 983 | UseFastStosb = true; |
kvn@4410 | 984 | } |
kvn@4410 | 985 | } else if (UseFastStosb) { |
kvn@4410 | 986 | warning("fast-string operations are not available on this CPU"); |
kvn@4410 | 987 | FLAG_SET_DEFAULT(UseFastStosb, false); |
kvn@4410 | 988 | } |
kvn@4410 | 989 | |
kvn@4105 | 990 | #ifdef COMPILER2 |
kvn@4105 | 991 | if (FLAG_IS_DEFAULT(AlignVector)) { |
kvn@4105 | 992 | // Modern processors allow misaligned memory operations for vectors. |
kvn@4105 | 993 | AlignVector = !UseUnalignedLoadStores; |
kvn@4105 | 994 | } |
kvn@4105 | 995 | #endif // COMPILER2 |
kvn@4105 | 996 | |
twisti@1020 | 997 | assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 998 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 999 | |
twisti@1020 | 1000 | // set valid Prefetch instruction |
twisti@1020 | 1001 | if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
twisti@1020 | 1002 | if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
kvn@2761 | 1003 | if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
kvn@2761 | 1004 | if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; |
twisti@1020 | 1005 | |
twisti@1020 | 1006 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
twisti@1020 | 1007 | if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
kvn@2761 | 1008 | if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
kvn@2761 | 1009 | if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; |
twisti@1020 | 1010 | |
twisti@1020 | 1011 | // Allocation prefetch settings |
kvn@3052 | 1012 | intx cache_line_size = prefetch_data_size(); |
twisti@1020 | 1013 | if( cache_line_size > AllocatePrefetchStepSize ) |
twisti@1020 | 1014 | AllocatePrefetchStepSize = cache_line_size; |
kvn@3052 | 1015 | |
twisti@1020 | 1016 | assert(AllocatePrefetchLines > 0, "invalid value"); |
kvn@3052 | 1017 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 1018 | AllocatePrefetchLines = 3; |
kvn@3052 | 1019 | assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
kvn@3052 | 1020 | if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
kvn@3052 | 1021 | AllocateInstancePrefetchLines = 1; |
twisti@1020 | 1022 | |
twisti@1020 | 1023 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
twisti@1020 | 1024 | AllocatePrefetchStyle = allocate_prefetch_style(); |
twisti@1020 | 1025 | |
kvn@7025 | 1026 | if (is_intel() && cpu_family() == 6 && supports_sse3()) { |
kvn@7025 | 1027 | if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core |
twisti@1020 | 1028 | #ifdef _LP64 |
kvn@1977 | 1029 | AllocatePrefetchDistance = 384; |
twisti@1020 | 1030 | #else |
kvn@1977 | 1031 | AllocatePrefetchDistance = 320; |
twisti@1020 | 1032 | #endif |
kvn@1977 | 1033 | } |
kvn@7025 | 1034 | if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
kvn@1977 | 1035 | AllocatePrefetchDistance = 192; |
kvn@1977 | 1036 | AllocatePrefetchLines = 4; |
kvn@7025 | 1037 | } |
never@2085 | 1038 | #ifdef COMPILER2 |
kvn@7025 | 1039 | if (supports_sse4_2()) { |
kvn@7025 | 1040 | if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
never@2085 | 1041 | FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
never@2085 | 1042 | } |
kvn@7025 | 1043 | } |
never@2085 | 1044 | #endif |
twisti@1020 | 1045 | } |
twisti@1020 | 1046 | assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
twisti@1020 | 1047 | |
twisti@1020 | 1048 | #ifdef _LP64 |
twisti@1020 | 1049 | // Prefetch settings |
twisti@1020 | 1050 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
twisti@1020 | 1051 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
twisti@1020 | 1052 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
twisti@1020 | 1053 | #endif |
twisti@1020 | 1054 | |
jwilhelm@4430 | 1055 | if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
jwilhelm@4430 | 1056 | (cache_line_size > ContendedPaddingWidth)) |
jwilhelm@4430 | 1057 | ContendedPaddingWidth = cache_line_size; |
jwilhelm@4430 | 1058 | |
twisti@1020 | 1059 | #ifndef PRODUCT |
twisti@1020 | 1060 | if (PrintMiscellaneous && Verbose) { |
twisti@1020 | 1061 | tty->print_cr("Logical CPUs per core: %u", |
twisti@1020 | 1062 | logical_processors_per_package()); |
kevinw@8966 | 1063 | tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
drchase@6680 | 1064 | tty->print("UseSSE=%d", (int) UseSSE); |
kvn@3388 | 1065 | if (UseAVX > 0) { |
drchase@6680 | 1066 | tty->print(" UseAVX=%d", (int) UseAVX); |
kvn@3388 | 1067 | } |
kvn@4205 | 1068 | if (UseAES) { |
kvn@4205 | 1069 | tty->print(" UseAES=1"); |
kvn@4205 | 1070 | } |
kvn@6388 | 1071 | #ifdef COMPILER2 |
kvn@6388 | 1072 | if (MaxVectorSize > 0) { |
drchase@6680 | 1073 | tty->print(" MaxVectorSize=%d", (int) MaxVectorSize); |
kvn@6388 | 1074 | } |
kvn@6388 | 1075 | #endif |
kvn@3388 | 1076 | tty->cr(); |
kvn@3052 | 1077 | tty->print("Allocation"); |
kvn@2761 | 1078 | if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
kvn@3052 | 1079 | tty->print_cr(": no prefetching"); |
twisti@1020 | 1080 | } else { |
kvn@3052 | 1081 | tty->print(" prefetching: "); |
kvn@2761 | 1082 | if (UseSSE == 0 && supports_3dnow_prefetch()) { |
twisti@1020 | 1083 | tty->print("PREFETCHW"); |
twisti@1020 | 1084 | } else if (UseSSE >= 1) { |
twisti@1020 | 1085 | if (AllocatePrefetchInstr == 0) { |
twisti@1020 | 1086 | tty->print("PREFETCHNTA"); |
twisti@1020 | 1087 | } else if (AllocatePrefetchInstr == 1) { |
twisti@1020 | 1088 | tty->print("PREFETCHT0"); |
twisti@1020 | 1089 | } else if (AllocatePrefetchInstr == 2) { |
twisti@1020 | 1090 | tty->print("PREFETCHT2"); |
twisti@1020 | 1091 | } else if (AllocatePrefetchInstr == 3) { |
twisti@1020 | 1092 | tty->print("PREFETCHW"); |
twisti@1020 | 1093 | } |
twisti@1020 | 1094 | } |
twisti@1020 | 1095 | if (AllocatePrefetchLines > 1) { |
drchase@6680 | 1096 | tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
twisti@1020 | 1097 | } else { |
drchase@6680 | 1098 | tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
twisti@1020 | 1099 | } |
twisti@1020 | 1100 | } |
twisti@1020 | 1101 | |
twisti@1020 | 1102 | if (PrefetchCopyIntervalInBytes > 0) { |
drchase@6680 | 1103 | tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
twisti@1020 | 1104 | } |
twisti@1020 | 1105 | if (PrefetchScanIntervalInBytes > 0) { |
drchase@6680 | 1106 | tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
twisti@1020 | 1107 | } |
twisti@1020 | 1108 | if (PrefetchFieldsAhead > 0) { |
drchase@6680 | 1109 | tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
twisti@1020 | 1110 | } |
jwilhelm@4430 | 1111 | if (ContendedPaddingWidth > 0) { |
drchase@6680 | 1112 | tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
jwilhelm@4430 | 1113 | } |
twisti@1020 | 1114 | } |
twisti@1020 | 1115 | #endif // !PRODUCT |
twisti@1020 | 1116 | } |
twisti@1020 | 1117 | |
kvn@6429 | 1118 | bool VM_Version::use_biased_locking() { |
kvn@6429 | 1119 | #if INCLUDE_RTM_OPT |
kvn@6429 | 1120 | // RTM locking is most useful when there is high lock contention and |
kvn@6429 | 1121 | // low data contention. With high lock contention the lock is usually |
kvn@6429 | 1122 | // inflated and biased locking is not suitable for that case. |
kvn@6429 | 1123 | // RTM locking code requires that biased locking is off. |
kvn@6429 | 1124 | // Note: we can't switch off UseBiasedLocking in get_processor_features() |
kvn@6429 | 1125 | // because it is used by Thread::allocate() which is called before |
kvn@6429 | 1126 | // VM_Version::initialize(). |
kvn@6429 | 1127 | if (UseRTMLocking && UseBiasedLocking) { |
kvn@6429 | 1128 | if (FLAG_IS_DEFAULT(UseBiasedLocking)) { |
kvn@6429 | 1129 | FLAG_SET_DEFAULT(UseBiasedLocking, false); |
kvn@6429 | 1130 | } else { |
kvn@6429 | 1131 | warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); |
kvn@6429 | 1132 | UseBiasedLocking = false; |
kvn@6429 | 1133 | } |
kvn@6429 | 1134 | } |
kvn@6429 | 1135 | #endif |
kvn@6429 | 1136 | return UseBiasedLocking; |
kvn@6429 | 1137 | } |
kvn@6429 | 1138 | |
twisti@1020 | 1139 | void VM_Version::initialize() { |
twisti@1020 | 1140 | ResourceMark rm; |
twisti@1020 | 1141 | // Making this stub must be FIRST use of assembler |
twisti@1020 | 1142 | |
kvn@6537 | 1143 | stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); |
twisti@1020 | 1144 | if (stub_blob == NULL) { |
kvn@6537 | 1145 | vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); |
twisti@1020 | 1146 | } |
twisti@2103 | 1147 | CodeBuffer c(stub_blob); |
twisti@1020 | 1148 | VM_Version_StubGenerator g(&c); |
kvn@6537 | 1149 | get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, |
kvn@6537 | 1150 | g.generate_get_cpu_info()); |
twisti@1020 | 1151 | |
twisti@1020 | 1152 | get_processor_features(); |
twisti@1020 | 1153 | } |