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src/cpu/sparc/vm/vm_version_sparc.hpp@8c95980d0b66 (annotated)

src/cpu/sparc/vm/vm_version_sparc.hpp

Sat, 07 Nov 2020 10:30:02 +0800

author

aoqi

date

Sat, 07 Nov 2020 10:30:02 +0800

changeset 10026

8c95980d0b66

parent 8856

ac27a9c85bea

permissions

-rw-r--r--

Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f

aoqi@0	1	/*
kvn@7027	2	* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@0	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0	4	*
aoqi@0	5	* This code is free software; you can redistribute it and/or modify it
aoqi@0	6	* under the terms of the GNU General Public License version 2 only, as
aoqi@0	7	* published by the Free Software Foundation.
aoqi@0	8	*
aoqi@0	9	* This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0	12	* version 2 for more details (a copy is included in the LICENSE file that
aoqi@0	13	* accompanied this code).
aoqi@0	14	*
aoqi@0	15	* You should have received a copy of the GNU General Public License version
aoqi@0	16	* 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0	18	*
aoqi@0	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0	20	* or visit www.oracle.com if you need additional information or have any
aoqi@0	21	* questions.
aoqi@0	22	*
aoqi@0	23	*/
aoqi@0	24
aoqi@0	25	#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0	26	#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
aoqi@0	27
aoqi@0	28	#include "runtime/globals_extension.hpp"
aoqi@0	29	#include "runtime/vm_version.hpp"
aoqi@0	30
aoqi@0	31	class VM_Version: public Abstract_VM_Version {
aoqi@0	32	protected:
aoqi@0	33	enum Feature_Flag {
aoqi@0	34	v8_instructions = 0,
aoqi@0	35	hardware_mul32 = 1,
aoqi@0	36	hardware_div32 = 2,
aoqi@0	37	hardware_fsmuld = 3,
aoqi@0	38	hardware_popc = 4,
aoqi@0	39	v9_instructions = 5,
aoqi@0	40	vis1_instructions = 6,
aoqi@0	41	vis2_instructions = 7,
aoqi@0	42	sun4v_instructions = 8,
aoqi@0	43	blk_init_instructions = 9,
aoqi@0	44	fmaf_instructions = 10,
aoqi@0	45	fmau_instructions = 11,
aoqi@0	46	vis3_instructions = 12,
aoqi@0	47	cbcond_instructions = 13,
aoqi@0	48	sparc64_family = 14,
aoqi@0	49	M_family = 15,
kevinw@8733	50	S_family = 16,
kevinw@8733	51	T_family = 17,
kevinw@8733	52	T1_model = 18,
kevinw@8733	53	sparc5_instructions = 19,
kevinw@8733	54	aes_instructions = 20,
kevinw@8733	55	sha1_instruction = 21,
kevinw@8733	56	sha256_instruction = 22,
kevinw@8733	57	sha512_instruction = 23
aoqi@0	58	};
aoqi@0	59
aoqi@0	60	enum Feature_Flag_Set {
aoqi@0	61	unknown_m = 0,
aoqi@0	62	all_features_m = -1,
aoqi@0	63
aoqi@0	64	v8_instructions_m = 1 << v8_instructions,
aoqi@0	65	hardware_mul32_m = 1 << hardware_mul32,
aoqi@0	66	hardware_div32_m = 1 << hardware_div32,
aoqi@0	67	hardware_fsmuld_m = 1 << hardware_fsmuld,
aoqi@0	68	hardware_popc_m = 1 << hardware_popc,
aoqi@0	69	v9_instructions_m = 1 << v9_instructions,
aoqi@0	70	vis1_instructions_m = 1 << vis1_instructions,
aoqi@0	71	vis2_instructions_m = 1 << vis2_instructions,
aoqi@0	72	sun4v_m = 1 << sun4v_instructions,
aoqi@0	73	blk_init_instructions_m = 1 << blk_init_instructions,
aoqi@0	74	fmaf_instructions_m = 1 << fmaf_instructions,
aoqi@0	75	fmau_instructions_m = 1 << fmau_instructions,
aoqi@0	76	vis3_instructions_m = 1 << vis3_instructions,
aoqi@0	77	cbcond_instructions_m = 1 << cbcond_instructions,
aoqi@0	78	sparc64_family_m = 1 << sparc64_family,
aoqi@0	79	M_family_m = 1 << M_family,
kevinw@8733	80	S_family_m = 1 << S_family,
aoqi@0	81	T_family_m = 1 << T_family,
aoqi@0	82	T1_model_m = 1 << T1_model,
aoqi@0	83	sparc5_instructions_m = 1 << sparc5_instructions,
aoqi@0	84	aes_instructions_m = 1 << aes_instructions,
kvn@7027	85	sha1_instruction_m = 1 << sha1_instruction,
kvn@7027	86	sha256_instruction_m = 1 << sha256_instruction,
kvn@7027	87	sha512_instruction_m = 1 << sha512_instruction,
aoqi@0	88
aoqi@0	89	generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
aoqi@0	90	generic_v9_m = generic_v8_m | v9_instructions_m,
aoqi@0	91	ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
aoqi@0	92
aoqi@0	93	// Temporary until we have something more accurate
aoqi@0	94	niagara1_unique_m = sun4v_m,
aoqi@0	95	niagara1_m = generic_v9_m | niagara1_unique_m
aoqi@0	96	};
aoqi@0	97
aoqi@0	98	static int _features;
aoqi@0	99	static const char* _features_str;
aoqi@0	100
iveresov@7767	101	static unsigned int _L2_data_cache_line_size;
iveresov@7767	102	static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; }
iveresov@7135	103
aoqi@0	104	static void print_features();
aoqi@0	105	static int determine_features();
aoqi@0	106	static int platform_features(int features);
aoqi@0	107
aoqi@0	108	// Returns true if the platform is in the niagara line (T series)
aoqi@0	109	static bool is_M_family(int features) { return (features & M_family_m) != 0; }
kevinw@8733	110	static bool is_S_family(int features) { return (features & S_family_m) != 0; }
aoqi@0	111	static bool is_T_family(int features) { return (features & T_family_m) != 0; }
aoqi@0	112	static bool is_niagara() { return is_T_family(_features); }
aoqi@0	113	#ifdef ASSERT
aoqi@0	114	static bool is_niagara(int features) {
aoqi@0	115	// 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
aoqi@0	116	// on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
aoqi@0	117	return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
aoqi@0	118	}
aoqi@0	119	#endif
aoqi@0	120
aoqi@0	121	// Returns true if it is niagara1 (T1).
aoqi@0	122	static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
aoqi@0	123
aoqi@0	124	static int maximum_niagara1_processor_count() { return 32; }
kevinw@8731	125	static int parse_features(const char* implementation);
aoqi@0	126	public:
aoqi@0	127	// Initialization
aoqi@0	128	static void initialize();
aoqi@0	129
poonam@8329	130	static void init_before_ergo() { _features = determine_features(); }
poonam@8329	131
aoqi@0	132	// Instruction support
aoqi@0	133	static bool has_v8() { return (_features & v8_instructions_m) != 0; }
aoqi@0	134	static bool has_v9() { return (_features & v9_instructions_m) != 0; }
aoqi@0	135	static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
aoqi@0	136	static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
aoqi@0	137	static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
aoqi@0	138	static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
aoqi@0	139	static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
aoqi@0	140	static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
aoqi@0	141	static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
aoqi@0	142	static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
aoqi@0	143	static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
aoqi@0	144	static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
aoqi@0	145	static bool has_aes() { return (_features & aes_instructions_m) != 0; }
kvn@7027	146	static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
kvn@7027	147	static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
kvn@7027	148	static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
aoqi@0	149
aoqi@0	150	static bool supports_compare_and_exchange()
aoqi@0	151	{ return has_v9(); }
aoqi@0	152
aoqi@0	153	// Returns true if the platform is in the niagara line (T series)
aoqi@0	154	// and newer than the niagara1.
aoqi@0	155	static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
aoqi@0	156
aoqi@0	157	static bool is_M_series() { return is_M_family(_features); }
kevinw@8733	158	static bool is_S_series() { return is_S_family(_features); }
aoqi@0	159	static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
aoqi@0	160	static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
aoqi@0	161
aoqi@0	162	// Fujitsu SPARC64
aoqi@0	163	static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
aoqi@0	164
aoqi@0	165	static bool is_sun4v() { return (_features & sun4v_m) != 0; }
aoqi@0	166	static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
aoqi@0	167
aoqi@0	168	static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
aoqi@0	169	static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
aoqi@0	170
aoqi@0	171	// T4 and newer Sparc have fast RDPC instruction.
aoqi@0	172	static bool has_fast_rdpc() { return is_T4(); }
aoqi@0	173
aoqi@0	174	// On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
aoqi@0	175	static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
aoqi@0	176
aoqi@0	177	static const char* cpu_features() { return _features_str; }
aoqi@0	178
iveresov@7135	179	// default prefetch block size on sparc
iveresov@7767	180	static intx prefetch_data_size() { return L2_data_cache_line_size(); }
aoqi@0	181
aoqi@0	182	// Prefetch
aoqi@0	183	static intx prefetch_copy_interval_in_bytes() {
aoqi@0	184	intx interval = PrefetchCopyIntervalInBytes;
aoqi@0	185	return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0	186	}
aoqi@0	187	static intx prefetch_scan_interval_in_bytes() {
aoqi@0	188	intx interval = PrefetchScanIntervalInBytes;
aoqi@0	189	return interval >= 0 ? interval : (has_v9() ? 512 : 0);
aoqi@0	190	}
aoqi@0	191	static intx prefetch_fields_ahead() {
aoqi@0	192	intx count = PrefetchFieldsAhead;
aoqi@0	193	return count >= 0 ? count : (is_ultra3() ? 1 : 0);
aoqi@0	194	}
aoqi@0	195
aoqi@0	196	static intx allocate_prefetch_distance() {
aoqi@0	197	// This method should be called before allocate_prefetch_style().
aoqi@0	198	intx count = AllocatePrefetchDistance;
aoqi@0	199	if (count < 0) { // default is not defined ?
aoqi@0	200	count = 512;
aoqi@0	201	}
aoqi@0	202	return count;
aoqi@0	203	}
aoqi@0	204	static intx allocate_prefetch_style() {
aoqi@0	205	assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
aoqi@0	206	// Return 0 if AllocatePrefetchDistance was not defined.
aoqi@0	207	return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
aoqi@0	208	}
aoqi@0	209
aoqi@0	210	// Assembler testing
aoqi@0	211	static void allow_all();
aoqi@0	212	static void revert();
aoqi@0	213
aoqi@0	214	// Override the Abstract_VM_Version implementation.
aoqi@0	215	static uint page_size_count() { return is_sun4v() ? 4 : 2; }
aoqi@0	216
aoqi@0	217	// Calculates the number of parallel threads
aoqi@0	218	static unsigned int calc_parallel_worker_threads();
aoqi@0	219	};
aoqi@0	220
aoqi@0	221	#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP