Fri, 17 Mar 2017 07:52:54 -0700
8134119: Use new API to get cache line sizes
Summary: Using new sysconf and sysinfo API on Solaris 12, avoid using libpicl and libkstat.
Reviewed-by: kvn
duke@435 | 1 | /* |
kvn@7027 | 2 | * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
stefank@2314 | 26 | #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
stefank@2314 | 27 | |
stefank@2314 | 28 | #include "runtime/globals_extension.hpp" |
stefank@2314 | 29 | #include "runtime/vm_version.hpp" |
stefank@2314 | 30 | |
duke@435 | 31 | class VM_Version: public Abstract_VM_Version { |
duke@435 | 32 | protected: |
duke@435 | 33 | enum Feature_Flag { |
kvn@3037 | 34 | v8_instructions = 0, |
kvn@3037 | 35 | hardware_mul32 = 1, |
kvn@3037 | 36 | hardware_div32 = 2, |
kvn@3037 | 37 | hardware_fsmuld = 3, |
kvn@3037 | 38 | hardware_popc = 4, |
kvn@3037 | 39 | v9_instructions = 5, |
kvn@3037 | 40 | vis1_instructions = 6, |
kvn@3037 | 41 | vis2_instructions = 7, |
kvn@3037 | 42 | sun4v_instructions = 8, |
kvn@2269 | 43 | blk_init_instructions = 9, |
kvn@3037 | 44 | fmaf_instructions = 10, |
kvn@3037 | 45 | fmau_instructions = 11, |
kvn@3037 | 46 | vis3_instructions = 12, |
kvn@3972 | 47 | cbcond_instructions = 13, |
kvn@3972 | 48 | sparc64_family = 14, |
kvn@3972 | 49 | M_family = 15, |
kvn@3972 | 50 | T_family = 16, |
kvn@6312 | 51 | T1_model = 17, |
jmasa@6325 | 52 | sparc5_instructions = 18, |
kvn@7027 | 53 | aes_instructions = 19, |
kvn@7027 | 54 | sha1_instruction = 20, |
kvn@7027 | 55 | sha256_instruction = 21, |
kvn@7027 | 56 | sha512_instruction = 22 |
duke@435 | 57 | }; |
duke@435 | 58 | |
duke@435 | 59 | enum Feature_Flag_Set { |
twisti@1076 | 60 | unknown_m = 0, |
twisti@1076 | 61 | all_features_m = -1, |
duke@435 | 62 | |
kvn@3037 | 63 | v8_instructions_m = 1 << v8_instructions, |
kvn@3037 | 64 | hardware_mul32_m = 1 << hardware_mul32, |
kvn@3037 | 65 | hardware_div32_m = 1 << hardware_div32, |
kvn@3037 | 66 | hardware_fsmuld_m = 1 << hardware_fsmuld, |
kvn@3037 | 67 | hardware_popc_m = 1 << hardware_popc, |
kvn@3037 | 68 | v9_instructions_m = 1 << v9_instructions, |
kvn@3037 | 69 | vis1_instructions_m = 1 << vis1_instructions, |
kvn@3037 | 70 | vis2_instructions_m = 1 << vis2_instructions, |
kvn@3037 | 71 | sun4v_m = 1 << sun4v_instructions, |
kvn@2269 | 72 | blk_init_instructions_m = 1 << blk_init_instructions, |
kvn@3037 | 73 | fmaf_instructions_m = 1 << fmaf_instructions, |
kvn@3037 | 74 | fmau_instructions_m = 1 << fmau_instructions, |
kvn@3037 | 75 | vis3_instructions_m = 1 << vis3_instructions, |
kvn@3972 | 76 | cbcond_instructions_m = 1 << cbcond_instructions, |
kvn@3037 | 77 | sparc64_family_m = 1 << sparc64_family, |
kvn@3972 | 78 | M_family_m = 1 << M_family, |
kvn@3037 | 79 | T_family_m = 1 << T_family, |
kvn@3037 | 80 | T1_model_m = 1 << T1_model, |
jmasa@6325 | 81 | sparc5_instructions_m = 1 << sparc5_instructions, |
kvn@6312 | 82 | aes_instructions_m = 1 << aes_instructions, |
kvn@7027 | 83 | sha1_instruction_m = 1 << sha1_instruction, |
kvn@7027 | 84 | sha256_instruction_m = 1 << sha256_instruction, |
kvn@7027 | 85 | sha512_instruction_m = 1 << sha512_instruction, |
duke@435 | 86 | |
twisti@1076 | 87 | generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
twisti@1076 | 88 | generic_v9_m = generic_v8_m | v9_instructions_m, |
twisti@1076 | 89 | ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
duke@435 | 90 | |
duke@435 | 91 | // Temporary until we have something more accurate |
twisti@1076 | 92 | niagara1_unique_m = sun4v_m, |
twisti@1076 | 93 | niagara1_m = generic_v9_m | niagara1_unique_m |
duke@435 | 94 | }; |
duke@435 | 95 | |
duke@435 | 96 | static int _features; |
duke@435 | 97 | static const char* _features_str; |
duke@435 | 98 | |
iveresov@7767 | 99 | static unsigned int _L2_data_cache_line_size; |
iveresov@7767 | 100 | static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; } |
iveresov@7135 | 101 | |
duke@435 | 102 | static void print_features(); |
duke@435 | 103 | static int determine_features(); |
duke@435 | 104 | static int platform_features(int features); |
duke@435 | 105 | |
kvn@2403 | 106 | // Returns true if the platform is in the niagara line (T series) |
kvn@3972 | 107 | static bool is_M_family(int features) { return (features & M_family_m) != 0; } |
kvn@2403 | 108 | static bool is_T_family(int features) { return (features & T_family_m) != 0; } |
kvn@2403 | 109 | static bool is_niagara() { return is_T_family(_features); } |
simonis@6154 | 110 | #ifdef ASSERT |
simonis@6154 | 111 | static bool is_niagara(int features) { |
simonis@6154 | 112 | // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as |
simonis@6154 | 113 | // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'. |
simonis@6154 | 114 | return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0; |
simonis@6154 | 115 | } |
simonis@6154 | 116 | #endif |
kvn@2403 | 117 | |
kvn@2403 | 118 | // Returns true if it is niagara1 (T1). |
kvn@2403 | 119 | static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } |
duke@435 | 120 | |
jmasa@445 | 121 | static int maximum_niagara1_processor_count() { return 32; } |
kevinw@8731 | 122 | static int parse_features(const char* implementation); |
duke@435 | 123 | public: |
duke@435 | 124 | // Initialization |
duke@435 | 125 | static void initialize(); |
duke@435 | 126 | |
poonam@8329 | 127 | static void init_before_ergo() { _features = determine_features(); } |
poonam@8329 | 128 | |
duke@435 | 129 | // Instruction support |
duke@435 | 130 | static bool has_v8() { return (_features & v8_instructions_m) != 0; } |
duke@435 | 131 | static bool has_v9() { return (_features & v9_instructions_m) != 0; } |
twisti@1076 | 132 | static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } |
twisti@1076 | 133 | static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
duke@435 | 134 | static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
twisti@1078 | 135 | static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
duke@435 | 136 | static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
duke@435 | 137 | static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } |
kvn@2403 | 138 | static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } |
kvn@2269 | 139 | static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } |
kvn@3037 | 140 | static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } |
jmasa@6325 | 141 | static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; } |
kvn@6312 | 142 | static bool has_aes() { return (_features & aes_instructions_m) != 0; } |
kvn@7027 | 143 | static bool has_sha1() { return (_features & sha1_instruction_m) != 0; } |
kvn@7027 | 144 | static bool has_sha256() { return (_features & sha256_instruction_m) != 0; } |
kvn@7027 | 145 | static bool has_sha512() { return (_features & sha512_instruction_m) != 0; } |
duke@435 | 146 | |
duke@435 | 147 | static bool supports_compare_and_exchange() |
duke@435 | 148 | { return has_v9(); } |
duke@435 | 149 | |
kvn@2403 | 150 | // Returns true if the platform is in the niagara line (T series) |
kvn@2403 | 151 | // and newer than the niagara1. |
kvn@2403 | 152 | static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } |
twisti@4108 | 153 | |
twisti@4108 | 154 | static bool is_M_series() { return is_M_family(_features); } |
kvn@3052 | 155 | static bool is_T4() { return is_T_family(_features) && has_cbcond(); } |
jmasa@6325 | 156 | static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); } |
kvn@3037 | 157 | |
kvn@2403 | 158 | // Fujitsu SPARC64 |
kvn@2403 | 159 | static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } |
duke@435 | 160 | |
kvn@3037 | 161 | static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
kvn@3037 | 162 | static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } |
kvn@3037 | 163 | |
kvn@2403 | 164 | static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } |
kvn@2403 | 165 | static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } |
kvn@3052 | 166 | |
kvn@3037 | 167 | // T4 and newer Sparc have fast RDPC instruction. |
kvn@3052 | 168 | static bool has_fast_rdpc() { return is_T4(); } |
kvn@3052 | 169 | |
kvn@3092 | 170 | // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. |
kvn@3092 | 171 | static bool has_block_zeroing() { return has_blk_init() && is_T4(); } |
duke@435 | 172 | |
duke@435 | 173 | static const char* cpu_features() { return _features_str; } |
duke@435 | 174 | |
iveresov@7135 | 175 | // default prefetch block size on sparc |
iveresov@7767 | 176 | static intx prefetch_data_size() { return L2_data_cache_line_size(); } |
duke@435 | 177 | |
duke@435 | 178 | // Prefetch |
duke@435 | 179 | static intx prefetch_copy_interval_in_bytes() { |
duke@435 | 180 | intx interval = PrefetchCopyIntervalInBytes; |
duke@435 | 181 | return interval >= 0 ? interval : (has_v9() ? 512 : 0); |
duke@435 | 182 | } |
duke@435 | 183 | static intx prefetch_scan_interval_in_bytes() { |
duke@435 | 184 | intx interval = PrefetchScanIntervalInBytes; |
duke@435 | 185 | return interval >= 0 ? interval : (has_v9() ? 512 : 0); |
duke@435 | 186 | } |
duke@435 | 187 | static intx prefetch_fields_ahead() { |
duke@435 | 188 | intx count = PrefetchFieldsAhead; |
duke@435 | 189 | return count >= 0 ? count : (is_ultra3() ? 1 : 0); |
duke@435 | 190 | } |
duke@435 | 191 | |
duke@435 | 192 | static intx allocate_prefetch_distance() { |
duke@435 | 193 | // This method should be called before allocate_prefetch_style(). |
duke@435 | 194 | intx count = AllocatePrefetchDistance; |
duke@435 | 195 | if (count < 0) { // default is not defined ? |
duke@435 | 196 | count = 512; |
duke@435 | 197 | } |
duke@435 | 198 | return count; |
duke@435 | 199 | } |
duke@435 | 200 | static intx allocate_prefetch_style() { |
duke@435 | 201 | assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); |
duke@435 | 202 | // Return 0 if AllocatePrefetchDistance was not defined. |
duke@435 | 203 | return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; |
duke@435 | 204 | } |
duke@435 | 205 | |
duke@435 | 206 | // Assembler testing |
duke@435 | 207 | static void allow_all(); |
duke@435 | 208 | static void revert(); |
duke@435 | 209 | |
duke@435 | 210 | // Override the Abstract_VM_Version implementation. |
duke@435 | 211 | static uint page_size_count() { return is_sun4v() ? 4 : 2; } |
jmasa@445 | 212 | |
jmasa@445 | 213 | // Calculates the number of parallel threads |
jmasa@445 | 214 | static unsigned int calc_parallel_worker_threads(); |
duke@435 | 215 | }; |
stefank@2314 | 216 | |
stefank@2314 | 217 | #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP |