jdk8-mips64-public/hotspot: src/cpu/mips/vm/assembler

src/cpu/mips/vm/assembler_mips.cpp@76b73e112cb7 (annotated)

src/cpu/mips/vm/assembler_mips.cpp

Tue, 24 Oct 2017 14:04:09 +0800

author: fujie
date: Tue, 24 Oct 2017 14:04:09 +0800
changeset 8001: 76b73e112cb7
parent 6880: 52ea28d233d2
child 8004: 941851413ebf
permissions: -rw-r--r--

[Assembler] Complex address modes support for Assembler::lea(Register rt, Address src), Assembler::sd(Register rt, Address dst) and Assembler::sw(Register rt, Address dst)

 /*
  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 only, as
  * published by the Free Software Foundation.
  *
  * This code is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * version 2 for more details (a copy is included in the LICENSE file that
  * accompanied this code).
  *
  * You should have received a copy of the GNU General Public License version
  * 2 along with this work; if not, write to the Free Software Foundation,
  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  *
  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  * or visit www.oracle.com if you need additional information or have any
  * questions.
  *
  */
 #include "precompiled.hpp"
 #include "asm/assembler.hpp"
 #include "asm/assembler.inline.hpp"
 #include "gc_interface/collectedHeap.inline.hpp"
 #include "interpreter/interpreter.hpp"
 #include "memory/cardTableModRefBS.hpp"
 #include "memory/resourceArea.hpp"
 #include "prims/methodHandles.hpp"
 #include "runtime/biasedLocking.hpp"
 #include "runtime/interfaceSupport.hpp"
 #include "runtime/objectMonitor.hpp"
 #include "runtime/os.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
 #if INCLUDE_ALL_GCS
 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
 #include "gc_implementation/g1/heapRegion.hpp"
 #endif // INCLUDE_ALL_GCS
 #ifdef PRODUCT
 #define BLOCK_COMMENT(str) /* nothing */
 #define STOP(error) stop(error)
 #else
 #define BLOCK_COMMENT(str) block_comment(str)
 #define STOP(error) block_comment(error); stop(error)
 #endif
 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
 // Implementation of AddressLiteral
 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
   _is_lval = false;
   _target = target;
   _rspec = rspec_from_rtype(rtype, target);
 }
 // Implementation of Address
 Address Address::make_array(ArrayAddress adr) {
   AddressLiteral base = adr.base();
   Address index = adr.index();
   assert(index._disp == 0, "must not have disp"); // maybe it can?
   Address array(index._base, index._index, index._scale, (intptr_t) base.target());
   array._rspec = base._rspec;
   return array;
 }
 // exceedingly dangerous constructor
 Address::Address(address loc, RelocationHolder spec) {
   _base  = noreg;
   _index = noreg;
   _scale = no_scale;
   _disp  = (intptr_t) loc;
   _rspec = spec;
 }
 // Implementation of Assembler
 const char *Assembler::ops_name[] = {
   "special",  "regimm",   "j",      "jal",    "beq",      "bne",      "blez",   "bgtz",
   "addi",     "addiu",    "slti",   "sltiu",  "andi",     "ori",      "xori",   "lui",
   "cop0",     "cop1",     "cop2",   "cop3",   "beql",     "bnel",     "bleql",  "bgtzl",
   "daddi",    "daddiu",   "ldl",    "ldr",    "",         "",         "",       "",
   "lb",       "lh",       "lwl",    "lw",     "lbu",      "lhu",      "lwr",    "lwu",
   "sb",       "sh",       "swl",    "sw",     "sdl",      "sdr",      "swr",    "cache",
   "ll",       "lwc1",     "",       "",       "lld",      "ldc1",     "",       "ld",
   "sc",       "swc1",     "",       "",       "scd",      "sdc1",     "",       "sd"
 };
 const char* Assembler::special_name[] = {
   "sll",      "",         "srl",      "sra",      "sllv",     "",         "srlv",     "srav",
   "jr",       "jalr",     "movz",     "movn",     "syscall",  "break",    "",         "sync",
   "mfhi",     "mthi",     "mflo",     "mtlo",     "dsll",     "",         "dsrl",     "dsra",
   "mult",     "multu",    "div",      "divu",     "dmult",    "dmultu",   "ddiv",     "ddivu",
   "add",      "addu",     "sub",      "subu",     "and",      "or",       "xor",      "nor",
   "",         "",         "slt",      "sltu",     "dadd",     "daddu",    "dsub",     "dsubu",
   "tge",      "tgeu",     "tlt",      "tltu",     "teq",      "",         "tne",      "",
   "dsll",     "",         "dsrl",     "dsra",     "dsll32",   "",         "dsrl32",   "dsra32"
 };
 const char* Assembler::cop1_name[] = {
   "add",      "sub",      "mul",      "div",      "sqrt",     "abs",      "mov",      "neg",
   "round.l",  "trunc.l",  "ceil.l",   "floor.l",  "round.w",  "trunc.w",  "ceil.w",   "floor.w",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "c.f",      "c.un",     "c.eq",     "c.ueq",    "c.olt",    "c.ult",    "c.ole",    "c.ule",
   "c.sf",     "c.ngle",   "c.seq",    "c.ngl",    "c.lt",     "c.nge",    "c.le",     "c.ngt"
 };
 const char* Assembler::cop1x_name[] = {
   "lwxc1", "ldxc1",       "",         "",         "",    "luxc1",         "",         "",
   "swxc1", "sdxc1",       "",         "",         "",    "suxc1",         "",    "prefx",
   "",         "",         "",         "",         "",         "",  "alnv.ps",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "madd.s",   "madd.d",   "",         "",         "",         "",  "madd.ps",         "",
   "msub.s",   "msub.d",   "",         "",         "",         "",  "msub.ps",         "",
   "nmadd.s", "nmadd.d",   "",         "",         "",         "", "nmadd.ps",         "",
   "nmsub.s", "nmsub.d",   "",         "",         "",         "", "nmsub.ps",         ""
 };
 const char* Assembler::special2_name[] = {
   "madd",     "",         "mul",      "",         "msub",     "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "gsdmult",  "",         "",         "gsdiv",    "gsddiv",   "",         "",
   "",         "",         "",         "",         "gsmod",    "gsdmod",   "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         ""
 };
 const char* Assembler::special3_name[] = {
   "ext",      "",         "",         "",      "ins",    "dinsm",    "dinsu",     "dins",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "bshfl",    "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
   "",         "",         "",         "",         "",         "",         "",         "",
 };
 const char* Assembler::regimm_name[] = {
   "bltz",     "bgez",     "bltzl",    "bgezl",    "",         "",         "",         "",
   "tgei",     "tgeiu",    "tlti",     "tltiu",    "teqi",     "",         "tnei",     "",
   "bltzal",   "bgezal",   "bltzall",  "bgezall"
 };
 const char* Assembler::gs_ldc2_name[] = {
   "gslbx",    "gslhx",    "gslwx",    "gsldx",    "",         "",         "gslwxc1",  "gsldxc1"
 };
 const char* Assembler::gs_lwc2_name[] = {
         "",       "",       "",       "",         "",         "",         "",         "",
         "",       "",       "",       "",         "",         "",         "",         "",
         "gslble", "gslbgt", "gslhle", "gslhgt",   "gslwle",   "gslwgt",   "gsldle",   "gsldgt",
         "",       "",       "",       "gslwlec1", "gslwgtc1", "gsldlec1", "gsldgtc1", "",/*LWDIR, LWPTE, LDDIR and LDPTE have the same low 6 bits.*/
         "gslq",   ""
 };
 const char* Assembler::gs_sdc2_name[] = {
   "gssbx",    "gsshx",    "gsswx",    "gssdx",    "",         "",         "gsswxc1",  "gssdxc1"
 };
 const char* Assembler::gs_swc2_name[] = {
         "",        "",        "",        "",        "",          "",          "",         "",
         "",        "",        "",        "",        "",          "",          "",         "",
         "gssble",  "gssbgt",  "gsshle",  "gsshgt",  "gsswle",    "gsswgt",    "gssdle",   "gssdgt",
         "",        "",        "",        "",        "gsswlec1",  "gsswgtc1",  "gssdlec1", "gssdgtc1",
         "gssq",    ""
 };
 //misleading name, print only branch/jump instruction
 void Assembler::print_instruction(int inst) {
   const char *s;
   switch( opcode(inst) ) {
   default:
     s = ops_name[opcode(inst)];
     break;
   case special_op:
     s = special_name[special(inst)];
     break;
   case regimm_op:
     s = special_name[rt(inst)];
     break;
   }
   ::tty->print("%s", s);
 }
 int Assembler::is_int_mask(int x) {
    int xx = x;
    int count = 0;
    while (x != 0) {
       x &= (x - 1);
       count++;
    }
    if ((1<<count) == (xx+1)) {
       return count;
    } else {
       return -1;
    }
 }
 int Assembler::is_jlong_mask(jlong x) {
    jlong  xx = x;
    int count = 0;
    while (x != 0) {
       x &= (x - 1);
       count++;
    }
    if ((1<<count) == (xx+1)) {
       return count;
    } else {
       return -1;
    }
 }
 //without check, maybe fixed
 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
   int v = (dest_pos - inst_pos - 4)>>2;
   switch(opcode(inst)) {
   case j_op:
   case jal_op:
     assert(false, "should not use j/jal here");
     break;
   default:
     assert(is_simm16(v), "must be simm16");
 #ifndef PRODUCT
     if(!is_simm16(v))
     {
       tty->print_cr("must be simm16");
       tty->print_cr("Inst: %lx", inst);
     }
 #endif
     v = low16(v);
     inst &= 0xffff0000;
     break;
   }
   return inst | v;
 }
 int Assembler::branch_destination(int inst, int pos) {
   int off;
   switch(opcode(inst)) {
   case j_op:
   case jal_op:
     assert(false, "should not use j/jal here");
     break;
   default:
     off = expand(low16(inst), 15);
     break;
   }
   return off ? pos + 4 + (off<<2) : 0;
 }
 int AbstractAssembler::code_fill_byte() {
     return 0x00;                  // illegal instruction 0x00000000
 }
 // Now the Assembler instruction (identical for 32/64 bits)
 void Assembler::lb(Register rt, Address src) {
   lb(rt, src.base(), src.disp());
 }
 void Assembler::lbu(Register rt, Address src) {
   lbu(rt, src.base(), src.disp());
 }
 void Assembler::ld(Register rt, Address src){
   ld(rt, src.base(), src.disp());
 }
 void Assembler::ldl(Register rt, Address src){
   ldl(rt, src.base(), src.disp());
 }
 void Assembler::ldr(Register rt, Address src){
   ldr(rt, src.base(), src.disp());
 }
 void Assembler::lh(Register rt, Address src){
   lh(rt, src.base(), src.disp());
 }
 void Assembler::lhu(Register rt, Address src){
   lhu(rt, src.base(), src.disp());
 }
 void Assembler::ll(Register rt, Address src){
   ll(rt, src.base(), src.disp());
 }
 void Assembler::lld(Register rt, Address src){
   lld(rt, src.base(), src.disp());
 }
 void Assembler::lw(Register rt, Address src){
   lw(rt, src.base(), src.disp());
 }
 void Assembler::lea(Register rt, Address src) {
   Register dst   = rt;
   Register base  = src.base();
   Register index = src.index();
   int scale = src.scale();
   int disp  = src.disp();
   if (index == noreg) {
     if (is_simm16(disp)) {
       daddiu(dst, base, disp);
     } else {
       lui(AT, split_low(disp >> 16));
       if (split_low(disp)) ori(AT, AT, split_low(disp));
       daddu(dst, base, AT);
     }
   } else {
     if (scale == 0) {
       if (is_simm16(disp)) {
         daddu(AT, base, index);
         daddiu(dst, AT, disp);
       } else {
         lui(AT, split_low(disp >> 16));
         if (split_low(disp)) ori(AT, AT, split_low(disp));
         daddu(AT, base, AT);
         daddu(dst, AT, index);
       }
     } else {
       if (is_simm16(disp)) {
         dsll(AT, index, scale);
         daddu(AT, AT, base);
         daddiu(dst, AT, disp);
       } else {
         lui(AT, split_low(disp >> 16));
         if (split_low(disp)) ori(AT, AT, split_low(disp));
         daddu(AT, AT, base);
         dsll(dst, index, scale);
         daddu(dst, dst, AT);
       }
     }
   }
 }
 void Assembler::lwl(Register rt, Address src){
   lwl(rt, src.base(), src.disp());
 }
 void Assembler::lwr(Register rt, Address src){
   lwr(rt, src.base(), src.disp());
 }
 void Assembler::lwu(Register rt, Address src){
   lwu(rt, src.base(), src.disp());
 }
 void Assembler::sb(Register rt, Address dst) {
   sb(rt, dst.base(), dst.disp());
 }
 void Assembler::sc(Register rt, Address dst) {
   sc(rt, dst.base(), dst.disp());
 }
 void Assembler::scd(Register rt, Address dst) {
   scd(rt, dst.base(), dst.disp());
 }
 void Assembler::sd(Register rt, Address dst) {
   Register src   = rt;
   Register base  = dst.base();
   Register index = dst.index();
   int scale = dst.scale();
   int disp  = dst.disp();
   if(index != noreg) {
     if(is_simm16(disp)) {
       if( UseLoongsonISA && is_simm(disp, 8)) {
         if (scale == 0) {
           gssdx(src, base, index, disp);
         } else {
           dsll(AT, index, scale);
           gssdx(src, base, AT, disp);
         }
       } else {
         if (scale == 0) {
           daddu(AT, base, index);
         } else {
           dsll(AT, index, scale);
           daddu(AT, base, AT);
         }
         sd(src, AT, disp);
       }
     } else {
       if (scale == 0) {
         lui(AT, split_low(disp >> 16));
         if (split_low(disp)) ori(AT, AT, split_low(disp));
         daddu(AT, AT, base);
         if(UseLoongsonISA) {
           gssdx(src, AT, index, 0);
         } else {
           daddu(AT, AT, index);
           sd(src, AT, 0);
         }
       } else {
         dsll(AT, index, scale);
         daddu(AT, base, AT);
         lui(T9, split_low(disp >> 16));
         if (split_low(disp)) ori(T9, T9, split_low(disp));
         if(UseLoongsonISA) {
           gssdx(src, AT, T9, 0);
         } else {
           daddu(AT, AT, T9);
           sd(src, AT, 0);
         }
       }
     }
   } else {
     if(is_simm16(disp)) {
       sd(src, base, disp);
     } else {
       lui(AT, split_low(disp >> 16));
       if (split_low(disp)) ori(AT, AT, split_low(disp));
       if(UseLoongsonISA) {
         gssdx(src, base, AT, 0);
       } else {
         daddu(AT, base, AT);
         sd(src, AT, 0);
       }
     }
   }
 }
 void Assembler::sdl(Register rt, Address dst) {
   sdl(rt, dst.base(), dst.disp());
 }
 void Assembler::sdr(Register rt, Address dst) {
   sdr(rt, dst.base(), dst.disp());
 }
 void Assembler::sh(Register rt, Address dst) {
   sh(rt, dst.base(), dst.disp());
 }
 void Assembler::sw(Register rt, Address dst) {
   Register src   = rt;
   Register base  = dst.base();
   Register index = dst.index();
   int scale = dst.scale();
   int disp  = dst.disp();
   if(index != noreg) {
     if( Assembler::is_simm16(disp) ) {
       if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
         if (scale == 0) {
           gsswx(src, base, index, disp);
         } else {
           dsll(AT, index, scale);
           gsswx(src, base, AT, disp);
         }
       } else {
         if (scale == 0) {
           daddu(AT, base, index);
         } else {
           dsll(AT, index, scale);
           daddu(AT, base, AT);
         }
         sw(src, AT, disp);
       }
     } else {
       if (scale == 0) {
         lui(AT, split_low(disp >> 16));
         if (split_low(disp)) ori(AT, AT, split_low(disp));
         daddu(AT, AT, base);
         if( UseLoongsonISA ) {
           gsswx(src, AT, index, 0);
         } else {
           daddu(AT, AT, index);
           sw(src, AT, 0);
         }
       } else {
         dsll(AT, index, scale);
         daddu(AT, base, AT);
         lui(T9, split_low(disp >> 16));
         if (split_low(disp)) ori(T9, T9, split_low(disp));
         if( UseLoongsonISA ) {
           gsswx(src, AT, T9, 0);
         } else {
           daddu(AT, AT, T9);
           sw(src, AT, 0);
         }
       }
     }
   } else {
     if( Assembler::is_simm16(disp) ) {
       sw(src, base, disp);
     } else {
       lui(AT, split_low(disp >> 16));
       if (split_low(disp)) ori(AT, AT, split_low(disp));
       if( UseLoongsonISA ) {
         gsswx(src, base, AT, 0);
       } else {
         daddu(AT, base, AT);
         sw(src, AT, 0);
       }
     }
   }
 }
 void Assembler::swl(Register rt, Address dst) {
   swl(rt, dst.base(), dst.disp());
 }
 void Assembler::swr(Register rt, Address dst) {
   swr(rt, dst.base(), dst.disp());
 }
 void Assembler::lwc1(FloatRegister rt, Address src) {
   lwc1(rt, src.base(), src.disp());
 }
 void Assembler::ldc1(FloatRegister rt, Address src) {
   ldc1(rt, src.base(), src.disp());
 }
 void Assembler::swc1(FloatRegister rt, Address dst) {
   swc1(rt, dst.base(), dst.disp());
 }
 void Assembler::sdc1(FloatRegister rt, Address dst) {
   sdc1(rt, dst.base(), dst.disp());
 }
 void Assembler::j(address entry) {
 #ifdef MIPS64
   int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xfffffffff0000000))>>2;
 #else
   int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xf0000000))>>2;
 #endif
   emit_long((j_op<<26) | dest);
   has_delay_slot();
 }
 void Assembler::jal(address entry) {
 #ifdef MIPS64
   int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xfffffffff0000000))>>2;
 #else
   int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xf0000000))>>2;
 #endif
   emit_long((jal_op<<26) | dest);
   has_delay_slot();
 }
 class ControlWord {
         public:
                 int32_t _value;
   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
   int  precision_control() const       { return  (_value >>  8) & 3      ; }
   bool precision() const               { return ((_value >>  5) & 1) != 0; }
   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
   void print() const {
     // rounding control
     const char* rc;
     switch (rounding_control()) {
       case 0: rc = "round near"; break;
       case 1: rc = "round down"; break;
       case 2: rc = "round up  "; break;
       case 3: rc = "chop      "; break;
     };
     // precision control
     const char* pc;
     switch (precision_control()) {
       case 0: pc = "24 bits "; break;
       case 1: pc = "reserved"; break;
       case 2: pc = "53 bits "; break;
       case 3: pc = "64 bits "; break;
     };
     // flags
     char f[9];
     f[0] = ' ';
     f[1] = ' ';
     f[2] = (precision   ()) ? 'P' : 'p';
     f[3] = (underflow   ()) ? 'U' : 'u';
     f[4] = (overflow    ()) ? 'O' : 'o';
     f[5] = (zero_divide ()) ? 'Z' : 'z';
     f[6] = (denormalized()) ? 'D' : 'd';
     f[7] = (invalid     ()) ? 'I' : 'i';
     f[8] = '\x0';
     // output
     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
   }
 };
 class StatusWord {
  public:
   int32_t _value;
   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
   int  top() const                     { return  (_value >> 11) & 7      ; }
   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
   bool precision() const               { return ((_value >>  5) & 1) != 0; }
   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
   void print() const {
     // condition codes
     char c[5];
     c[0] = (C3()) ? '3' : '-';
     c[1] = (C2()) ? '2' : '-';
     c[2] = (C1()) ? '1' : '-';
     c[3] = (C0()) ? '0' : '-';
     c[4] = '\x0';
     // flags
     char f[9];
     f[0] = (error_status()) ? 'E' : '-';
     f[1] = (stack_fault ()) ? 'S' : '-';
     f[2] = (precision   ()) ? 'P' : '-';
     f[3] = (underflow   ()) ? 'U' : '-';
     f[4] = (overflow    ()) ? 'O' : '-';
     f[5] = (zero_divide ()) ? 'Z' : '-';
     f[6] = (denormalized()) ? 'D' : '-';
     f[7] = (invalid     ()) ? 'I' : '-';
     f[8] = '\x0';
     // output
     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
   }
 };
 class TagWord {
  public:
   int32_t _value;
   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
   void print() const {
     printf("%04x", _value & 0xFFFF);
   }
 };
 class FPU_Register {
  public:
   int32_t _m0;
   int32_t _m1;
   int16_t _ex;
   bool is_indefinite() const           {
     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
   }
   void print() const {
     char  sign = (_ex < 0) ? '-' : '+';
     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
   };
 };
 class FPU_State {
  public:
   enum {
     register_size       = 10,
     number_of_registers =  8,
     register_mask       =  7
   };
   ControlWord  _control_word;
   StatusWord   _status_word;
   TagWord      _tag_word;
   int32_t      _error_offset;
   int32_t      _error_selector;
   int32_t      _data_offset;
   int32_t      _data_selector;
   int8_t       _register[register_size * number_of_registers];
   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
   const char* tag_as_string(int tag) const {
     switch (tag) {
       case 0: return "valid";
       case 1: return "zero";
       case 2: return "special";
       case 3: return "empty";
     }
     ShouldNotReachHere();
     return NULL;
   }
   void print() const {
     // print computation registers
     { int t = _status_word.top();
       for (int i = 0; i < number_of_registers; i++) {
         int j = (i - t) & register_mask;
         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
         st(j)->print();
         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
       }
     }
     printf("\n");
     // print control registers
     printf("ctrl = "); _control_word.print(); printf("\n");
     printf("stat = "); _status_word .print(); printf("\n");
     printf("tags = "); _tag_word    .print(); printf("\n");
   }
 };
 class Flag_Register {
  public:
   int32_t _value;
   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
   bool direction() const               { return ((_value >> 10) & 1) != 0; }
   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
   void print() const {
     // flags
     char f[8];
     f[0] = (overflow       ()) ? 'O' : '-';
     f[1] = (direction      ()) ? 'D' : '-';
     f[2] = (sign           ()) ? 'S' : '-';
     f[3] = (zero           ()) ? 'Z' : '-';
     f[4] = (auxiliary_carry()) ? 'A' : '-';
     f[5] = (parity         ()) ? 'P' : '-';
     f[6] = (carry          ()) ? 'C' : '-';
     f[7] = '\x0';
     // output
     printf("%08x  flags = %s", _value, f);
   }
 };
 class IU_Register {
  public:
   int32_t _value;
   void print() const {
     printf("%08x  %11d", _value, _value);
   }
 };
 class IU_State {
  public:
   Flag_Register _eflags;
   IU_Register   _rdi;
   IU_Register   _rsi;
   IU_Register   _rbp;
   IU_Register   _rsp;
   IU_Register   _rbx;
   IU_Register   _rdx;
   IU_Register   _rcx;
   IU_Register   _rax;
   void print() const {
     // computation registers
     printf("rax,  = "); _rax.print(); printf("\n");
     printf("rbx,  = "); _rbx.print(); printf("\n");
     printf("rcx  = "); _rcx.print(); printf("\n");
     printf("rdx  = "); _rdx.print(); printf("\n");
     printf("rdi  = "); _rdi.print(); printf("\n");
     printf("rsi  = "); _rsi.print(); printf("\n");
     printf("rbp,  = "); _rbp.print(); printf("\n");
     printf("rsp  = "); _rsp.print(); printf("\n");
     printf("\n");
     // control registers
     printf("flgs = "); _eflags.print(); printf("\n");
   }
 };
 class CPU_State {
  public:
   FPU_State _fpu_state;
   IU_State  _iu_state;
   void print() const {
     printf("--------------------------------------------------\n");
     _iu_state .print();
     printf("\n");
     _fpu_state.print();
     printf("--------------------------------------------------\n");
   }
 };

Mercurial > jdk8-mips64-public > hotspot / annotate

src/cpu/mips/vm/assembler_mips.cpp@76b73e112cb7 (annotated)

src/cpu/mips/vm/assembler_mips.cpp