Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/cpu/mips/vm/assembler_mips.cpp
src/cpu/mips/vm/assembler_mips.cpp
- changeset 8001
- 76b73e112cb7
- parent 6880
- 52ea28d233d2
- child 8004
- 941851413ebf
equal
deleted
inserted
replaced
| 8000:1510f9dcc0fa | 8001:76b73e112cb7 |
|---|---|
| 317 | 317 |
| 318 void Assembler::lw(Register rt, Address src){ | 318 void Assembler::lw(Register rt, Address src){ |
| 319 lw(rt, src.base(), src.disp()); | 319 lw(rt, src.base(), src.disp()); |
| 320 } | 320 } |
| 321 void Assembler::lea(Register rt, Address src) { | 321 void Assembler::lea(Register rt, Address src) { |
| 322 #ifdef _LP64 | 322 Register dst = rt; |
| 323 daddi(rt, src.base(), src.disp()); | 323 Register base = src.base(); |
| 324 #else | 324 Register index = src.index(); |
| 325 addi(rt, src.base(), src.disp()); | 325 |
| 326 #endif | 326 int scale = src.scale(); |
| 327 int disp = src.disp(); | |
| 328 | |
| 329 if (index == noreg) { | |
| 330 if (is_simm16(disp)) { | |
| 331 daddiu(dst, base, disp); | |
| 332 } else { | |
| 333 lui(AT, split_low(disp >> 16)); | |
| 334 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 335 daddu(dst, base, AT); | |
| 336 } | |
| 337 } else { | |
| 338 if (scale == 0) { | |
| 339 if (is_simm16(disp)) { | |
| 340 daddu(AT, base, index); | |
| 341 daddiu(dst, AT, disp); | |
| 342 } else { | |
| 343 lui(AT, split_low(disp >> 16)); | |
| 344 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 345 daddu(AT, base, AT); | |
| 346 daddu(dst, AT, index); | |
| 347 } | |
| 348 } else { | |
| 349 if (is_simm16(disp)) { | |
| 350 dsll(AT, index, scale); | |
| 351 daddu(AT, AT, base); | |
| 352 daddiu(dst, AT, disp); | |
| 353 } else { | |
| 354 lui(AT, split_low(disp >> 16)); | |
| 355 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 356 daddu(AT, AT, base); | |
| 357 dsll(dst, index, scale); | |
| 358 daddu(dst, dst, AT); | |
| 359 } | |
| 360 } | |
| 361 } | |
| 327 } | 362 } |
| 328 | 363 |
| 329 void Assembler::lwl(Register rt, Address src){ | 364 void Assembler::lwl(Register rt, Address src){ |
| 330 lwl(rt, src.base(), src.disp()); | 365 lwl(rt, src.base(), src.disp()); |
| 331 } | 366 } |
| 349 void Assembler::scd(Register rt, Address dst) { | 384 void Assembler::scd(Register rt, Address dst) { |
| 350 scd(rt, dst.base(), dst.disp()); | 385 scd(rt, dst.base(), dst.disp()); |
| 351 } | 386 } |
| 352 | 387 |
| 353 void Assembler::sd(Register rt, Address dst) { | 388 void Assembler::sd(Register rt, Address dst) { |
| 354 sd(rt, dst.base(), dst.disp()); | 389 Register src = rt; |
| 390 Register base = dst.base(); | |
| 391 Register index = dst.index(); | |
| 392 | |
| 393 int scale = dst.scale(); | |
| 394 int disp = dst.disp(); | |
| 395 | |
| 396 if(index != noreg) { | |
| 397 if(is_simm16(disp)) { | |
| 398 if( UseLoongsonISA && is_simm(disp, 8)) { | |
| 399 if (scale == 0) { | |
| 400 gssdx(src, base, index, disp); | |
| 401 } else { | |
| 402 dsll(AT, index, scale); | |
| 403 gssdx(src, base, AT, disp); | |
| 404 } | |
| 405 } else { | |
| 406 if (scale == 0) { | |
| 407 daddu(AT, base, index); | |
| 408 } else { | |
| 409 dsll(AT, index, scale); | |
| 410 daddu(AT, base, AT); | |
| 411 } | |
| 412 sd(src, AT, disp); | |
| 413 } | |
| 414 } else { | |
| 415 if (scale == 0) { | |
| 416 lui(AT, split_low(disp >> 16)); | |
| 417 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 418 daddu(AT, AT, base); | |
| 419 if(UseLoongsonISA) { | |
| 420 gssdx(src, AT, index, 0); | |
| 421 } else { | |
| 422 daddu(AT, AT, index); | |
| 423 sd(src, AT, 0); | |
| 424 } | |
| 425 } else { | |
| 426 dsll(AT, index, scale); | |
| 427 daddu(AT, base, AT); | |
| 428 lui(T9, split_low(disp >> 16)); | |
| 429 if (split_low(disp)) ori(T9, T9, split_low(disp)); | |
| 430 if(UseLoongsonISA) { | |
| 431 gssdx(src, AT, T9, 0); | |
| 432 } else { | |
| 433 daddu(AT, AT, T9); | |
| 434 sd(src, AT, 0); | |
| 435 } | |
| 436 } | |
| 437 } | |
| 438 } else { | |
| 439 if(is_simm16(disp)) { | |
| 440 sd(src, base, disp); | |
| 441 } else { | |
| 442 lui(AT, split_low(disp >> 16)); | |
| 443 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 444 | |
| 445 if(UseLoongsonISA) { | |
| 446 gssdx(src, base, AT, 0); | |
| 447 } else { | |
| 448 daddu(AT, base, AT); | |
| 449 sd(src, AT, 0); | |
| 450 } | |
| 451 } | |
| 452 } | |
| 355 } | 453 } |
| 356 | 454 |
| 357 void Assembler::sdl(Register rt, Address dst) { | 455 void Assembler::sdl(Register rt, Address dst) { |
| 358 sdl(rt, dst.base(), dst.disp()); | 456 sdl(rt, dst.base(), dst.disp()); |
| 359 } | 457 } |
| 365 void Assembler::sh(Register rt, Address dst) { | 463 void Assembler::sh(Register rt, Address dst) { |
| 366 sh(rt, dst.base(), dst.disp()); | 464 sh(rt, dst.base(), dst.disp()); |
| 367 } | 465 } |
| 368 | 466 |
| 369 void Assembler::sw(Register rt, Address dst) { | 467 void Assembler::sw(Register rt, Address dst) { |
| 370 sw(rt, dst.base(), dst.disp()); | 468 Register src = rt; |
| 469 Register base = dst.base(); | |
| 470 Register index = dst.index(); | |
| 471 | |
| 472 int scale = dst.scale(); | |
| 473 int disp = dst.disp(); | |
| 474 | |
| 475 if(index != noreg) { | |
| 476 if( Assembler::is_simm16(disp) ) { | |
| 477 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { | |
| 478 if (scale == 0) { | |
| 479 gsswx(src, base, index, disp); | |
| 480 } else { | |
| 481 dsll(AT, index, scale); | |
| 482 gsswx(src, base, AT, disp); | |
| 483 } | |
| 484 } else { | |
| 485 if (scale == 0) { | |
| 486 daddu(AT, base, index); | |
| 487 } else { | |
| 488 dsll(AT, index, scale); | |
| 489 daddu(AT, base, AT); | |
| 490 } | |
| 491 sw(src, AT, disp); | |
| 492 } | |
| 493 } else { | |
| 494 if (scale == 0) { | |
| 495 lui(AT, split_low(disp >> 16)); | |
| 496 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 497 daddu(AT, AT, base); | |
| 498 if( UseLoongsonISA ) { | |
| 499 gsswx(src, AT, index, 0); | |
| 500 } else { | |
| 501 daddu(AT, AT, index); | |
| 502 sw(src, AT, 0); | |
| 503 } | |
| 504 } else { | |
| 505 dsll(AT, index, scale); | |
| 506 daddu(AT, base, AT); | |
| 507 lui(T9, split_low(disp >> 16)); | |
| 508 if (split_low(disp)) ori(T9, T9, split_low(disp)); | |
| 509 if( UseLoongsonISA ) { | |
| 510 gsswx(src, AT, T9, 0); | |
| 511 } else { | |
| 512 daddu(AT, AT, T9); | |
| 513 sw(src, AT, 0); | |
| 514 } | |
| 515 } | |
| 516 } | |
| 517 } else { | |
| 518 if( Assembler::is_simm16(disp) ) { | |
| 519 sw(src, base, disp); | |
| 520 } else { | |
| 521 lui(AT, split_low(disp >> 16)); | |
| 522 if (split_low(disp)) ori(AT, AT, split_low(disp)); | |
| 523 | |
| 524 if( UseLoongsonISA ) { | |
| 525 gsswx(src, base, AT, 0); | |
| 526 } else { | |
| 527 daddu(AT, base, AT); | |
| 528 sw(src, AT, 0); | |
| 529 } | |
| 530 } | |
| 531 } | |
| 371 } | 532 } |
| 372 | 533 |
| 373 void Assembler::swl(Register rt, Address dst) { | 534 void Assembler::swl(Register rt, Address dst) { |
| 374 swl(rt, dst.base(), dst.disp()); | 535 swl(rt, dst.base(), dst.disp()); |
| 375 } | 536 } |
